diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 4b6228b0cf8..6b0114dcb7f 100755 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -48,5 +48,5 @@ CHIP_ASRCS = CHIP_CSRCS = stm32_start.c stm32_rcc.c stm32_gpio.c stm32_idle.c \ stm32_irq.c stm32_timerisr.c stm32_dma.c stm32_lowputc.c \ stm32_serial.c stm32_spi.c stm32_usbdev.c stm32_sdio.c \ - stm32_tim.c stm32_i2c.c stm32_waste.c + stm32_tim.c stm32_i2c.c stm32_pwr.c stm32_rtc.c stm32_waste.c diff --git a/arch/arm/src/stm32/chip/stm32_bkp.h b/arch/arm/src/stm32/chip/stm32_bkp.h new file mode 100644 index 00000000000..1788bdee08e --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32_bkp.h @@ -0,0 +1,190 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32_bkp.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_BKP_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_BKP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define CONFIG_STM32_NBKP_BYTES 84 +# define CONFIG_STM32_NBKP_REGS 42 +#else +# define CONFIG_STM32_NBKP_BYTES 20 +# define CONFIG_STM32_NBKP_REGS 10 +#endif + +/* Register Offsets *****************************************************************/ + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_BKP_DR_OFFSET(n) ((n) > 10 ? 0x0040+4*((n)-10) : 0x0004+4*(n)) +#else +# define STM32_BKP_DR_OFFSET(n) (0x0004+4*(n)) +#endif + +#define STM32_BKP_DR1_OFFSET 0x0004 /* Backup data register 1 */ +#define STM32_BKP_DR2_OFFSET 0x0008 /* Backup data register 2 */ +#define STM32_BKP_DR3_OFFSET 0x000c /* Backup data register 3 */ +#define STM32_BKP_DR4_OFFSET 0x0010 /* Backup data register 4 */ +#define STM32_BKP_DR5_OFFSET 0x0014 /* Backup data register 5 */ +#define STM32_BKP_DR6_OFFSET 0x0018 /* Backup data register 6 */ +#define STM32_BKP_DR7_OFFSET 0x001c /* Backup data register 7 */ +#define STM32_BKP_DR8_OFFSET 0x0020 /* Backup data register 8 */ +#define STM32_BKP_DR9_OFFSET 0x0024 /* Backup data register 9 */ +#define STM32_BKP_DR10_OFFSET 0x0028 /* Backup data register 10 */ + +#define STM32_BKP_RTCCR_OFFSET 0x002c /* RTC clock calibration register */ +#define STM32_BKP_CR_OFFSET 0x0030 /* Backup control register */ +#define STM32_BKP_CSR_OFFSET 0x0034 /* Backup control/status register */ + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_BKP_DR11_OFFSET 0x0040 /* Backup data register 11 */ +# define STM32_BKP_DR12_OFFSET 0x0044 /* Backup data register 12 */ +# define STM32_BKP_DR13_OFFSET 0x0048 /* Backup data register 13 */ +# define STM32_BKP_DR14_OFFSET 0x004c /* Backup data register 14 */ +# define STM32_BKP_DR15_OFFSET 0x0050 /* Backup data register 15 */ +# define STM32_BKP_DR16_OFFSET 0x0054 /* Backup data register 16 */ +# define STM32_BKP_DR17_OFFSET 0x0058 /* Backup data register 17 */ +# define STM32_BKP_DR18_OFFSET 0x005c /* Backup data register 18 */ +# define STM32_BKP_DR19_OFFSET 0x0060 /* Backup data register 19 */ +# define STM32_BKP_DR20_OFFSET 0x0064 /* Backup data register 20 */ +# define STM32_BKP_DR21_OFFSET 0x0068 /* Backup data register 21 */ +# define STM32_BKP_DR22_OFFSET 0x006c /* Backup data register 22 */ +# define STM32_BKP_DR23_OFFSET 0x0070 /* Backup data register 23 */ +# define STM32_BKP_DR24_OFFSET 0x0074 /* Backup data register 24 */ +# define STM32_BKP_DR25_OFFSET 0x0078 /* Backup data register 25 */ +# define STM32_BKP_DR26_OFFSET 0x007c /* Backup data register 26 */ +# define STM32_BKP_DR27_OFFSET 0x0080 /* Backup data register 27 */ +# define STM32_BKP_DR28_OFFSET 0x0084 /* Backup data register 28 */ +# define STM32_BKP_DR29_OFFSET 0x0088 /* Backup data register 29 */ +# define STM32_BKP_DR30_OFFSET 0x008c /* Backup data register 30 */ +# define STM32_BKP_DR31_OFFSET 0x0090 /* Backup data register 31 */ +# define STM32_BKP_DR32_OFFSET 0x0094 /* Backup data register 32 */ +# define STM32_BKP_DR33_OFFSET 0x0098 /* Backup data register 33 */ +# define STM32_BKP_DR34_OFFSET 0x009c /* Backup data register 34 */ +# define STM32_BKP_DR35_OFFSET 0x00a0 /* Backup data register 35 */ +# define STM32_BKP_DR36_OFFSET 0x00a4 /* Backup data register 36 */ +# define STM32_BKP_DR37_OFFSET 0x00a8 /* Backup data register 37 */ +# define STM32_BKP_DR38_OFFSET 0x00ac /* Backup data register 38 */ +# define STM32_BKP_DR39_OFFSET 0x00b0 /* Backup data register 39 */ +# define STM32_BKP_DR40_OFFSET 0x00b4 /* Backup data register 40 */ +# define STM32_BKP_DR41_OFFSET 0x00b8 /* Backup data register 41 */ +# define STM32_BKP_DR42_OFFSET 0x00bc /* Backup data register 42 */ +#endif + +/* Register Addresses ***************************************************************/ + +#define STM32_BKP_RTCCR (STM32_BKP_BASE+STM32_BKP_RTCCR_OFFSET) +#define STM32_BKP_CR (STM32_BKP_BASE+STM32_BKP_CR_OFFSET) +#define STM32_BKP_CSR (STM32_BKP_BASE+STM32_BKP_CSR_OFFSET) + +#define STM32_BKP_DR(n) (STM32_BKP_BASE+STM32_BKP_DR_OFFSET(n)) +#define STM32_BKP_DR1 (STM32_BKP_BASE+STM32_BKP_DR1_OFFSET) +#define STM32_BKP_DR2 (STM32_BKP_BASE+STM32_BKP_DR2_OFFSET) +#define STM32_BKP_DR3 (STM32_BKP_BASE+STM32_BKP_DR3_OFFSET) +#define STM32_BKP_DR4 (STM32_BKP_BASE+STM32_BKP_DR4_OFFSET) +#define STM32_BKP_DR5 (STM32_BKP_BASE+STM32_BKP_DR5_OFFSET) +#define STM32_BKP_DR6 (STM32_BKP_BASE+STM32_BKP_DR6_OFFSET) +#define STM32_BKP_DR7 (STM32_BKP_BASE+STM32_BKP_DR7_OFFSET) +#define STM32_BKP_DR8 (STM32_BKP_BASE+STM32_BKP_DR8_OFFSET) +#define STM32_BKP_DR9 (STM32_BKP_BASE+STM32_BKP_DR9_OFFSET) +#define STM32_BKP_DR10 (STM32_BKP_BASE+STM32_BKP_DR10_OFFSET) + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_BKP_DR11 (STM32_BKP_BASE+STM32_BKP_DR11_OFFSET) +# define STM32_BKP_DR12 (STM32_BKP_BASE+STM32_BKP_DR12_OFFSET) +# define STM32_BKP_DR13 (STM32_BKP_BASE+STM32_BKP_DR13_OFFSET) +# define STM32_BKP_DR14 (STM32_BKP_BASE+STM32_BKP_DR14_OFFSET) +# define STM32_BKP_DR15 (STM32_BKP_BASE+STM32_BKP_DR15_OFFSET) +# define STM32_BKP_DR16 (STM32_BKP_BASE+STM32_BKP_DR16_OFFSET) +# define STM32_BKP_DR17 (STM32_BKP_BASE+STM32_BKP_DR17_OFFSET) +# define STM32_BKP_DR18 (STM32_BKP_BASE+STM32_BKP_DR18_OFFSET) +# define STM32_BKP_DR19 (STM32_BKP_BASE+STM32_BKP_DR19_OFFSET) +# define STM32_BKP_DR20 (STM32_BKP_BASE+STM32_BKP_DR20_OFFSET) +# define STM32_BKP_DR21 (STM32_BKP_BASE+STM32_BKP_DR21_OFFSET) +# define STM32_BKP_DR22 (STM32_BKP_BASE+STM32_BKP_DR22_OFFSET) +# define STM32_BKP_DR23 (STM32_BKP_BASE+STM32_BKP_DR23_OFFSET) +# define STM32_BKP_DR24 (STM32_BKP_BASE+STM32_BKP_DR24_OFFSET) +# define STM32_BKP_DR25 (STM32_BKP_BASE+STM32_BKP_DR25_OFFSET) +# define STM32_BKP_DR26 (STM32_BKP_BASE+STM32_BKP_DR26_OFFSET) +# define STM32_BKP_DR27 (STM32_BKP_BASE+STM32_BKP_DR27_OFFSET) +# define STM32_BKP_DR28 (STM32_BKP_BASE+STM32_BKP_DR28_OFFSET) +# define STM32_BKP_DR29 (STM32_BKP_BASE+STM32_BKP_DR29_OFFSET) +# define STM32_BKP_DR30 (STM32_BKP_BASE+STM32_BKP_DR30_OFFSET) +# define STM32_BKP_DR31 (STM32_BKP_BASE+STM32_BKP_DR31_OFFSET) +# define STM32_BKP_DR32 (STM32_BKP_BASE+STM32_BKP_DR32_OFFSET) +# define STM32_BKP_DR33 (STM32_BKP_BASE+STM32_BKP_DR33_OFFSET) +# define STM32_BKP_DR34 (STM32_BKP_BASE+STM32_BKP_DR34_OFFSET) +# define STM32_BKP_DR35 (STM32_BKP_BASE+STM32_BKP_DR35_OFFSET) +# define STM32_BKP_DR36 (STM32_BKP_BASE+STM32_BKP_DR36_OFFSET) +# define STM32_BKP_DR37 (STM32_BKP_BASE+STM32_BKP_DR37_OFFSET) +# define STM32_BKP_DR38 (STM32_BKP_BASE+STM32_BKP_DR38_OFFSET) +# define STM32_BKP_DR39 (STM32_BKP_BASE+STM32_BKP_DR39_OFFSET) +# define STM32_BKP_DR40 (STM32_BKP_BASE+STM32_BKP_DR40_OFFSET) +# define STM32_BKP_DR41 (STM32_BKP_BASE+STM32_BKP_DR41_OFFSET) +# define STM32_BKP_DR42 (STM32_BKP_BASE+STM32_BKP_DR42_OFFSET) +#endif + +/* Register Bitfield Definitions ****************************************************/ + +/* RTC clock calibration register */ + +#define BKP_RTCCR_CAL_SHIFT (0) /* Bits 6-0: Calibration value */ +#define BKP_RTCCR_CAL_MASK (0x7f << BKP_RTCCR_CAL_SHIFT) +#define BKP_RTCCR_CCO (1 << 7) /* Bit 7: Calibration Clock Output */ +#define BKP_RTCCR_ASOE (1 << 8) /* Bit 8: Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS (1 << 9) /* Bit 9: Alarm or Second Output Selection */ + +/* Backup control register */ + +#define BKP_CR_TPE (1 << 0) /* Bit 0: TAMPER pin enable */ +#define BKP_CR_TPAL (1 << 1) /* Bit 1: TAMPER pin active level */ + +/* Backup control/status register */ + +#define BKP_CSR_CTE (1 << 0) /* Bit 0: Clear Tamper event */ +#define BKP_CSR_CTI (1 << 1) /* Bit 1: Clear Tamper Interrupt */ +#define BKP_CSR_TPIE (1 << 2) /* Bit 2: TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF (1 << 8) /* Bit 8: Tamper Event Flag */ +#define BKP_CSR_TIF (1 << 9) /* Bit 9: Tamper Interrupt Flag */ + +/* Backup data register */ + +#define BKP_DR_SHIFT (0) /* Bits 1510: Backup data */ +#define BKP_DR_MASK (0xffff << BKP_DR_SHIFT) + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_BKP_H */ diff --git a/arch/arm/src/stm32/chip/stm32_pwr.h b/arch/arm/src/stm32/chip/stm32_pwr.h new file mode 100644 index 00000000000..8066845af8c --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32_pwr.h @@ -0,0 +1,79 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32_pwr.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_PWR_CR_OFFSET 0x0000 /* Power control register */ +#define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */ + +/* Register Addresses ***************************************************************/ + + +/* Register Bitfield Definitions ****************************************************/ + +/* Power control register */ + +#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep */ +#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */ +#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */ +#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */ +#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */ +#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */ +#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT) +# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */ +# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */ +# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */ +# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */ +# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */ +# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */ +# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */ +# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */ +#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ + +/* Power control/status register */ + +#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */ +#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */ +#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */ +#define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */ + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H */ diff --git a/arch/arm/src/stm32/chip/stm32_rtc.h b/arch/arm/src/stm32/chip/stm32_rtc.h new file mode 100644 index 00000000000..b9fe3d8f33b --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32_rtc.h @@ -0,0 +1,96 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32_rtc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_RTC_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_RTC_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_RTC_CRH_OFFSET 0x0000 /* RTC control register High (16-bit) */ +#define STM32_RTC_CRL_OFFSET 0x0004 /* RTC control register low (16-bit) */ +#define STM32_RTC_PRLH_OFFSET 0x0008 /* RTC prescaler load register high (16-bit) */ +#define STM32_RTC_PRLL_OFFSET 0x000c /* RTC prescaler load register low (16-bit) */ +#define STM32_RTC_DIVH_OFFSET 0x0010 /* RTC prescaler divider register high (16-bit) */ +#define STM32_RTC_DIVL_OFFSET 0x0014 /* RTC prescaler divider register low (16-bit) */ +#define STM32_RTC_CNTH_OFFSET 0x0018 /* RTC counter register high (16-bit) */ +#define STM32_RTC_CNTL_OFFSET 0x001c /* RTC counter register low (16-bit) */ +#define STM32_RTC_ALRH_OFFSET 0x0020 /* RTC alarm register high (16-bit) */ +#define STM32_RTC_ALRL_OFFSET 0x0024 /* RTC alarm register low (16-bit) */ + +/* Register Addresses ***************************************************************/ + +#define STM32_RTC_CRH (STM32_RTC_BASE+STM32_RTC_CRH_OFFSET) +#define STM32_RTC_CRL (STM32_RTC_BASE+STM32_RTC_CRL_OFFSET) +#define STM32_RTC_PRLH (STM32_RTC_BASE+STM32_RTC_PRLH_OFFSET) +#define STM32_RTC_PRLL (STM32_RTC_BASE+STM32_RTC_PRLL_OFFSET) +#define STM32_RTC_DIVH (STM32_RTC_BASE+STM32_RTC_DIVH_OFFSET) +#define STM32_RTC_DIVL (STM32_RTC_BASE+STM32_RTC_DIVL_OFFSET) +#define STM32_RTC_CNTH (STM32_RTC_BASE+STM32_RTC_CNTH_OFFSET) +#define STM32_RTC_CNTL (STM32_RTC_BASE+STM32_RTC_CNTL_OFFSET) +#define STM32_RTC_ALRH (STM32_RTC_BASE+STM32_RTC_ALRH_OFFSET) +#define STM32_RTC_ALRL (STM32_RTC_BASE+STM32_RTC_ALRL_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* RTC control register High (16-bit) */ + +#define RTC_CRH_SECIE (1 << 0) /* Bit 0 : Second Interrupt Enable */ +#define RTC_CRH_ALRIE (1 << 1) /* Bit 1: Alarm Interrupt Enable */ +#define RTC_CRH_OWIE (1 << 2) /* Bit 2: OverfloW Interrupt Enable */ + +/* RTC control register low (16-bit) */ + +#define RTC_CRL_SECF (1 << 0) /* Bit 0: Second Flag */ +#define RTC_CRL_ALRF (1 << 1) /* Bit 1: Alarm Flag */ +#define RTC_CRL_OWF (1 << 2) /* Bit 2: Overflow Flag */ +#define RTC_CRL_RSF (1 << 3) /* Bit 3: Registers Synchronized Flag */ +#define RTC_CRL_CNF (1 << 4) /* Bit 4: Configuration Flag */ +#define RTC_CRL_RTOFF (1 << 5) /* Bit 5: RTC operation OFF */ + +/* RTC prescaler load register high (16-bit) */ + +#define RTC_PRLH_PRL_SHIFT (0) /* Bits 3-0: RTC Prescaler Reload Value High */ +#define RTC_PRLH_PRL_MASK (0x0f << RTC_PRLH_PRL_SHIFT) + +/* RTC prescaler divider register high (16-bit) */ + +#define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */ +#define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT) + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_RTC_H */ diff --git a/arch/arm/src/stm32/stm32.h b/arch/arm/src/stm32/stm32.h index 2845d4e5f66..999af048a38 100644 --- a/arch/arm/src/stm32/stm32.h +++ b/arch/arm/src/stm32/stm32.h @@ -67,7 +67,7 @@ #include "chip.h" #include "stm32_adc.h" -#include "stm32_bkp.h" +//#include "stm32_bkp.h" #include "stm32_can.h" #include "stm32_dgbmcu.h" #include "stm32_dma.h" diff --git a/arch/arm/src/stm32/stm32_bkp.h b/arch/arm/src/stm32/stm32_bkp.h index fd69240e407..8436dbf62b7 100644 --- a/arch/arm/src/stm32/stm32_bkp.h +++ b/arch/arm/src/stm32/stm32_bkp.h @@ -43,168 +43,6 @@ #include #include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define CONFIG_STM32_NBKP_BYTES 84 -# define CONFIG_STM32_NBKP_REGS 42 -#else -# define CONFIG_STM32_NBKP_BYTES 20 -# define CONFIG_STM32_NBKP_REGS 10 -#endif - -/* Register Offsets *****************************************************************/ - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_BKP_DR_OFFSET(n) ((n) > 10 ? 0x0040+4*((n)-10) : 0x0004+4*(n)) -#else -# define STM32_BKP_DR_OFFSET(n) (0x0004+4*(n)) -#endif - -#define STM32_BKP_DR1_OFFSET 0x0004 /* Backup data register 1 */ -#define STM32_BKP_DR2_OFFSET 0x0008 /* Backup data register 2 */ -#define STM32_BKP_DR3_OFFSET 0x000c /* Backup data register 3 */ -#define STM32_BKP_DR4_OFFSET 0x0010 /* Backup data register 4 */ -#define STM32_BKP_DR5_OFFSET 0x0014 /* Backup data register 5 */ -#define STM32_BKP_DR6_OFFSET 0x0018 /* Backup data register 6 */ -#define STM32_BKP_DR7_OFFSET 0x001c /* Backup data register 7 */ -#define STM32_BKP_DR8_OFFSET 0x0020 /* Backup data register 8 */ -#define STM32_BKP_DR9_OFFSET 0x0024 /* Backup data register 9 */ -#define STM32_BKP_DR10_OFFSET 0x0028 /* Backup data register 10 */ - -#define STM32_BKP_RTCCR_OFFSET 0x002c /* RTC clock calibration register */ -#define STM32_BKP_CR_OFFSET 0x0030 /* Backup control register */ -#define STM32_BKP_CSR_OFFSET 0x0034 /* Backup control/status register */ - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_BKP_DR11_OFFSET 0x0040 /* Backup data register 11 */ -# define STM32_BKP_DR12_OFFSET 0x0044 /* Backup data register 12 */ -# define STM32_BKP_DR13_OFFSET 0x0048 /* Backup data register 13 */ -# define STM32_BKP_DR14_OFFSET 0x004c /* Backup data register 14 */ -# define STM32_BKP_DR15_OFFSET 0x0050 /* Backup data register 15 */ -# define STM32_BKP_DR16_OFFSET 0x0054 /* Backup data register 16 */ -# define STM32_BKP_DR17_OFFSET 0x0058 /* Backup data register 17 */ -# define STM32_BKP_DR18_OFFSET 0x005c /* Backup data register 18 */ -# define STM32_BKP_DR19_OFFSET 0x0060 /* Backup data register 19 */ -# define STM32_BKP_DR20_OFFSET 0x0064 /* Backup data register 20 */ -# define STM32_BKP_DR21_OFFSET 0x0068 /* Backup data register 21 */ -# define STM32_BKP_DR22_OFFSET 0x006c /* Backup data register 22 */ -# define STM32_BKP_DR23_OFFSET 0x0070 /* Backup data register 23 */ -# define STM32_BKP_DR24_OFFSET 0x0074 /* Backup data register 24 */ -# define STM32_BKP_DR25_OFFSET 0x0078 /* Backup data register 25 */ -# define STM32_BKP_DR26_OFFSET 0x007c /* Backup data register 26 */ -# define STM32_BKP_DR27_OFFSET 0x0080 /* Backup data register 27 */ -# define STM32_BKP_DR28_OFFSET 0x0084 /* Backup data register 28 */ -# define STM32_BKP_DR29_OFFSET 0x0088 /* Backup data register 29 */ -# define STM32_BKP_DR30_OFFSET 0x008c /* Backup data register 30 */ -# define STM32_BKP_DR31_OFFSET 0x0090 /* Backup data register 31 */ -# define STM32_BKP_DR32_OFFSET 0x0094 /* Backup data register 32 */ -# define STM32_BKP_DR33_OFFSET 0x0098 /* Backup data register 33 */ -# define STM32_BKP_DR34_OFFSET 0x009c /* Backup data register 34 */ -# define STM32_BKP_DR35_OFFSET 0x00a0 /* Backup data register 35 */ -# define STM32_BKP_DR36_OFFSET 0x00a4 /* Backup data register 36 */ -# define STM32_BKP_DR37_OFFSET 0x00a8 /* Backup data register 37 */ -# define STM32_BKP_DR38_OFFSET 0x00ac /* Backup data register 38 */ -# define STM32_BKP_DR39_OFFSET 0x00b0 /* Backup data register 39 */ -# define STM32_BKP_DR40_OFFSET 0x00b4 /* Backup data register 40 */ -# define STM32_BKP_DR41_OFFSET 0x00b8 /* Backup data register 41 */ -# define STM32_BKP_DR42_OFFSET 0x00bc /* Backup data register 42 */ -#endif - -/* Register Addresses ***************************************************************/ - -#define STM32_BKP_RTCCR (STM32_BKP_BASE+STM32_BKP_RTCCR_OFFSET) -#define STM32_BKP_CR (STM32_BKP_BASE+STM32_BKP_CR_OFFSET) -#define STM32_BKP_CSR (STM32_BKP_BASE+STM32_BKP_CSR_OFFSET) - -#define STM32_BKP_DR(n) (STM32_BKP_BASE+STM32_BKP_DR_OFFSET(n)) -#define STM32_BKP_DR1 (STM32_BKP_BASE+STM32_BKP_DR1_OFFSET) -#define STM32_BKP_DR2 (STM32_BKP_BASE+STM32_BKP_DR2_OFFSET) -#define STM32_BKP_DR3 (STM32_BKP_BASE+STM32_BKP_DR3_OFFSET) -#define STM32_BKP_DR4 (STM32_BKP_BASE+STM32_BKP_DR4_OFFSET) -#define STM32_BKP_DR5 (STM32_BKP_BASE+STM32_BKP_DR5_OFFSET) -#define STM32_BKP_DR6 (STM32_BKP_BASE+STM32_BKP_DR6_OFFSET) -#define STM32_BKP_DR7 (STM32_BKP_BASE+STM32_BKP_DR7_OFFSET) -#define STM32_BKP_DR8 (STM32_BKP_BASE+STM32_BKP_DR8_OFFSET) -#define STM32_BKP_DR9 (STM32_BKP_BASE+STM32_BKP_DR9_OFFSET) -#define STM32_BKP_DR10 (STM32_BKP_BASE+STM32_BKP_DR10_OFFSET) - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_BKP_DR11 (STM32_BKP_BASE+STM32_BKP_DR11_OFFSET) -# define STM32_BKP_DR12 (STM32_BKP_BASE+STM32_BKP_DR12_OFFSET) -# define STM32_BKP_DR13 (STM32_BKP_BASE+STM32_BKP_DR13_OFFSET) -# define STM32_BKP_DR14 (STM32_BKP_BASE+STM32_BKP_DR14_OFFSET) -# define STM32_BKP_DR15 (STM32_BKP_BASE+STM32_BKP_DR15_OFFSET) -# define STM32_BKP_DR16 (STM32_BKP_BASE+STM32_BKP_DR16_OFFSET) -# define STM32_BKP_DR17 (STM32_BKP_BASE+STM32_BKP_DR17_OFFSET) -# define STM32_BKP_DR18 (STM32_BKP_BASE+STM32_BKP_DR18_OFFSET) -# define STM32_BKP_DR19 (STM32_BKP_BASE+STM32_BKP_DR19_OFFSET) -# define STM32_BKP_DR20 (STM32_BKP_BASE+STM32_BKP_DR20_OFFSET) -# define STM32_BKP_DR21 (STM32_BKP_BASE+STM32_BKP_DR21_OFFSET) -# define STM32_BKP_DR22 (STM32_BKP_BASE+STM32_BKP_DR22_OFFSET) -# define STM32_BKP_DR23 (STM32_BKP_BASE+STM32_BKP_DR23_OFFSET) -# define STM32_BKP_DR24 (STM32_BKP_BASE+STM32_BKP_DR24_OFFSET) -# define STM32_BKP_DR25 (STM32_BKP_BASE+STM32_BKP_DR25_OFFSET) -# define STM32_BKP_DR26 (STM32_BKP_BASE+STM32_BKP_DR26_OFFSET) -# define STM32_BKP_DR27 (STM32_BKP_BASE+STM32_BKP_DR27_OFFSET) -# define STM32_BKP_DR28 (STM32_BKP_BASE+STM32_BKP_DR28_OFFSET) -# define STM32_BKP_DR29 (STM32_BKP_BASE+STM32_BKP_DR29_OFFSET) -# define STM32_BKP_DR30 (STM32_BKP_BASE+STM32_BKP_DR30_OFFSET) -# define STM32_BKP_DR31 (STM32_BKP_BASE+STM32_BKP_DR31_OFFSET) -# define STM32_BKP_DR32 (STM32_BKP_BASE+STM32_BKP_DR32_OFFSET) -# define STM32_BKP_DR33 (STM32_BKP_BASE+STM32_BKP_DR33_OFFSET) -# define STM32_BKP_DR34 (STM32_BKP_BASE+STM32_BKP_DR34_OFFSET) -# define STM32_BKP_DR35 (STM32_BKP_BASE+STM32_BKP_DR35_OFFSET) -# define STM32_BKP_DR36 (STM32_BKP_BASE+STM32_BKP_DR36_OFFSET) -# define STM32_BKP_DR37 (STM32_BKP_BASE+STM32_BKP_DR37_OFFSET) -# define STM32_BKP_DR38 (STM32_BKP_BASE+STM32_BKP_DR38_OFFSET) -# define STM32_BKP_DR39 (STM32_BKP_BASE+STM32_BKP_DR39_OFFSET) -# define STM32_BKP_DR40 (STM32_BKP_BASE+STM32_BKP_DR40_OFFSET) -# define STM32_BKP_DR41 (STM32_BKP_BASE+STM32_BKP_DR41_OFFSET) -# define STM32_BKP_DR42 (STM32_BKP_BASE+STM32_BKP_DR42_OFFSET) -#endif - -/* Register Bitfield Definitions ****************************************************/ - -/* RTC clock calibration register */ - -#define BKP_RTCCR_CAL_SHIFT (0) /* Bits 6-0: Calibration value */ -#define BKP_RTCCR_CAL_MASK (0x7f << BKP_RTCCR_CAL_SHIFT) -#define BKP_RTCCR_CCO (1 << 7) /* Bit 7: Calibration Clock Output */ -#define BKP_RTCCR_ASOE (1 << 8) /* Bit 8: Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS (1 << 9) /* Bit 9: Alarm or Second Output Selection */ - -/* Backup control register */ - -#define BKP_CR_TPE (1 << 0) /* Bit 0: TAMPER pin enable */ -#define BKP_CR_TPAL (1 << 1) /* Bit 1: TAMPER pin active level */ - -/* Backup control/status register */ - -#define BKP_CSR_CTE (1 << 0) /* Bit 0: Clear Tamper event */ -#define BKP_CSR_CTI (1 << 1) /* Bit 1: Clear Tamper Interrupt */ -#define BKP_CSR_TPIE (1 << 2) /* Bit 2: TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF (1 << 8) /* Bit 8: Tamper Event Flag */ -#define BKP_CSR_TIF (1 << 9) /* Bit 9: Tamper Interrupt Flag */ - -/* Backup data register */ - -#define BKP_DR_SHIFT (0) /* Bits 1510: Backup data */ -#define BKP_DR_MASK (0xffff << BKP_DR_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ +#include "chip/stm32_bkp.h" #endif /* __ARCH_ARM_SRC_STM32_STM32_BKP_H */ diff --git a/arch/arm/src/stm32/stm32_i2c.c b/arch/arm/src/stm32/stm32_i2c.c index 90673ef628b..f19a1909cca 100644 --- a/arch/arm/src/stm32/stm32_i2c.c +++ b/arch/arm/src/stm32/stm32_i2c.c @@ -66,6 +66,7 @@ #include #include #include +#include #include #include @@ -81,6 +82,7 @@ #include "stm32_rcc.h" #include "stm32_i2c.h" +#include "stm32_waste.h" #if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) @@ -89,8 +91,6 @@ * Private Types ************************************************************************************/ -#define I2C_FLAGS 0x8000 /* RxNE and TxE enabled */ - /** I2C Device Private Data */ struct stm32_i2c_priv_s { @@ -593,8 +593,6 @@ int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int uint32_t status = 0; int status_errno = 0; - extern void up_waste(void); - ASSERT(count); /* wait as stop might still be in progress @@ -789,7 +787,7 @@ FAR struct i2c_dev_s * up_i2cinitialize(int port) /* Allocate instance */ - if ( !(inst = malloc( sizeof(struct stm32_i2c_inst_s) )) ) return NULL; + if ( !(inst = kmalloc( sizeof(struct stm32_i2c_inst_s) )) ) return NULL; /* initialize instance */ @@ -831,7 +829,7 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev) if ( --((struct stm32_i2c_inst_s *)dev)->priv->refs ) { irqrestore(irqs); - free(dev); + kfree(dev); return OK; } @@ -845,7 +843,7 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev) stm32_i2c_sem_destroy( (struct i2c_dev_s *)dev ); - free(dev); + kfree(dev); return OK; } diff --git a/arch/arm/src/stm32/stm32_pwr.c b/arch/arm/src/stm32/stm32_pwr.c new file mode 100644 index 00000000000..861d32b649c --- /dev/null +++ b/arch/arm/src/stm32/stm32_pwr.c @@ -0,0 +1,90 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32_pwr.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/** \file + * \author Uros Platise + * \brief STM32 Power + * + * \addtogroup STM32_PWR + * \{ + */ + +#include +#include + +#include +#include + +#include "up_arch.h" +#include "stm32_pwr.h" + + +#if defined(CONFIG_STM32_PWR) + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +static inline uint16_t stm32_pwr_getreg(uint8_t offset) +{ + return getreg32(STM32_PWR_BASE + offset); +} + + +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) +{ + putreg32(value, STM32_PWR_BASE + offset); +} + + +static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) +{ + modifyreg32(STM32_PWR_BASE + offset, clearbits, setbits); +} + + + +/************************************************************************************ + * Public Function - Initialization + ************************************************************************************/ + +void stm32_pwr_enablebkp(void) +{ + stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_DBP); +} + + +#endif // defined(CONFIG_STM32_PWR) +/** \} */ diff --git a/arch/arm/src/stm32/stm32_pwr.h b/arch/arm/src/stm32/stm32_pwr.h index bf2b733c3f1..638d23640dd 100644 --- a/arch/arm/src/stm32/stm32_pwr.h +++ b/arch/arm/src/stm32/stm32_pwr.h @@ -43,57 +43,35 @@ #include #include "chip.h" +#include "chip/stm32_pwr.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register Offsets *****************************************************************/ +#ifndef __ASSEMBLY__ -#define STM32_PWR_CR_OFFSET 000x00 /* Power control register */ -#define STM32_PWR_CSR_OFFSET 0x0004 /* Power control/status register */ - -/* Register Addresses ***************************************************************/ - - -/* Register Bitfield Definitions ****************************************************/ - -/* Power control register */ - -#define PWR_CR_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep */ -#define PWR_CR_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */ -#define PWR_CR_CWUF (1 << 2) /* Bit 2: Clear Wakeup Flag */ -#define PWR_CR_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */ -#define PWR_CR_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */ -#define PWR_CR_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */ -#define PWR_CR_PLS_MASK (7 << PWR_CR_PLS_SHIFT) -# define PWR_CR_2p2V (0 << PWR_CR_PLS_SHIFT) /* 000: 2.2V */ -# define PWR_CR_2p3V (1 << PWR_CR_PLS_SHIFT) /* 001: 2.3V */ -# define PWR_CR_2p4V (2 << PWR_CR_PLS_SHIFT) /* 010: 2.4V */ -# define PWR_CR_2p5V (3 << PWR_CR_PLS_SHIFT) /* 011: 2.5V */ -# define PWR_CR_2p6V (4 << PWR_CR_PLS_SHIFT) /* 100: 2.6V */ -# define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */ -# define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */ -# define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */ -#define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ - -/* Power control/status register */ - -#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */ -#define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */ -#define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */ -#define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif /************************************************************************************ * Public Functions ************************************************************************************/ + +/** Disables Write Protection to the Backup Area + **/ +EXTERN void stm32_pwr_enablebkp(void); + +/** \} */ +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_STM32_STM32_PWR_H */ diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c index 52e1ac0ae14..480345938e9 100755 --- a/arch/arm/src/stm32/stm32_rcc.c +++ b/arch/arm/src/stm32/stm32_rcc.c @@ -42,6 +42,7 @@ #include #include #include +#include #include "up_internal.h" #include "up_arch.h" @@ -50,6 +51,7 @@ #include "stm32_rcc.h" #include "stm32_flash.h" #include "stm32_internal.h" +#include "stm32_waste.h" /**************************************************************************** * Definitions @@ -58,11 +60,7 @@ #define HSERDY_TIMEOUT 256 /**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes + * Private Functions ****************************************************************************/ /* Put all RCC registers in reset state */ @@ -100,6 +98,7 @@ static inline void rcc_reset(void) putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */ } + static inline void rcc_enableahb(void) { uint32_t regval; @@ -141,6 +140,7 @@ static inline void rcc_enableahb(void) putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */ } + static inline void rcc_enableapb1(void) { uint32_t regval; @@ -292,6 +292,7 @@ static inline void rcc_enableapb1(void) putreg32(regval, STM32_RCC_APB1ENR); } + static inline void rcc_enableapb2(void) { uint32_t regval; @@ -373,17 +374,14 @@ static inline void rcc_enableapb2(void) putreg32(regval, STM32_RCC_APB2ENR); } -/**************************************************************************** - * Name: stm32_stdclockconfig - * - * Description: - * Called to set clocking based on standard definitions in board.h. - * NOTE: This logic would need to be extended if you need to select low- - * power clocking modes! - * - ****************************************************************************/ #if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + +/** Called to change to new clock based on settings in board.h + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + **/ static inline void stm32_stdclockconfig(void) { uint32_t regval; @@ -471,18 +469,9 @@ static inline void stm32_stdclockconfig(void) } #endif -/**************************************************************************** - * Global Functions - ****************************************************************************/ /**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to change to new clock based on settings in board.h. - * NOTE: This logic needs to be extended so that we can selected low-power - * clocking modes as well! - * + * Public Functions ****************************************************************************/ void stm32_clockconfig(void) @@ -511,3 +500,23 @@ void stm32_clockconfig(void) rcc_enableapb2(); rcc_enableapb1(); } + + +/** + * \todo Check for LSE good timeout and return with -1, + * possible ISR optimization? or at least ISR should be cough in case of failure + */ +void stm32_rcc_enablelse(void) +{ + /* Enable LSE */ + modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON); + + /* We could wait for ISR here ... */ + while( !(getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) ) up_waste(); + + /* Select LSE as RTC Clock Source */ + modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); + + /* Enable Clock */ + modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); +} diff --git a/arch/arm/src/stm32/stm32_rcc.h b/arch/arm/src/stm32/stm32_rcc.h index 8a4baacbad5..1c0020a21db 100755 --- a/arch/arm/src/stm32/stm32_rcc.h +++ b/arch/arm/src/stm32/stm32_rcc.h @@ -46,7 +46,7 @@ #include "chip/stm32_rcc.h" /************************************************************************************ - * Public Data + * Pre-processor Definitions ************************************************************************************/ #ifndef __ASSEMBLY__ @@ -59,6 +59,10 @@ extern "C" { #define EXTERN extern #endif +/************************************************************************************ + * Public Data + ************************************************************************************/ + /* This symbol references the Cortex-M3 vector table (as positioned by the the linker * script, ld.script or ld.script.dfu. The standard location for the vector table is * at the beginning of FLASH at address 0x0800:0000. If we are using the STMicro DFU @@ -68,25 +72,26 @@ extern "C" { extern uint32_t stm32_vectors[]; /* See stm32_vectors.S */ + /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: stm32_clockconfig - * - * Description: - * Called to change to new clock based on settings in board.h - * - ************************************************************************************/ - +/** Called to change to new clock based on settings in board.h + * + * NOTE: This logic needs to be extended so that we can selected low-power + * clocking modes as well! + **/ EXTERN void stm32_clockconfig(void); +/** Enable LSE Clock + **/ +EXTERN void stm32_rcc_enablelse(void); + + #undef EXTERN #if defined(__cplusplus) } #endif - #endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_STM32_STM32_RRC_H */ - diff --git a/arch/arm/src/stm32/stm32_rtc.c b/arch/arm/src/stm32/stm32_rtc.c new file mode 100644 index 00000000000..ec0afdc3562 --- /dev/null +++ b/arch/arm/src/stm32/stm32_rtc.c @@ -0,0 +1,314 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32_rtc.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/** \file + * \author Uros Platise + * \brief STM32 Real-Time Clock + * + * \addtogroup STM32_RTC + * \{ + * + * The STM32 RTC Driver offers standard precision of 1 Hz or High Resolution + * operating at rate up to 16384 Hz. It provides UTC time and alarm interface + * with external output pin (for wake-up). + * + * RTC is based on hardware RTC module which is located in a separate power + * domain. The 32-bit counter is extended by 16-bit registers in BKP domain + * STM32_BKP_DR1 to provide system equiv. function to the: time_t time(time_t *). + * + * Notation: + * - clock refers to 32-bit hardware counter + * - time is a combination of clock and upper bits stored in backuped domain + * with unit of 1 [s] + * + * \todo Error Handling in case LSE fails during start-up or during operation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" + +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_waste.h" + + +#if defined(CONFIG_STM32_BKP) + +/************************************************************************************ + * Configuration of the RTC Backup Register (16-bit) + ************************************************************************************/ + +#define RTC_TIMEMSB_REG STM32_BKP_DR1 + + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/** Variable determines the state of the LSE oscilator. + * Possible errors: + * - on start-up + * - during operation, reported by LSE interrupt + */ +volatile bool g_rtc_enabled = false; + + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +static inline void stm32_rtc_beginwr(void) +{ + /* Previous write is done? */ + while( (getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF)==0 ) up_waste(); + + /* Enter Config mode, Set Value and Exit */ + modifyreg16(STM32_RTC_CRL, 0, RTC_CRL_CNF); +} + + +static inline void stm32_rtc_endwr(void) +{ + modifyreg16(STM32_RTC_CRL, RTC_CRL_CNF, 0); +} + + +/** Wait for registerred to synchronise with RTC module, call after power-up only */ +static inline void stm32_rtc_wait4rsf(void) +{ + modifyreg16(STM32_RTC_CRL, RTC_CRL_RSF, 0); + while( !(getreg16(STM32_RTC_CRL) & RTC_CRL_RSF) ) up_waste(); +} + + + +/************************************************************************************ + * Interrupt Service Routines + ************************************************************************************/ + +static int stm32_rtc_overflow_isr(int irq, void *context) +{ + uint16_t source = getreg16( STM32_RTC_CRL ); + + if (source & RTC_CRL_OWF) { + putreg16( getreg16(RTC_TIMEMSB_REG) + 1, RTC_TIMEMSB_REG ); + } + + if (source & RTC_CRL_ALRF) { + /* Alarm */ + } + + /* Clear pending flags, leave RSF high */ + + putreg16( RTC_CRL_RSF, STM32_RTC_CRL ); + return 0; +} + + +/************************************************************************************ + * Public Function - Initialization + ************************************************************************************/ + +/** Power-up RTC + * + * \param prescaler A 20-bit value determines the time base, and is defined as: + * f = 32768 / (prescaler + 1) + * + * \return State of the RTC unit + * + * \retval OK If RTC has been successfully configured. + * \retval ERROR On error, if LSE does not start. + **/ +int up_rtcinitialize(void) +{ + /* For this initial version we use predefined value */ + + uint32_t prescaler = STM32_RTC_PRESCALER_MIN; + + /* Set access to the peripheral, enable power and LSE */ + + stm32_pwr_enablebkp(); + stm32_rcc_enablelse(); + + // \todo Get state from this function, if everything is + // okay and whether it is already enabled (if it was disabled + // reset upper time register + g_rtc_enabled = true; + + // \todo Possible stall? should we set the timeout period? and return with -1 + stm32_rtc_wait4rsf(); + + /* Configure prescaler, note that this are write-only registers */ + + stm32_rtc_beginwr(); + putreg16(prescaler >> 16, STM32_RTC_PRLH); + putreg16(prescaler & 0xFFFF, STM32_RTC_PRLL); + stm32_rtc_endwr(); + + /* Configure Overflow Interrupt */ + + irq_attach(STM32_IRQ_RTC, stm32_rtc_overflow_isr); + up_enable_irq(STM32_IRQ_RTC); + + /* Previous write is done? This is required prior writing into CRH */ + + while( (getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF)==0 ) up_waste(); + + modifyreg16(STM32_RTC_CRH, 0, RTC_CRH_OWIE); + + /* Alarm Int via EXTI Line */ + + // STM32_IRQ_RTCALR /* 41: RTC alarm through EXTI line interrupt */ + + return OK; +} + + +/** Get time (counter) value + * + * \return time, where the unit depends on the prescaler value + **/ +clock_t up_rtc_getclock(void) +{ + return ( (uint32_t)getreg16(STM32_RTC_CNTH) << 16) | + (uint32_t)getreg16(STM32_RTC_CNTL); +} + + +/** Set time (counter) value + * + * \param time The unit depends on the prescaler value + **/ +void up_rtc_setclock(clock_t clock) +{ + stm32_rtc_beginwr(); + putreg16(clock >> 16, STM32_RTC_CNTH); + putreg16(clock & 0xFFFF, STM32_RTC_CNTL); + stm32_rtc_endwr(); +} + + +time_t up_rtc_gettime(void) +{ + /* Fetch time from LSB (hardware counter) and MSB (backup domain) + * Take care on overflow of the LSB: + * - it may overflow just after reading the up_rtc_getclock, transition + * from 0xFF...FF -> 0x000000 + * - ISR would be generated to increment the RTC_TIMEMSB_REG + * - Wrong result would when: DR+1 and LSB is old, resulting in ~DR+2 + * instead of just DR+1 + */ + + irqstate_t irqs = irqsave(); + + uint32_t time_lsb = up_rtc_getclock(); + uint32_t time_msb = getreg16(RTC_TIMEMSB_REG); + + irqrestore( irqs ); + + /* Use the upper bits of the LSB and lower bits of the MSB + * structured as: + * time = time[31:18] from MSB[13:0] | time[17:0] from time_lsb[31:14] + */ + + time_lsb >>= RTC_CLOCKS_SHIFT; + + time_msb <<= (32-RTC_CLOCKS_SHIFT); + time_msb &= ~((1<<(32-RTC_CLOCKS_SHIFT))-1); + + return time_msb | time_lsb; +} + + +void up_rtc_settime(time_t time) +{ + /* Do reverse compared to gettime above */ + + uint32_t time_lsb = time << RTC_CLOCKS_SHIFT | + (up_rtc_getclock() & ((1<> (32-RTC_CLOCKS_SHIFT); + + irqstate_t irqs = irqsave(); + + up_rtc_setclock(time_lsb); + putreg16( time_msb, RTC_TIMEMSB_REG ); + + irqrestore( irqs ); +} + + +/** Set ALARM at which time ALARM callback is going to be generated + * + * The function sets the alarm and return present time at the time + * of setting the alarm. + * + * Note that If actual time has already passed callback will not be + * generated and it is up to the higher level code to compare the + * returned (actual) time and desired time of alarm. + * + * \param attime The unit depends on the prescaler value + * \return presenttime, where the unit depends on the prescaler value + **/ +clock_t up_rtc_setalarm(clock_t atclock) +{ + stm32_rtc_beginwr(); + putreg16(atclock >> 16, STM32_RTC_ALRH); + putreg16(atclock & 0xFFFF, STM32_RTC_ALRL); + stm32_rtc_endwr(); + + return up_rtc_getclock(); +} + + +/** Set alarm output pin */ +void stm32_rtc_settalarmpin(bool activate) +{ +} + + +#endif // defined(CONFIG_STM32_BKP) +/** \} */ diff --git a/arch/arm/src/stm32/stm32_rtc.h b/arch/arm/src/stm32/stm32_rtc.h index 4ebff07a96c..46746466490 100644 --- a/arch/arm/src/stm32/stm32_rtc.h +++ b/arch/arm/src/stm32/stm32_rtc.h @@ -1,8 +1,8 @@ /************************************************************************************ * arch/arm/src/stm32/stm32_rtc.h * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -33,84 +33,48 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H -#define __ARCH_ARM_SRC_STM32_STM32_RTC_H - /************************************************************************************ * Included Files ************************************************************************************/ +#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H +#define __ARCH_ARM_SRC_STM32_STM32_RTC_H + #include #include "chip.h" +#include "chip/stm32_rtc.h" +#include "chip/stm32_bkp.h" /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register Offsets *****************************************************************/ +#define STM32_RTC_PRESCALER_SECOND 32767 /** Default prescaler to get a second base */ +#define STM32_RTC_PRESCALER_MIN 1 /** Maximum speed of 16384 Hz */ -#define STM32_RTC_CRH_OFFSET 0x0000 /* RTC control register High (16-bit) */ -#define STM32_RTC_CRL_OFFSET 0x0004 /* RTC control register low (16-bit) */ -#define STM32_RTC_PRLH_OFFSET 0x0008 /* RTC prescaler load register high (16-bit) */ -#define STM32_RTC_PRLL_OFFSET 0x000c /* RTC prescaler load register low (16-bit) */ -#define STM32_RTC_DIVH_OFFSET 0x0010 /* RTC prescaler divider register high (16-bit) */ -#define STM32_RTC_DIVL_OFFSET 0x0014 /* RTC prescaler divider register low (16-bit) */ -#define STM32_RTC_CNTH_OFFSET 0x0018 /* RTC counter register high (16-bit) */ -#define STM32_RTC_CNTL_OFFSET 0x001c /* RTC counter register low (16-bit) */ -#define STM32_RTC_ALRH_OFFSET 0x0020 /* RTC alarm register high (16-bit) */ -#define STM32_RTC_ALRL_OFFSET 0x0024 /* RTC alarm register low (16-bit) */ +#ifndef __ASSEMBLY__ -/* Register Addresses ***************************************************************/ - -#define STM32_RTC_CRH (STM32_RTC_BASE+STM32_RTC_CRH_OFFSET) -#define STM32_RTC_CRL (STM32_RTC_BASE+STM32_RTC_CRL_OFFSET) -#define STM32_RTC_PRLH (STM32_RTC_BASE+STM32_RTC_PRLH_OFFSET) -#define STM32_RTC_PRLL (STM32_RTC_BASE+STM32_RTC_PRLL_OFFSET) -#define STM32_RTC_DIVH (STM32_RTC_BASE+STM32_RTC_DIVH_OFFSET) -#define STM32_RTC_DIVL (STM32_RTC_BASE+STM32_RTC_DIVL_OFFSET) -#define STM32_RTC_CNTH (STM32_RTC_BASE+STM32_RTC_CNTH_OFFSET) -#define STM32_RTC_CNTL (STM32_RTC_BASE+STM32_RTC_CNTL_OFFSET) -#define STM32_RTC_ALRH (STM32_RTC_BASE+STM32_RTC_ALRH_OFFSET) -#define STM32_RTC_ALRL (STM32_RTC_BASE+STM32_RTC_ALRL_OFFSET) - -/* Register Bitfield Definitions ****************************************************/ - -/* RTC control register High (16-bit) */ - -#define RTC_CRH_SECIE (1 << 0) /* Bit 0 : Second Interrupt Enable*/ -#define RTC_CRH_ALRIE (1 << 1) /* Bit 1: Alarm Interrupt Enable*/ -#define RTC_CRH_OWIE (1 << 2) /* Bit 2: OverfloW Interrupt Enable*/ - -/* RTC control register low (16-bit) */ - -#define RTC_CRL_SECF (1 << 0) /* Bit 0: Second Flag*/ -#define RTC_CRL_ALRF (1 << 1) /* Bit 1: Alarm Flag*/ -#define RTC_CRL_OWF (1 << 2) /* Bit 2: Overflow Flag*/ -#define RTC_CRL_RSF (1 << 3) /* Bit 3: Registers Synchronized Flag*/ -#define RTC_CRL_CNF (1 << 4) /* Bit 4: Configuration Flag*/ -#define RTC_CRL_RTOFF (1 << 5) /* Bit 5: RTC operation OFF*/ - -/* RTC prescaler load register high (16-bit) */ - -#define RTC_PRLH_PRL_SHIFT (0) /* Bits 3-0: RTC Prescaler Reload Value High */ -#define RTC_PRLH_PRL_MASK (0x0f << RTC_PRLH_PRL_SHIFT) - -/* RTC prescaler divider register high (16-bit) */ - -#define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */ -#define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif /************************************************************************************ * Public Functions ************************************************************************************/ +/** Set alarm output pin */ +EXTERN void stm32_rtc_settalarmpin(bool activate); + + +/** \} */ +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_STM32_STM32_RTC_H */ diff --git a/arch/arm/src/stm32/stm32_spi.h b/arch/arm/src/stm32/stm32_spi.h index 7a58dd83eb1..268589bf35f 100755 --- a/arch/arm/src/stm32/stm32_spi.h +++ b/arch/arm/src/stm32/stm32_spi.h @@ -46,7 +46,7 @@ #include "chip/stm32_spi.h" /************************************************************************************ - * Public Data + * Pre-processor Definitions ************************************************************************************/ #ifndef __ASSEMBLY__ @@ -59,6 +59,10 @@ extern "C" { #define EXTERN extern #endif +/************************************************************************************ + * Public Data + ************************************************************************************/ + struct spi_dev_s; enum spi_dev_e; diff --git a/arch/arm/src/stm32/stm32_tim.h b/arch/arm/src/stm32/stm32_tim.h index a35d0134bd1..1aa18328e28 100644 --- a/arch/arm/src/stm32/stm32_tim.h +++ b/arch/arm/src/stm32/stm32_tim.h @@ -46,6 +46,19 @@ #include "chip.h" #include "chip/stm32_tim.h" +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif /************************************************************************************ * Public Types @@ -155,9 +168,16 @@ struct stm32_tim_ops_s { ************************************************************************************/ /** Power-up timer and get its structure */ -FAR struct stm32_tim_dev_s * stm32_tim_init(int timer); +EXTERN FAR struct stm32_tim_dev_s * stm32_tim_init(int timer); /** Power-down timer, mark it as unused */ -int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev); +EXTERN int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_STM32_STM32_TIM_H */ diff --git a/arch/arm/src/stm32/stm32_waste.c b/arch/arm/src/stm32/stm32_waste.c index 057e2eb3764..a680b8b0f3d 100755 --- a/arch/arm/src/stm32/stm32_waste.c +++ b/arch/arm/src/stm32/stm32_waste.c @@ -39,46 +39,19 @@ #include #include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#include "stm32_waste.h" /**************************************************************************** * Private Data ****************************************************************************/ -/**************************************************************************** - * Public Data - ****************************************************************************/ - uint32_t idle_wastecounter = 0; -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: up_waste - * - * Description: - * up_waste() is the logic that will be executed when portions of kernel - * or user-app is polling some register or similar, waiting for desired - * status. This time is wasted away. This function offers a measure of - * badly written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - * - ****************************************************************************/ - void up_waste(void) { idle_wastecounter++; } - - diff --git a/arch/arm/src/stm32/stm32_waste.h b/arch/arm/src/stm32/stm32_waste.h new file mode 100755 index 00000000000..11703d5a652 --- /dev/null +++ b/arch/arm/src/stm32/stm32_waste.h @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_waste.h + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_WASTE_H +#define __ARCH_ARM_SRC_STM32_STM32_WASTE_H + +/** \file + * \author Uros Platise + * \brief Waste CPU Time + * + * \addtogroup STM32_WASTE + * \{ + */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/** Waste CPU Time + * + * up_waste() is the logic that will be executed when portions of kernel + * or user-app is polling some register or similar, waiting for desired + * status. This time is wasted away. This function offers a measure of + * badly written piece of software or some undesired behavior. + * + * At the same time this function adds to some IDLE time which portion + * cannot be used for other purposes (yet). + **/ + +EXTERN void up_waste(void); + + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32_STM32_RRC_H */