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@@ -45,6 +45,7 @@
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#include <debug.h>
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#include <arch/irq.h>
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#include <nuttx/arch.h>
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#include "up_arch.h"
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#include "chip.h"
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@@ -84,17 +85,17 @@
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static unsigned int lpc17_getintedge(unsigned int port, unsigned int pin)
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{
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const uint64_t *intedge;
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uint64_t *intedge;
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/* Which word to we use? */
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if (port == 0)
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{
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intedge = g_intedge0;
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intedge = &g_intedge0;
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}
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else if (port == 2)
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{
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intedge = g_intedge2;
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intedge = &g_intedge2;
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}
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else
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{
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@@ -129,7 +130,6 @@ static void lpc17_setintedge(uint32_t intbase, unsigned int pin, unsigned int ed
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{
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regval &= ~GPIOINT(pin);
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}
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endif
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putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET);
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/* Set/clear the rising edge enable bit */
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@@ -143,7 +143,6 @@ static void lpc17_setintedge(uint32_t intbase, unsigned int pin, unsigned int ed
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{
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regval &= ~GPIOINT(pin);
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}
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endif
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putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET);
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}
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@@ -159,21 +158,21 @@ static int lpc17_irq2port(int irq)
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{
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/* Set 1: 12 interrupts p0.0-p0.11 */
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if (irq >= LPC17_VALID_FIRST0L && irq < (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
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if (irq >= LPC17_VALID_FIRST0L && irq < (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L))
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{
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return 0;
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}
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/* Set 2: 16 interrupts p0.15-p0.30 */
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else if (irq >= LPC17_VALID_FIRST0H && irq < (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
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else if (irq >= LPC17_VALID_FIRST0H && irq < (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H))
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{
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return 0;
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}
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/* Set 3: 14 interrupts p2.0-p2.13 */
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else if (irq >= LPC17_VALID_NIRQS2 && irq < (LPC17_VALID_FIRST2+LPC17_VALID_NIRQS2)
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else if (irq >= LPC17_VALID_NIRQS2 && irq < (LPC17_VALID_FIRST2+LPC17_VALID_NIRQS2))
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{
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return 2;
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}
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@@ -188,45 +187,176 @@ static int lpc17_irq2port(int irq)
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*
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****************************************************************************/
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static int lpc17_irq2port(int irq)
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static int lpc17_irq2pin(int irq)
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{
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/* Set 1: 12 interrupts p0.0-p0.11 */
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if (irq >= LPC17_VALID_FIRST0L && irq < (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
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if (irq >= LPC17_VALID_FIRST0L && irq < (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L))
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{
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return irq - LPC17_VALID_FIRST0L + LPC17_VALID_SHIFT0L;
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}
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/* Set 2: 16 interrupts p0.15-p0.30 */
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else if (irq >= LPC17_VALID_FIRST0H && irq < (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
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else if (irq >= LPC17_VALID_FIRST0H && irq < (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H))
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{
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return irq - LPC17_VALID_FIRST0H + LPC17_VALID_SHIFT0H;
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12
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}
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/* Set 3: 14 interrupts p2.0-p2.13 */
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else if (irq >= LPC17_VALID_NIRQS2 && irq < (LPC17_VALID_FIRST2+LPC17_VALID_NIRQS2)
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else if (irq >= LPC17_VALID_NIRQS2 && irq < (LPC17_VALID_FIRST2+LPC17_VALID_NIRQS2))
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{
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return irq - LPC17_VALID_FIRST0H + LPC17_VALID_SHIFT2;
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}
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return -EINVAL;
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}
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/****************************************************************************
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* Name: lpc17_gpiodemux
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*
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* Description:
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* Demux all interrupts on one GPIO interrupt status register.
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*
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****************************************************************************/
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static void lpc17_gpiodemux(uint32_t intbase, uint32_t intmask,
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int irqbase, void *context)
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{
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uint32_t intstatr;
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uint32_t intstatf;
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uint32_t intstatus;
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uint32_t bit;
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int irq;
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/* Get the interrupt rising and falling edge status and mask out only the
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* interrupts that are enabled.
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*/
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intstatr = getreg32(intbase + LPC17_GPIOINT_INTSTATR_OFFSET);
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intstatr &= getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET);
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intstatf = getreg32(intbase + LPC17_GPIOINT_INTSTATF_OFFSET);
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intstatf &= getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET);
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/* And get the OR of the enabled interrupt sources. We do not make any
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* distinction between rising and falling edges (but the hardware does support
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* the ability to differently if needed.
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*/
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intstatus = intstatr | intstatf;
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/* Now march through the (valid) bits and dispatch each interrupt */
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irq = irqbase;
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bit = 1;
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while (intstatus != 0)
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{
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/* Does this pin support an interrupt? If no, skip over it WITHOUT
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* incrementing irq.
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*/
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if ((intmask & bit) != 0)
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{
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/* This pin can support an interrupt. Is there an interrupt pending
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* and enabled?
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*/
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if ((intstatus & bit) != 0)
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{
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/* Clear the interrupt status */
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putreg32(bit, intbase + LPC17_GPIOINT_INTCLR_OFFSET);
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/* And dispatch the interrupt */
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irq_dispatch(irq, context);
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}
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/* Increment the IRQ number on each interrupt pin */
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irq++;
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}
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/* Next bit */
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intstatus &= ~bit;
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bit <<= 1;
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}
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}
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/****************************************************************************
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* Name: lpc17_gpiointerrupt
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*
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* Description:
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* Handle the EINT3 interrupt that also indicates that a GPIO interrupt has
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* occurred. NOTE: This logic will have to be extended if EINT3 is
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* actually used for External Interrupt 3.
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*
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****************************************************************************/
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static int lpc17_gpiointerrupt(int irq, void *context)
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{
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/* Get the GPIO interrupt status */
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uint32_t intstatus = getreg32(LPC17_GPIOINT_IOINTSTATUS);
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/* Check for an interrupt on GPIO0 */
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if ((intstatus & GPIOINT_IOINTSTATUS_P0INT) != 0)
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{
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lpc17_gpiodemux(LPC17_GPIOINT0_BASE, LPC17_VALID_GPIOINT0,
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LPC17_VALID_FIRST0L, context);
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}
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/* Check for an interrupt on GPIO2 */
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if ((intstatus & GPIOINT_IOINTSTATUS_P2INT) != 0)
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{
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lpc17_gpiodemux(LPC17_GPIOINT2_BASE, LPC17_VALID_GPIOINT2,
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LPC17_VALID_FIRST2, context);
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}
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return OK;
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}
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/****************************************************************************
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* Global Functions
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Name: lpc17_gpioirqinitialize
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*
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* Description:
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* Initialize logic to support a second level of interrupt decoding for
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* GPIO pins.
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*
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****************************************************************************/
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void lpc17_gpioirqinitialize(void)
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{
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/* Disable all GPIO interrupts */
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putreg32(0, LPC17_GPIOINT0_INTENR);
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putreg32(0, LPC17_GPIOINT0_INTENF);
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putreg32(0, LPC17_GPIOINT2_INTENR);
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putreg32(0, LPC17_GPIOINT2_INTENF);
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/* Attach and enable the GPIO IRQ. Note: GPIO0 and GPIO2 interrupts share
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* the same position in the NVIC with External Interrupt 3
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*/
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(void)irq_attach(LPC17_IRQ_EINT3, lpc17_gpiointerrupt);
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up_enable_irq(LPC17_IRQ_EINT3);
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}
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/****************************************************************************
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* Name: lpc17_gpioirqenable
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*
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* Description:
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* Enable the interrupt for specified GPIO IRQ
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*
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************************************************************************************/
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****************************************************************************/
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void lpc17_gpioirqenable(int irq)
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{
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@@ -239,25 +369,25 @@ void lpc17_gpioirqenable(int irq)
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* address of the GPIOINT registers for the port.
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*/
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uint32_t intbase = g_intbase[GPIO_NPORTS];
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if (intabase != 0)
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uint32_t intbase = g_intbase[port];
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if (intbase != 0)
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{
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/* And get the pin number associated with the port */
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unsigned int pin = g_irq2pin(irq);
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unsigned int pin = lpc17_irq2pin(irq);
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unsigned int edges = lpc17_getintedge(port, pin);
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lpc17_setintedge(intbase, pin, edges);
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}
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}
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}
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/************************************************************************************
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/****************************************************************************
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* Name: lpc17_gpioirqdisable
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*
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* Description:
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* Disable the interrupt for specified GPIO IRQ
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*
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************************************************************************************/
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****************************************************************************/
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void lpc17_gpioirqdisable(int irq)
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{
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@@ -270,18 +400,16 @@ void lpc17_gpioirqdisable(int irq)
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* address of the GPIOINT registers for the port.
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*/
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uint32_t intbase = g_intbase[GPIO_NPORTS];
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if (intabase != 0)
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uint32_t intbase = g_intbase[port];
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if (intbase != 0)
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{
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/* And get the pin number associated with the port */
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unsigned int pin = g_irq2pin(irq);
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unsigned int pin = lpc17_irq2pin(irq);
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lpc17_setintedge(intbase, pin, 0);
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}
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}
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}
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#warning "Still needs initialization, interrupt handling and decoding logic"
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#endif /* CONFIG_GPIO_IRQ */
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patacongo