diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 872f92f5933..c2cee042645 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -416,6 +416,7 @@ config ARCH_CHIP_CXD56XX select ARCH_HAVE_FPU select ARCH_HAVE_HEAPCHECK select ARCH_HAVE_MULTICPU + select ARCH_GLOBAL_IRQDISABLE select ARCH_HAVE_SDIO if MMCSD ---help--- Sony CXD56XX (ARM Cortex-M4) architectures diff --git a/arch/arm/src/cxd56xx/Make.defs b/arch/arm/src/cxd56xx/Make.defs index 3b0be404581..8bfdb799b90 100644 --- a/arch/arm/src/cxd56xx/Make.defs +++ b/arch/arm/src/cxd56xx/Make.defs @@ -107,6 +107,13 @@ CHIP_CSRCS += cxd56_powermgr.c CHIP_CSRCS += cxd56_farapi.c CHIP_CSRCS += cxd56_sysctl.c +ifeq ($(CONFIG_SMP), y) +CHIP_CSRCS += cxd56_cpuidlestack.c +CHIP_CSRCS += cxd56_cpuindex.c +CHIP_CSRCS += cxd56_cpupause.c +CHIP_CSRCS += cxd56_cpustart.c +endif + ifeq ($(CONFIG_CXD56_UART0),y) CHIP_CSRCS += cxd56_uart0.c endif diff --git a/arch/arm/src/cxd56xx/cxd56_cpuidlestack.c b/arch/arm/src/cxd56xx/cxd56_cpuidlestack.c new file mode 100644 index 00000000000..b081e56dd8c --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_cpuidlestack.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_cpuidlestack.c + * + * Copyright 2019 Sony Home Entertainment & Sound Products Inc. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_internal.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_idlestack + * + * Description: + * Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and + * setup up stack-related information in the IDLE task's TCB. This + * function is always called before up_cpu_start(). This function is + * only called for the CPU's initial IDLE task; up_create_task is used for + * all normal tasks, pthreads, and kernel threads for all CPUs. + * + * The initial IDLE task is a special case because the CPUs can be started + * in different wans in different environments: + * + * 1. The CPU may already have been started and waiting in a low power + * state for up_cpu_start(). In this case, the IDLE thread's stack + * has already been allocated and is already in use. Here + * up_cpu_idlestack() only has to provide information about the + * already allocated stack. + * + * 2. The CPU may be disabled but started when up_cpu_start() is called. + * In this case, a new stack will need to be created for the IDLE + * thread and this function is then equivalent to: + * + * return up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL); + * + * The following TCB fields must be initialized by this function: + * + * - adj_stack_size: Stack size after adjustment for hardware, processor, + * etc. This value is retained only for debug purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of + * the stack pointer. + * + * Input Parameters: + * - cpu: CPU index that indicates which CPU the IDLE task is + * being created for. + * - tcb: The TCB of new CPU IDLE task + * - stack_size: The requested stack size for the IDLE task. At least + * this much must be allocated. This should be + * CONFIG_SMP_STACK_SIZE. + * + ****************************************************************************/ + +int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size) +{ +#if CONFIG_SMP_NCPUS > 1 + (void)up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL); +#endif + return OK; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/cxd56xx/cxd56_cpuindex.c b/arch/arm/src/cxd56xx/cxd56_cpuindex.c new file mode 100644 index 00000000000..8ddb11b4e43 --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_cpuindex.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_cpuindex.c + * + * Copyright 2019 Sony Home Entertainment & Sound Products Inc. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "up_arch.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CXD56_ADSP_PID 0x0e002040 /* APP_DSP Processor ID */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + +int up_cpu_index(void) +{ + /* NOTE: APP_DSP Processor ID starts from 2 */ + + return getreg32(CXD56_ADSP_PID) - 2; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/cxd56xx/cxd56_cpupause.c b/arch/arm/src/cxd56xx/cxd56_cpupause.c new file mode 100644 index 00000000000..0010f5ab20e --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_cpupause.c @@ -0,0 +1,455 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_cpupause.c + * + * Copyright 2019 Sony Home Entertainment & Sound Products Inc. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "sched/sched.h" +#include "up_internal.h" +#include "hardware/cxd5602_memorymap.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if 0 +# define DPRINTF(fmt, args...) _err(fmt, ##args) +#else +# define DPRINTF(fmt, args...) do {} while (0) +#endif + +#define CXD56_CPU_P2_INT (CXD56_SWINT_BASE + 0x8) /* for APP_DSP0 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* These spinlocks are used in the SMP configuration in order to implement + * up_cpu_pause(). The protocol for CPUn to pause CPUm is as follows + * + * 1. The up_cpu_pause() implementation on CPUn locks both g_cpu_wait[m] + * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_paused[m]. + * 2. CPUm receives the interrupt it (1) unlocks g_cpu_paused[m] and + * (2) locks g_cpu_wait[m]. The first unblocks CPUn and the second + * blocks CPUm in the interrupt handler. + * + * When CPUm resumes, CPUn unlocks g_cpu_wait[m] and the interrupt handler + * on CPUm continues. CPUm must, of course, also then unlock g_cpu_wait[m] + * so that it will be ready for the next pause operation. + */ + +static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; +static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; + +static volatile int g_irq_to_handle[CONFIG_SMP_NCPUS][2]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: handle_irqreq + * + * Description: + * If an irq handling request is found on cpu, call up_enable_irq() or + * up_disable_irq(), then return true. + * + * Input Parameters: + * cpu - The index of the CPU to be queried + * + * Returned Value: + * true = an irq handling request is found + * false = no irq handling request is found + * + ****************************************************************************/ + +static bool handle_irqreq(int cpu) +{ + int i; + bool handled = false; + + /* Check both cases */ + + for (i = 0; i < 2; i++) + { + int irqreq = g_irq_to_handle[cpu][i]; + + if (irqreq) + { + /* Unlock the spinlock first */ + + spin_unlock(&g_cpu_paused[cpu]); + + /* Then wait for the spinlock to be released */ + + spin_lock(&g_cpu_wait[cpu]); + + /* Clear g_irq_to_handle[cpu][i] */ + + g_irq_to_handle[cpu][i] = 0; + + if (0 == i) + { + up_enable_irq(irqreq); + } + else + { + up_disable_irq(irqreq); + } + + /* Finally unlock the spinlock */ + + spin_unlock(&g_cpu_wait[cpu]); + handled = true; + } + } + + return handled; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_pausereq + * + * Description: + * Return true if a pause request is pending for this CPU. + * + * Input Parameters: + * cpu - The index of the CPU to be queried + * + * Returned Value: + * true = a pause request is pending. + * false = no pasue request is pending. + * + ****************************************************************************/ + +bool up_cpu_pausereq(int cpu) +{ + return spin_islocked(&g_cpu_paused[cpu]); +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ + FAR struct tcb_s *tcb = this_task(); + + /* Update scheduler parameters */ + + sched_suspend_scheduler(tcb); + +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify that we are paused */ + + sched_note_cpu_paused(tcb); +#endif + + /* Save the current context at CURRENT_REGS into the TCB at the head + * of the assigned task list for this CPU. + */ + + up_savestate(tcb->xcp.regs); + + /* Wait for the spinlock to be released */ + + spin_unlock(&g_cpu_paused[cpu]); + spin_lock(&g_cpu_wait[cpu]); + + /* Restore the exception context of the tcb at the (new) head of the + * assigned task list. + */ + + tcb = this_task(); + +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify that we have resumed */ + + sched_note_cpu_resumed(tcb); +#endif + + /* Reset scheduler parameters */ + + sched_resume_scheduler(tcb); + + /* Then switch contexts. Any necessary address environment changes + * will be made when the interrupt returns. + */ + + up_restorestate(tcb->xcp.regs); + spin_unlock(&g_cpu_wait[cpu]); + + return OK; +} + +/**************************************************************************** + * Name: arm_pause_handler + * + * Description: + * Inter-CPU interrupt handler + * + * Input Parameters: + * Standard interrupt handler inputs + * + * Returned Value: + * Should always return OK + * + ****************************************************************************/ + +int arm_pause_handler(int irq, void *c, FAR void *arg) +{ + int cpu = up_cpu_index(); + + DPRINTF("cpu%d will be paused \n", cpu); + + /* Clear SW_INT for APP_DSP(cpu) */ + + putreg32(0, CXD56_CPU_P2_INT + (4 * cpu)); + + /* Check if this IPI is to enable/disable IRQ */ + + if (handle_irqreq(cpu)) + { + return OK; + } + + /* Check for false alarms. Such false could occur as a consequence of + * some deadlock breaking logic that might have already serviced the SG2 + * interrupt by calling up_cpu_paused. + */ + + if (spin_islocked(&g_cpu_paused[cpu])) + { + return up_cpu_paused(cpu); + } + + return OK; +} + +/**************************************************************************** + * Name: up_cpu_pause + * + * Description: + * Save the state of the current task at the head of the + * g_assignedtasks[cpu] task list and then pause task execution on the + * CPU. + * + * This function is called by the OS when the logic executing on one CPU + * needs to modify the state of the g_assignedtasks[cpu] list for another + * CPU. + * + * Input Parameters: + * cpu - The index of the CPU to be stopped/ + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_pause(int cpu) +{ + DPRINTF("cpu=%d\n", cpu); + + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); + +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify of the pause event */ + + sched_note_cpu_pause(this_task(), cpu); +#endif + + /* Take the both spinlocks. The g_cpu_wait spinlock will prevent the + * handler from returning until up_cpu_resume() is called; g_cpu_paused + * is a handshake that will prefent this function from returning until + * the CPU is actually paused. + */ + + DEBUGASSERT(!spin_islocked(&g_cpu_wait[cpu]) && + !spin_islocked(&g_cpu_paused[cpu])); + + spin_lock(&g_cpu_wait[cpu]); + spin_lock(&g_cpu_paused[cpu]); + + /* Generate IRQ for CPU(cpu) */ + + putreg32(1, CXD56_CPU_P2_INT + (4 * cpu)); + + /* Wait for the other CPU to unlock g_cpu_paused meaning that + * it is fully paused and ready for up_cpu_resume(); + */ + + spin_lock(&g_cpu_paused[cpu]); + spin_unlock(&g_cpu_paused[cpu]); + + /* On successful return g_cpu_wait will be locked, the other CPU will be + * spinninf on g_cpu_wait and will not continue until g_cpu_resume() is + * called. g_cpu_paused will be unlocked in any case. + */ + + return OK; +} + +/**************************************************************************** + * Name: up_cpu_resume + * + * Description: + * Restart the cpu after it was paused via up_cpu_pause(), restoring the + * state of the task at the head of the g_assignedtasks[cpu] list, and + * resume normal tasking. + * + * This function is called after up_cpu_pause in order resume operation of + * the CPU after modifying its g_assignedtasks[cpu] list. + * + * Input Parameters: + * cpu - The index of the CPU being re-started. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_resume(int cpu) +{ + DPRINTF("cpu=%d\n", cpu); + + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); + +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify of the resume event */ + + sched_note_cpu_resume(this_task(), cpu); +#endif + + /* Release the spinlock. Releasing the spinlock will cause the SGI2 + * handler on 'cpu' to continue and return from interrupt to the newly + * established thread. + */ + + DEBUGASSERT(spin_islocked(&g_cpu_wait[cpu]) && + !spin_islocked(&g_cpu_paused[cpu])); + + spin_unlock(&g_cpu_wait[cpu]); + return OK; +} + +/**************************************************************************** + * Name: up_send_irqreq() + * + * Description: + * Send up_enable_irq() / up_disable_irq() request to the specified cpu + * + * This function is called from up_enable_irq() or up_disable_irq() + * to be handled on specified CPU. Locking protocol in the sequence is + * the same as up_pause_cpu() plus up_resume_cpu(). + * + * Input Parameters: + * idx - The request index (0: enable, 1: disable) + * irq - The IRQ number to be handled + * cpu - The index of the CPU which will handle the request + * + ****************************************************************************/ + +void up_send_irqreq(int idx, int irq, int cpu) +{ + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); + + /* Wait for the spinlocks to be released */ + + spin_lock(&g_cpu_wait[cpu]); + spin_lock(&g_cpu_paused[cpu]); + + /* Set irq for the cpu */ + + g_irq_to_handle[cpu][idx] = irq; + + /* Generate IRQ for CPU(cpu) */ + + putreg32(1, CXD56_CPU_P2_INT + (4 * cpu)); + + /* Wait for the handler is excecuted on cpu */ + + spin_lock(&g_cpu_paused[cpu]); + spin_unlock(&g_cpu_paused[cpu]); + + /* Finally unlock the spinlock to proceed the handler */ + + spin_unlock(&g_cpu_wait[cpu]); + return; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/cxd56xx/cxd56_cpustart.c b/arch/arm/src/cxd56xx/cxd56_cpustart.c new file mode 100644 index 00000000000..f1b48cf4279 --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_cpustart.c @@ -0,0 +1,254 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_cpustart.c + * + * Copyright 2019 Sony Home Entertainment & Sound Products Inc. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "nvic.h" +#include "up_arch.h" +#include "sched/sched.h" +#include "init/init.h" +#include "up_internal.h" +#include "hardware/cxd56_crg.h" +#include "hardware/cxd5602_memorymap.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if 0 +# define DPRINTF(fmt, args...) _err(fmt, ##args) +#else +# define DPRINTF(fmt, args...) do {} while (0) +#endif + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) up_lowputc(c) +#else +# define showprogress(c) +#endif + +#define CXD56_ACNV_P0_DST0 0x0e012004 +#define CXD56_CPU_P2_INT (CXD56_SWINT_BASE + 0x8) /* for APP_DSP0 */ + +#define VECTOR_ISTACK (CXD56_ADSP_RAM_BASE + 0) +#define VECTOR_RESETV (CXD56_ADSP_RAM_BASE + 4) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile static spinlock_t g_appdsp_boot; + +extern int arm_pause_handler(int irq, void *c, FAR void *arg); +extern void fpuconfig(void); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: appdsp_boot + * + * Description: + * This is the boot vector for APP_DSP + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void appdsp_boot(void) +{ + int cpu; + + cpu = up_cpu_index(); + DPRINTF("cpu = %d\n", cpu); + + /* Setup FPU */ + + fpuconfig(); + + /* Clear SW_INT for APP_DSP(cpu) */ + + putreg32(0, CXD56_CPU_P2_INT + (4 * cpu)); + + /* Enable SW_INT */ + + irq_attach(CXD56_IRQ_SW_INT, arm_pause_handler, NULL); + up_enable_irq(CXD56_IRQ_SW_INT); + + spin_unlock(&g_appdsp_boot); + +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify that this CPU has started */ + + sched_note_cpu_started(this_task()); +#endif + + /* Then transfer control to the IDLE task */ + + (void)nx_idle_task(0, NULL); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_start + * + * Description: + * In an SMP configution, only one CPU is initially active (CPU 0). System + * initialization occurs on that single thread. At the completion of the + * initialization of the OS, just before beginning normal multitasking, + * the additional CPUs would be started by calling this function. + * + * Each CPU is provided the entry point to is IDLE task when started. A + * TCB for each CPU's IDLE task has been initialized and placed in the + * CPU's g_assignedtasks[cpu] list. Not stack has been alloced or + * initialized. + * + * The OS initialization logic calls this function repeatedly until each + * CPU has been started, 1 through (CONFIG_SMP_NCPUS-1). + * + * Input Parameters: + * cpu - The index of the CPU being started. This will be a numeric + * value in the range of from one to (CONFIG_SMP_NCPUS-1). (CPU + * 0 is already active) + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_start(int cpu) +{ + int i; + struct tcb_s *tcb = current_task(cpu); + + DPRINTF("cpu=%d\n", cpu); + +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify of the start event */ + + sched_note_cpu_start(this_task(), cpu); +#endif + + /* Reset APP_DSP(cpu) */ + + modifyreg32(CXD56_CRG_RESET, 1 << (16 + cpu), 0); + + /* Copy initial stack and reset vector for APP_DSP */ + + putreg32((uint32_t)tcb->adj_stack_ptr, VECTOR_ISTACK); + putreg32((uint32_t)appdsp_boot, VECTOR_RESETV); + + spin_lock(&g_appdsp_boot); + + /* See 3.13.4.16.3 ADSP Startup */ + + /* 2. Clock supply */ + + modifyreg32(CXD56_CRG_CK_GATE_AHB, 0, 1 << (16 + cpu)); + + /* 3. Clock stop */ + + modifyreg32(CXD56_CRG_CK_GATE_AHB, 1 << (16 + cpu), 0); + + /* 4. APP_DSP(cpu) start preparation */ + + /* Copy APP_DSP0 settings to all 12 tiles for APP_DSP(cpu) + * TODO: need to exclude memory areas for AMP + */ + + for (i = 0; i < 12; i++) + { + uint32_t val = getreg32(CXD56_ACNV_P0_DST0 + (4 * i)); + putreg32(val, CXD56_ACNV_P0_DST0 + (4 * i) + (cpu * 0x20)); + } + + /* 5. Reset release */ + + modifyreg32(CXD56_CRG_RESET, 0, 1 << (16 + cpu)); + + /* 6. Clock supply */ + + modifyreg32(CXD56_CRG_CK_GATE_AHB, 0, 1 << (16 + cpu)); + + /* Setup SW_INT for APP_DSP0. The caller is APP_DSP0 and + * it's enough to setup only once. So, here this setup is + * done in case that we boot APP_DSP1 (cpu=1). + */ + + if (1 == cpu) + { + /* Clear SW_INT for this APP_DSP0 */ + + putreg32(0, CXD56_CPU_P2_INT); + + /* Setup SW_INT fot this APP_DSP0 */ + + irq_attach(CXD56_IRQ_SW_INT, arm_pause_handler, NULL); + up_enable_irq(CXD56_IRQ_SW_INT); + } + + spin_lock(&g_appdsp_boot); + + /* APP_DSP(cpu) boot done */ + + spin_unlock(&g_appdsp_boot); + + return 0; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/cxd56xx/cxd56_irq.c b/arch/arm/src/cxd56xx/cxd56_irq.c index 3914b6c3a8d..111d455c304 100644 --- a/arch/arm/src/cxd56xx/cxd56_irq.c +++ b/arch/arm/src/cxd56xx/cxd56_irq.c @@ -92,6 +92,11 @@ volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; volatile uint32_t *g_current_regs[1]; #endif +#ifdef CONFIG_SMP +static volatile int8_t g_cpu_for_irq[CXD56_IRQ_NIRQS]; +extern void up_send_irqreq(int idx, int irq, int cpu); +#endif + /* This is the address of the exception vector table (determined by the * linker script). */ @@ -285,6 +290,14 @@ void up_irqinitialize(void) uint32_t regaddr; int num_priority_registers; +#ifdef CONFIG_SMP + int i; + for (i = 0; i < CXD56_IRQ_NIRQS; i++) + { + g_cpu_for_irq[i] = -1; + } +#endif + /* Disable all interrupts */ putreg32(0, NVIC_IRQ0_31_ENABLE); @@ -421,14 +434,37 @@ void up_disable_irq(int irq) if (irq >= CXD56_IRQ_EXTINT) { - irqstate_t flags = enter_critical_section(); +#ifdef CONFIG_SMP + /* Obtain cpu number which enabled this irq */ + + int8_t cpu = g_cpu_for_irq[irq]; + + if (-1 == cpu) + { + /* Already disabled */ + + return; + } + + /* If a defferent cpu requested, send an irq request */ + + if (cpu != (int8_t)up_cpu_index()) + { + up_send_irqreq(1, irq, cpu); + return; + } + + g_cpu_for_irq[irq] = -1; +#endif + + irqstate_t flags = spin_lock_irqsave(); irq -= CXD56_IRQ_EXTINT; bit = 1 << (irq & 0x1f); regval = getreg32(INTC_EN(irq)); regval &= ~bit; putreg32(regval, INTC_EN(irq)); - leave_critical_section(flags); + spin_unlock_irqrestore(flags); putreg32(bit, NVIC_IRQ_CLEAR(irq)); } else @@ -460,14 +496,30 @@ void up_enable_irq(int irq) if (irq >= CXD56_IRQ_EXTINT) { - irqstate_t flags = enter_critical_section(); +#ifdef CONFIG_SMP + int cpu = up_cpu_index(); + + /* Set the caller cpu for this irq */ + + g_cpu_for_irq[irq] = (int8_t)cpu; + + /* EXTINT needs to be handled on CPU0 to avoid deadlock */ + + if (irq > CXD56_IRQ_EXTINT && irq != CXD56_IRQ_SW_INT && 0 != cpu) + { + up_send_irqreq(0, irq, 0); + return; + } +#endif + + irqstate_t flags = spin_lock_irqsave(); irq -= CXD56_IRQ_EXTINT; bit = 1 << (irq & 0x1f); regval = getreg32(INTC_EN(irq)); regval |= bit; putreg32(regval, INTC_EN(irq)); - leave_critical_section(flags); + spin_unlock_irqrestore(flags); putreg32(bit, NVIC_IRQ_ENABLE(irq)); } else diff --git a/arch/arm/src/cxd56xx/cxd56_start.c b/arch/arm/src/cxd56xx/cxd56_start.c index e1dd54c6363..d656d1d91d6 100644 --- a/arch/arm/src/cxd56xx/cxd56_start.c +++ b/arch/arm/src/cxd56xx/cxd56_start.c @@ -129,100 +129,9 @@ static void go_nx_start(void *pv, unsigned int nbytes) extern uint32_t _vectors[]; /**************************************************************************** - * Public Functions + * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: fpuconfig - * - * Description: - * Configure the FPU. Relative bit settings: - * - * CPACR: Enables access to CP10 and CP11 - * CONTROL.FPCA: Determines whether the FP extension is active in the - * current context: - * FPCCR.ASPEN: Enables automatic FP state preservation, then the - * processor sets this bit to 1 on successful completion of any FP - * instruction. - * FPCCR.LSPEN: Enables lazy context save of FP state. When this is - * done, the processor reserves space on the stack for the FP state, - * but does not save that state information to the stack. - * - * Software must not change the value of the ASPEN bit or LSPEN bit while - * either: - * - the CPACR permits access to CP10 and CP11, that give access to the FP - * extension, or - * - the CONTROL.FPCA bit is set to 1 - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_FPU -# ifndef CONFIG_ARMV7M_LAZYFPU - -static inline void fpuconfig(void) -{ - uint32_t regval; - - /* Set CONTROL.FPCA so that we always get the extended context frame - * with the volatile FP registers stacked above the basic context. - */ - - regval = getcontrol(); - regval |= (1 << 2); - setcontrol(regval); - - /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend - * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we - * are going to turn on CONTROL.FPCA for all contexts. - */ - - regval = getreg32(NVIC_FPCCR); - regval &= ~((1 << 31) | (1 << 30)); - putreg32(regval, NVIC_FPCCR); - - /* Enable full access to CP10 and CP11 */ - - regval = getreg32(NVIC_CPACR); - regval |= ((3 << (2 * 10)) | (3 << (2 * 11))); - putreg32(regval, NVIC_CPACR); -} - -# else - -static inline void fpuconfig(void) -{ - uint32_t regval; - - /* Clear CONTROL.FPCA so that we do not get the extended context frame - * with the volatile FP registers stacked in the saved context. - */ - - regval = getcontrol(); - regval &= ~(1 << 2); - setcontrol(regval); - - /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend - * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we - * are going to keep CONTROL.FPCA off for all contexts. - */ - - regval = getreg32(NVIC_FPCCR); - regval &= ~((1 << 31) | (1 << 30)); - putreg32(regval, NVIC_FPCCR); - - /* Enable full access to CP10 and CP11 */ - - regval = getreg32(NVIC_CPACR); - regval |= ((3 << (2 * 10)) | (3 << (2 * 11))); - putreg32(regval, NVIC_CPACR); -} - -# endif - -#else -# define fpuconfig() -#endif - /**************************************************************************** * Name: go_nx_start * @@ -267,6 +176,97 @@ static void go_nx_start(void *pv, unsigned int nbytes) * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: fpuconfig + * + * Description: + * Configure the FPU. Relative bit settings: + * + * CPACR: Enables access to CP10 and CP11 + * CONTROL.FPCA: Determines whether the FP extension is active in the + * current context: + * FPCCR.ASPEN: Enables automatic FP state preservation, then the + * processor sets this bit to 1 on successful completion of any FP + * instruction. + * FPCCR.LSPEN: Enables lazy context save of FP state. When this is + * done, the processor reserves space on the stack for the FP state, + * but does not save that state information to the stack. + * + * Software must not change the value of the ASPEN bit or LSPEN bit while + * either: + * - the CPACR permits access to CP10 and CP11, that give access to the FP + * extension, or + * - the CONTROL.FPCA bit is set to 1 + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +# ifndef CONFIG_ARMV7M_LAZYFPU + +void fpuconfig(void) +{ + uint32_t regval; + + /* Set CONTROL.FPCA so that we always get the extended context frame + * with the volatile FP registers stacked above the basic context. + */ + + regval = getcontrol(); + regval |= (1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to turn on CONTROL.FPCA for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2 * 10)) | (3 << (2 * 11))); + putreg32(regval, NVIC_CPACR); +} + +# else + +void fpuconfig(void) +{ + uint32_t regval; + + /* Clear CONTROL.FPCA so that we do not get the extended context frame + * with the volatile FP registers stacked in the saved context. + */ + + regval = getcontrol(); + regval &= ~(1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to keep CONTROL.FPCA off for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2 * 10)) | (3 << (2 * 11))); + putreg32(regval, NVIC_CPACR); +} + +# endif + +#else +# define fpuconfig() +#endif + /**************************************************************************** * Name: _start * diff --git a/boards/arm/cxd56xx/spresense/README.txt b/boards/arm/cxd56xx/spresense/README.txt index fc4daf3d388..cb94798cf89 100644 --- a/boards/arm/cxd56xx/spresense/README.txt +++ b/boards/arm/cxd56xx/spresense/README.txt @@ -22,6 +22,11 @@ about this board. Configuration sub-directories ----------------------------- + smp + + This is a configuration to run Spresense in SMP mode. To use this + configuration, new boot loader which will be released later must be used. + wifi This is a configuration for Spresense + Wi-Fi addon (Telit GS2200M) module. diff --git a/boards/arm/cxd56xx/spresense/configs/smp/defconfig b/boards/arm/cxd56xx/spresense/configs/smp/defconfig new file mode 100644 index 00000000000..c91264954be --- /dev/null +++ b/boards/arm/cxd56xx/spresense/configs/smp/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_CXD56_I2C0_SCUSEQ is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="spresense" +CONFIG_ARCH_BOARD_SPRESENSE=y +CONFIG_ARCH_CHIP="cxd56xx" +CONFIG_ARCH_CHIP_CXD56XX=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LOOPSPERMSEC=5434 +CONFIG_BOOT_RUNFROMISRAM=y +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_CXD56_BINARY=y +CONFIG_CXD56_I2C0=y +CONFIG_CXD56_I2C=y +CONFIG_CXD56_SPI4=y +CONFIG_CXD56_SPI5=y +CONFIG_CXD56_SPI=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_RAM_SIZE=1572864 +CONFIG_RAM_START=0x0d000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_INSTRUMENTATION=y +CONFIG_SCHED_INSTRUMENTATION_BUFFER=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SMP=y +CONFIG_SMP_NCPUS=2 +CONFIG_SPI=y +CONFIG_SPINLOCK_IRQ=y +CONFIG_START_DAY=3 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_CLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_CXXINITIALIZE=y +CONFIG_SYSTEM_TASKSET=y +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_FPUSIZE=64 +CONFIG_TESTING_SMP=y +CONFIG_UART1_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="spresense_main"