diff --git a/arch/risc-v/src/mpfs/Kconfig b/arch/risc-v/src/mpfs/Kconfig
index 99eec4bd0da..dc4e3984d0d 100644
--- a/arch/risc-v/src/mpfs/Kconfig
+++ b/arch/risc-v/src/mpfs/Kconfig
@@ -452,7 +452,12 @@ config MPFS_CORESPI
 
 config MPFS_CORESPI_BASE
 	hex "Base address for the (first) CoreSPI instance"
-	default 0x4A000000
+	default 0x4B008000
+	depends on MPFS_CORESPI
+
+config MPFS_CORESPI_INST_OFFSET
+	hex "Offset of instances in memory, base + n * offset finds instance n"
+	default 0x1000
 	depends on MPFS_CORESPI
 
 config MPFS_CORESPI_INSTANCES
@@ -463,10 +468,15 @@ config MPFS_CORESPI_INSTANCES
 
 config MPFS_CORESPI_IRQNUM
 	int "Number of (first) F2H interrupt"
-	default 4
+	default 20
 	range 0 63
 	depends on MPFS_CORESPI
 
+config MPFS_CORESPI_IRQNUM_OFFSET
+	int "Offset of interrupt source for instance n"
+	default 1
+	depends on MPFS_CORESPI
+
 endif # MPFS_HAVE_CORESPI
 
 comment "CorePWM Options"
diff --git a/arch/risc-v/src/mpfs/mpfs_corespi.c b/arch/risc-v/src/mpfs/mpfs_corespi.c
index ecd5a177d27..6180fa5ff16 100644
--- a/arch/risc-v/src/mpfs/mpfs_corespi.c
+++ b/arch/risc-v/src/mpfs/mpfs_corespi.c
@@ -90,8 +90,8 @@
 #define MPFS_CORESPI_BASE           CONFIG_MPFS_CORESPI_BASE
 #define MPFS_CORESPI_IRQNUM         (MPFS_IRQ_FABRIC_F2H_0 + \
                                      CONFIG_MPFS_CORESPI_IRQNUM)
-#define MPFS_CORESPI_INST_OFFSET(n) ((n) * 0x1000000)
-#define MPFS_CORESPI_IRQ_OFFSET(n)  ((n) * 1)
+#define MPFS_CORESPI_INST_OFFSET(n) ((n) * CONFIG_MPFS_CORESPI_INST_OFFSET)
+#define MPFS_CORESPI_IRQ_OFFSET(n)  ((n) * CONFIG_MPFS_CORESPI_IRQNUM_OFFSET)
 
 /* Gives TTOA in microseconds, ~4.8% bias, +1 rounds up */