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arch/arm/src/am335x/hardware: Add register description files for I2C (plus various improvements to the WDOG register definitions)

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This commit is contained in:
Petro Karashchenko
2019-07-06 09:24:53 -06:00
committed by Gregory Nutt
parent feb0d0ad67
commit 4af30628b6
4 changed files with 369 additions and 70 deletions
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arch/arm/src/am335x/am335x_wdog.c
+4 -4
View File
@@ -58,13 +58,13 @@
void am335x_wdog_disable_all(void) void am335x_wdog_disable_all(void)
{ {
putreg32(WDT_WSPR_STOP_FEED_A, AM335X_WDT_WSPR); putreg32(WDT_SPR_STOP_FEED_A, AM335X_WDT_SPR);
while ((getreg32(AM335X_WDT_WWPS) & WDT_WWPS_W_PEND_WSPR) != 0) while ((getreg32(AM335X_WDT_WPS) & WDT_WPS_W_PEND_WSPR) != 0)
{ {
} }
putreg32(WDT_WSPR_STOP_FEED_B, AM335X_WDT_WSPR); putreg32(WDT_SPR_STOP_FEED_B, AM335X_WDT_SPR);
while ((getreg32(AM335X_WDT_WWPS) & WDT_WWPS_W_PEND_WSPR) != 0) while ((getreg32(AM335X_WDT_WPS) & WDT_WPS_W_PEND_WSPR) != 0)
{ {
} }
} }
arch/arm/src/am335x/hardware/am335x_i2c.h
+299
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@@ -0,0 +1,299 @@
/************************************************************************************
* arch/arm/src/am335x/hardware/am335x_i2c.h
*
* Copyright (C) 2019 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_I2C_H
#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_I2C_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "hardware/am335x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define AM335X_I2C_SYSC_OFFSET 0x0010
#define AM335X_I2C_IRQ_STAT_RAW_OFFSET 0x0024
#define AM335X_I2C_IRQ_STAT_OFFSET 0x0028
#define AM335X_I2C_IRQ_EN_SET_OFFSET 0x002c
#define AM335X_I2C_IRQ_EN_CLR_OFFSET 0x0030
#define AM335X_I2C_WE_OFFSET 0x0034
#define AM335X_I2C_DMA_RX_EN_SET_OFFSET 0x0038
#define AM335X_I2C_DMA_TX_EN_SET_OFFSET 0x003c
#define AM335X_I2C_DMA_RX_EN_CLR_OFFSET 0x0040
#define AM335X_I2C_DMA_TX_EN_CLR_OFFSET 0x0044
#define AM335X_I2C_DMA_RX_WAKE_EN_OFFSET 0x0048
#define AM335X_I2C_DMA_TX_WAKE_EN_OFFSET 0x004c
#define AM335X_I2C_SYSS_OFFSET 0x0090
#define AM335X_I2C_BUF_OFFSET 0x0094
#define AM335X_I2C_CNT_OFFSET 0x0098
#define AM335X_I2C_DATA_OFFSET 0x009c
#define AM335X_I2C_CON_OFFSET 0x00a4
#define AM335X_I2C_OA_OFFSET 0x00a8
#define AM335X_I2C_SA_OFFSET 0x00ac
#define AM335X_I2C_PSC_OFFSET 0x00b0
#define AM335X_I2C_SCLL_OFFSET 0x00b4
#define AM335X_I2C_SCLH_OFFSET 0x00b8
#define AM335X_I2C_SYSTEST_OFFSET 0x00bc
#define AM335X_I2C_BUFSTAT_OFFSET 0x00c0
#define AM335X_I2C_OA1_OFFSET 0x00c4
#define AM335X_I2C_OA2_OFFSET 0x00c8
#define AM335X_I2C_OA3_OFFSET 0x00cc
#define AM335X_I2C_ACTOA_OFFSET 0x00d0
#define AM335X_I2C_SBLOCK_OFFSET 0x00d4
/* Register virtual addresses *******************************************************/
#define AM335X_I2C0_SYSC (AM335X_I2C0_VADDR + AM335X_I2C_SYSC_OFFSET)
#define AM335X_I2C0_IRQ_STAT_RAW (AM335X_I2C0_VADDR + AM335X_I2C_IRQ_STAT_RAW_OFFSET)
#define AM335X_I2C0_IRQ_STAT (AM335X_I2C0_VADDR + AM335X_I2C_IRQ_STAT_OFFSET)
#define AM335X_I2C0_IRQ_EN_SET (AM335X_I2C0_VADDR + AM335X_I2C_IRQ_EN_SET_OFFSET)
#define AM335X_I2C0_IRQ_EN_CLR (AM335X_I2C0_VADDR + AM335X_I2C_IRQ_EN_CLR_OFFSET)
#define AM335X_I2C0_WE (AM335X_I2C0_VADDR + AM335X_I2C_WE_OFFSET)
#define AM335X_I2C0_DMA_RX_EN_SET (AM335X_I2C0_VADDR + AM335X_I2C_DMA_RX_EN_SET_OFFSET)
#define AM335X_I2C0_DMA_TX_EN_SET (AM335X_I2C0_VADDR + AM335X_I2C_DMA_TX_EN_SET_OFFSET)
#define AM335X_I2C0_DMA_RX_EN_CLR (AM335X_I2C0_VADDR + AM335X_I2C_DMA_RX_EN_CLR_OFFSET)
#define AM335X_I2C0_DMA_TX_EN_CLR (AM335X_I2C0_VADDR + AM335X_I2C_DMA_TX_EN_CLR_OFFSET)
#define AM335X_I2C0_DMA_RX_WAKE_EN (AM335X_I2C0_VADDR + AM335X_I2C_DMA_RX_WAKE_EN_OFFSET)
#define AM335X_I2C0_DMA_TX_WAKE_EN (AM335X_I2C0_VADDR + AM335X_I2C_DMA_TX_WAKE_EN_OFFSET)
#define AM335X_I2C0_SYSS (AM335X_I2C0_VADDR + AM335X_I2C_SYSS_OFFSET)
#define AM335X_I2C0_BUF (AM335X_I2C0_VADDR + AM335X_I2C_BUF_OFFSET)
#define AM335X_I2C0_CNT (AM335X_I2C0_VADDR + AM335X_I2C_CNT_OFFSET)
#define AM335X_I2C0_DATA (AM335X_I2C0_VADDR + AM335X_I2C_DATA_OFFSET)
#define AM335X_I2C0_CON (AM335X_I2C0_VADDR + AM335X_I2C_CON_OFFSET)
#define AM335X_I2C0_OA (AM335X_I2C0_VADDR + AM335X_I2C_OA_OFFSET)
#define AM335X_I2C0_SA (AM335X_I2C0_VADDR + AM335X_I2C_SA_OFFSET)
#define AM335X_I2C0_PSC (AM335X_I2C0_VADDR + AM335X_I2C_PSC_OFFSET)
#define AM335X_I2C0_SCLL (AM335X_I2C0_VADDR + AM335X_I2C_SCLL_OFFSET)
#define AM335X_I2C0_SCLH (AM335X_I2C0_VADDR + AM335X_I2C_SCLH_OFFSET)
#define AM335X_I2C0_SYSTEST (AM335X_I2C0_VADDR + AM335X_I2C_SYSTEST_OFFSET)
#define AM335X_I2C0_BUFSTAT (AM335X_I2C0_VADDR + AM335X_I2C_BUFSTAT_OFFSET)
#define AM335X_I2C0_OA1 (AM335X_I2C0_VADDR + AM335X_I2C_OA1_OFFSET)
#define AM335X_I2C0_OA2 (AM335X_I2C0_VADDR + AM335X_I2C_OA2_OFFSET)
#define AM335X_I2C0_OA3 (AM335X_I2C0_VADDR + AM335X_I2C_OA3_OFFSET)
#define AM335X_I2C0_ACTOA (AM335X_I2C0_VADDR + AM335X_I2C_ACTOA_OFFSET)
#define AM335X_I2C0_SBLOCK (AM335X_I2C0_VADDR + AM335X_I2C_SBLOCK_OFFSET)
#define AM335X_I2C1_SYSC (AM335X_I2C1_VADDR + AM335X_I2C_SYSC_OFFSET)
#define AM335X_I2C1_IRQ_STAT_RAW (AM335X_I2C1_VADDR + AM335X_I2C_IRQ_STAT_RAW_OFFSET)
#define AM335X_I2C1_IRQ_STAT (AM335X_I2C1_VADDR + AM335X_I2C_IRQ_STAT_OFFSET)
#define AM335X_I2C1_IRQ_EN_SET (AM335X_I2C1_VADDR + AM335X_I2C_IRQ_EN_SET_OFFSET)
#define AM335X_I2C1_IRQ_EN_CLR (AM335X_I2C1_VADDR + AM335X_I2C_IRQ_EN_CLR_OFFSET)
#define AM335X_I2C1_WE (AM335X_I2C1_VADDR + AM335X_I2C_WE_OFFSET)
#define AM335X_I2C1_DMA_RX_EN_SET (AM335X_I2C1_VADDR + AM335X_I2C_DMA_RX_EN_SET_OFFSET)
#define AM335X_I2C1_DMA_TX_EN_SET (AM335X_I2C1_VADDR + AM335X_I2C_DMA_TX_EN_SET_OFFSET)
#define AM335X_I2C1_DMA_RX_EN_CLR (AM335X_I2C1_VADDR + AM335X_I2C_DMA_RX_EN_CLR_OFFSET)
#define AM335X_I2C1_DMA_TX_EN_CLR (AM335X_I2C1_VADDR + AM335X_I2C_DMA_TX_EN_CLR_OFFSET)
#define AM335X_I2C1_DMA_RX_WAKE_EN (AM335X_I2C1_VADDR + AM335X_I2C_DMA_RX_WAKE_EN_OFFSET)
#define AM335X_I2C1_DMA_TX_WAKE_EN (AM335X_I2C1_VADDR + AM335X_I2C_DMA_TX_WAKE_EN_OFFSET)
#define AM335X_I2C1_SYSS (AM335X_I2C1_VADDR + AM335X_I2C_SYSS_OFFSET)
#define AM335X_I2C1_BUF (AM335X_I2C1_VADDR + AM335X_I2C_BUF_OFFSET)
#define AM335X_I2C1_CNT (AM335X_I2C1_VADDR + AM335X_I2C_CNT_OFFSET)
#define AM335X_I2C1_DATA (AM335X_I2C1_VADDR + AM335X_I2C_DATA_OFFSET)
#define AM335X_I2C1_CON (AM335X_I2C1_VADDR + AM335X_I2C_CON_OFFSET)
#define AM335X_I2C1_OA (AM335X_I2C1_VADDR + AM335X_I2C_OA_OFFSET)
#define AM335X_I2C1_SA (AM335X_I2C1_VADDR + AM335X_I2C_SA_OFFSET)
#define AM335X_I2C1_PSC (AM335X_I2C1_VADDR + AM335X_I2C_PSC_OFFSET)
#define AM335X_I2C1_SCLL (AM335X_I2C1_VADDR + AM335X_I2C_SCLL_OFFSET)
#define AM335X_I2C1_SCLH (AM335X_I2C1_VADDR + AM335X_I2C_SCLH_OFFSET)
#define AM335X_I2C1_SYSTEST (AM335X_I2C1_VADDR + AM335X_I2C_SYSTEST_OFFSET)
#define AM335X_I2C1_BUFSTAT (AM335X_I2C1_VADDR + AM335X_I2C_BUFSTAT_OFFSET)
#define AM335X_I2C1_OA1 (AM335X_I2C1_VADDR + AM335X_I2C_OA1_OFFSET)
#define AM335X_I2C1_OA2 (AM335X_I2C1_VADDR + AM335X_I2C_OA2_OFFSET)
#define AM335X_I2C1_OA3 (AM335X_I2C1_VADDR + AM335X_I2C_OA3_OFFSET)
#define AM335X_I2C1_ACTOA (AM335X_I2C1_VADDR + AM335X_I2C_ACTOA_OFFSET)
#define AM335X_I2C1_SBLOCK (AM335X_I2C1_VADDR + AM335X_I2C_SBLOCK_OFFSET)
#define AM335X_I2C2_SYSC (AM335X_I2C2_VADDR + AM335X_I2C_SYSC_OFFSET)
#define AM335X_I2C2_IRQ_STAT_RAW (AM335X_I2C2_VADDR + AM335X_I2C_IRQ_STAT_RAW_OFFSET)
#define AM335X_I2C2_IRQ_STAT (AM335X_I2C2_VADDR + AM335X_I2C_IRQ_STAT_OFFSET)
#define AM335X_I2C2_IRQ_EN_SET (AM335X_I2C2_VADDR + AM335X_I2C_IRQ_EN_SET_OFFSET)
#define AM335X_I2C2_IRQ_EN_CLR (AM335X_I2C2_VADDR + AM335X_I2C_IRQ_EN_CLR_OFFSET)
#define AM335X_I2C2_WE (AM335X_I2C2_VADDR + AM335X_I2C_WE_OFFSET)
#define AM335X_I2C2_DMA_RX_EN_SET (AM335X_I2C2_VADDR + AM335X_I2C_DMA_RX_EN_SET_OFFSET)
#define AM335X_I2C2_DMA_TX_EN_SET (AM335X_I2C2_VADDR + AM335X_I2C_DMA_TX_EN_SET_OFFSET)
#define AM335X_I2C2_DMA_RX_EN_CLR (AM335X_I2C2_VADDR + AM335X_I2C_DMA_RX_EN_CLR_OFFSET)
#define AM335X_I2C2_DMA_TX_EN_CLR (AM335X_I2C2_VADDR + AM335X_I2C_DMA_TX_EN_CLR_OFFSET)
#define AM335X_I2C2_DMA_RX_WAKE_EN (AM335X_I2C2_VADDR + AM335X_I2C_DMA_RX_WAKE_EN_OFFSET)
#define AM335X_I2C2_DMA_TX_WAKE_EN (AM335X_I2C2_VADDR + AM335X_I2C_DMA_TX_WAKE_EN_OFFSET)
#define AM335X_I2C2_SYSS (AM335X_I2C2_VADDR + AM335X_I2C_SYSS_OFFSET)
#define AM335X_I2C2_BUF (AM335X_I2C2_VADDR + AM335X_I2C_BUF_OFFSET)
#define AM335X_I2C2_CNT (AM335X_I2C2_VADDR + AM335X_I2C_CNT_OFFSET)
#define AM335X_I2C2_DATA (AM335X_I2C2_VADDR + AM335X_I2C_DATA_OFFSET)
#define AM335X_I2C2_CON (AM335X_I2C2_VADDR + AM335X_I2C_CON_OFFSET)
#define AM335X_I2C2_OA (AM335X_I2C2_VADDR + AM335X_I2C_OA_OFFSET)
#define AM335X_I2C2_SA (AM335X_I2C2_VADDR + AM335X_I2C_SA_OFFSET)
#define AM335X_I2C2_PSC (AM335X_I2C2_VADDR + AM335X_I2C_PSC_OFFSET)
#define AM335X_I2C2_SCLL (AM335X_I2C2_VADDR + AM335X_I2C_SCLL_OFFSET)
#define AM335X_I2C2_SCLH (AM335X_I2C2_VADDR + AM335X_I2C_SCLH_OFFSET)
#define AM335X_I2C2_SYSTEST (AM335X_I2C2_VADDR + AM335X_I2C_SYSTEST_OFFSET)
#define AM335X_I2C2_BUFSTAT (AM335X_I2C2_VADDR + AM335X_I2C_BUFSTAT_OFFSET)
#define AM335X_I2C2_OA1 (AM335X_I2C2_VADDR + AM335X_I2C_OA1_OFFSET)
#define AM335X_I2C2_OA2 (AM335X_I2C2_VADDR + AM335X_I2C_OA2_OFFSET)
#define AM335X_I2C2_OA3 (AM335X_I2C2_VADDR + AM335X_I2C_OA3_OFFSET)
#define AM335X_I2C2_ACTOA (AM335X_I2C2_VADDR + AM335X_I2C_ACTOA_OFFSET)
#define AM335X_I2C2_SBLOCK (AM335X_I2C2_VADDR + AM335X_I2C_SBLOCK_OFFSET)
/* Register bit field definitions ***************************************************/
#define I2C_SYSC_AUTOIDLE (1 << 0) /* Bit 0: Autoidle */
#define I2C_SYSC_SRST (1 << 1) /* Bit 1: SoftReset */
#define I2C_SYSC_WAKEUP (1 << 2) /* Bit 2: Enable Wakeup control */
#define I2C_SYSC_IDLE_SHIFT (3) /* Bits 3-4: Idle Mode selection */
#define I2C_SYSC_IDLE_MASK (3 << I2C_SYSC_IDLE_SHIFT)
# define I2C_SYSC_IDLE_FORCE (0 << I2C_SYSC_IDLE_SHIFT) /* Force-idle mode */
# define I2C_SYSC_IDLE_NO (1 << I2C_SYSC_IDLE_SHIFT) /* No-idle mode */
# define I2C_SYSC_IDLE_SMART (2 << I2C_SYSC_IDLE_SHIFT) /* Smart-idle mode */
# define I2C_SYSC_IDLE_SMART_WKUP (3 << I2C_SYSC_IDLE_SHIFT) /* Smart-idle Wakeup mode */
#define I2C_SYSC_CLK_SHIFT (8) /* Bits 8-9: Clock Activity selection */
#define I2C_SYSC_CLK_MASK (3 << I2C_SYSC_CLK_SHIFT)
# define I2C_SYSC_CLK_NONE (0 << I2C_SYSC_CLK_SHIFT) /* Both clocks can be cut off */
# define I2C_SYSC_CLK_OCP (1 << I2C_SYSC_CLK_SHIFT) /* Only Interface/OCP clock must be kept active */
# define I2C_SYSC_CLK_SYS (2 << I2C_SYSC_CLK_SHIFT) /* Only system clock must be kept active */
# define I2C_SYSC_CLK_BOTH (3 << I2C_SYSC_CLK_SHIFT) /* Both clocks must be kept active */
#define I2C_IRQ_AL (1 << 0) /* Bit 0: Arbitration lost */
#define I2C_IRQ_NACK (1 << 1) /* Bit 1: No acknowledgment */
#define I2C_IRQ_ARDY (1 << 2) /* Bit 2: Register access ready */
#define I2C_IRQ_RRDY (1 << 3) /* Bit 3: Receive data ready */
#define I2C_IRQ_XRDY (1 << 4) /* Bit 4: Transmit data ready */
#define I2C_IRQ_GC (1 << 5) /* Bit 5: General call */
#define I2C_IRQ_STC (1 << 6) /* Bit 6: Start Condition */
#define I2C_IRQ_AERR (1 << 7) /* Bit 7: Access Error */
#define I2C_IRQ_BF (1 << 8) /* Bit 8: Bus Free */
#define I2C_IRQ_AAS (1 << 9) /* Bit 9: Address recognized as slave */
#define I2C_IRQ_XUDF (1 << 10) /* Bit 10: Transmit underflow */
#define I2C_IRQ_ROVR (1 << 11) /* Bit 11: Receive overrun */
#define I2C_IRQ_BB (1 << 12) /* Bit 12: Bus busy */
#define I2C_IRQ_RDR (1 << 13) /* Bit 13: Receive draining IRQ */
#define I2C_IRQ_XDR (1 << 14) /* Bit 14: Transmit draining IRQ */
#define I2C_WE_AL (1 << 0) /* Bit 0: Arbitration lost */
#define I2C_WE_NACK (1 << 1) /* Bit 1: No acknowledgment */
#define I2C_WE_ARDY (1 << 2) /* Bit 2: Register access ready */
#define I2C_WE_DRDY (1 << 3) /* Bit 3: Receive/Transmit data ready */
#define I2C_WE_GC (1 << 5) /* Bit 5: General call */
#define I2C_WE_STC (1 << 6) /* Bit 6: Start Condition */
#define I2C_WE_BF (1 << 8) /* Bit 8: Bus Free */
#define I2C_WE_AAS (1 << 9) /* Bit 9: Address recognized as slave */
#define I2C_WE_XUDF (1 << 10) /* Bit 10: Transmit underflow */
#define I2C_WE_ROVR (1 << 11) /* Bit 11: Receive overrun */
#define I2C_WE_RDR (1 << 13) /* Bit 13: Receive draining IRQ */
#define I2C_WE_XDR (1 << 14) /* Bit 14: Transmit draining IRQ */
#define I2C_DMA_ENABLE (1 << 0) /* Bit 0: DMA channel enable */
#define I2C_SYSS_RST_DONE (1 << 0) /* Bit 0: Reset done */
#define I2C_BUF_TXTRSH_SHIFT (0) /* Bits 0-5: Threshold value for FIFO buffer in TX mode */
#define I2C_BUF_TXTRSH_MASK (63 << I2C_BUF_TXTRSH_SHIFT)
#define I2C_BUF_TXFIFO_CLR (1 << 6) /* Bit 6: Transmit FIFO clear */
#define I2C_BUF_XDMA_EN (1 << 7) /* Bit 7: Transmit DMA channel enable */
#define I2C_BUF_RXTRSH_SHIFT (8) /* Bits 8-13: Threshold value for FIFO buffer in RX mode */
#define I2C_BUF_RXTRSH_MASK (63 << I2C_BUF_RXTRSH_SHIFT)
#define I2C_BUF_RXFIFO_CLR (1 << 14) /* Bit 14: Receive FIFO clear */
#define I2C_BUF_RDMA_EN (1 << 15) /* Bit 15: Receive DMA channel enable */
#define I2C_CNT_SHIFT (0) /* Bits 0-15: Data count */
#define I2C_CNT_MASK (65535 << I2C_CNT_SHIFT)
#define I2C_DATA_SHIFT (0) /* Bits 0-7: Transmit/Receive data FIFO endpoint */
#define I2C_DATA_MASK (255 << I2C_DATA_SHIFT)
#define I2C_CON_STT (1 << 0) /* Bit 0: Start condition (I2C master mode only) */
#define I2C_CON_STP (1 << 1) /* Bit 1: Stop condition (I2C master mode only) */
#define I2C_CON_XOA3 (1 << 4) /* Bit 4: Expand own address 3 */
#define I2C_CON_XOA2 (1 << 5) /* Bit 5: Expand own address 2 */
#define I2C_CON_XOA1 (1 << 6) /* Bit 6: Expand own address 1 */
#define I2C_CON_XOA0 (1 << 7) /* Bit 7: Expand own address 0 */
#define I2C_CON_XSA (1 << 8) /* Bit 8: Expand slave address */
#define I2C_CON_TRX (1 << 9) /* Bit 9: Transmitter/receiver mode (I2C master mode only) */
#define I2C_CON_MST (1 << 10) /* Bit 10: Master/slave mode */
#define I2C_CON_STB (1 << 11) /* Bit 11: Start byte mode (I2C master mode only) */
#define I2C_CON_OPMODE_SHIFT (1 << 12) /* Bits 12-13: Operation mode selection */
#define I2C_CON_OPMODE_MASK (3 << I2C_CON_OPMODE_SHIFT)
# define I2C_CON_OPMODE_FAST (0 << I2C_CON_OPMODE_SHIFT)
#define I2C_CON_EN (1 << 15) /* Bit 15: I2C module enable */
#define I2C_SA_SHIFT (0) /* Bits 0-9: Slave address */
#define I2C_SA_MASK (0x3ff << I2C_SA_SHIFT)
#define I2C_PSC_SHIFT (0) /* Bits 0-7: Fast/Standard mode prescale sampling clock divider */
#define I2C_PSC_MASK (255 << I2C_PSC_SHIFT)
#define I2C_SCLL_SHIFT (0) /* Bits 0-7: Fast/Standard mode SCL low time */
#define I2C_SCLL_MASK (255 << I2C_SCLL_SHIFT)
#define I2C_SCLH_SHIFT (0) /* Bits 0-7: Fast/Standard mode SCL high time. */
#define I2C_SCLH_MASK (255 << I2C_SCLH_SHIFT)
#define I2C_SYSTEST_SDA_O (1 << 0) /* Bit 0: SDA line drive output value */
#define I2C_SYSTEST_SDA_I (1 << 1) /* Bit 1: SDA line sense input value */
#define I2C_SYSTEST_SCL_O (1 << 2) /* Bit 2: SCL line drive output value */
#define I2C_SYSTEST_SCL_I (1 << 3) /* Bit 3: SCL line sense input value */
#define I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* Bit 5: SDA line output value (functional mode) */
#define I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* Bit 6: SDA line input value (functional mode) */
#define I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* Bit 7: SCL line output value (functional mode) */
#define I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* Bit 8: SCL line input value (functional mode) */
#define I2C_SYSTEST_SSB (1 << 11) /* Bit 11: Set status bits */
#define I2C_SYSTEST_TMODE_SHIFT (12) /* Bits 12-13: Test mode select */
#define I2C_SYSTEST_TMODE_MASK (3 << I2C_SYSTEST_TMODE_SHIFT)
# define I2C_SYSTEST_TMODE_FUNC (0 << I2C_SYSTEST_TMODE_SHIFT) /* Functional mode */
# define I2C_SYSTEST_TMODE_SCL (2 << I2C_SYSTEST_TMODE_SHIFT) /* Test of SCL counters (SCLL, SCLH, PSC) */
# define I2C_SYSTEST_TMODE_LOOPBACK (3 << I2C_SYSTEST_TMODE_SHIFT) /* Loop back mode select + SDA/SCL IO mode select */
#define I2C_SYSTEST_FREE (1 << 14) /* Bit 14: Free running mode (on breakpoint) */
#define I2C_SYSTEST_ST_EN (1 << 15) /* Bit 15: System test enable */
#define I2C_BUFSTAT_TXSTAT_SHIFT (0) /* Bits 0-5: TX buffer status */
#define I2C_BUFSTAT_TXSTAT_MASK (63 << I2C_BUFSTAT_TXSTAT_SHIFT)
#define I2C_BUFSTAT_RXSTAT_SHIFT (8) /* Bits 8-13: RX buffer status */
#define I2C_BUFSTAT_RXSTAT_MASK (63 << I2C_BUFSTAT_RXSTAT_SHIFT)
#define I2C_BUFSTAT_FIFODEPTH_SHIFT (14) /* Bits 14-15: Internal FIFO buffers depth */
#define I2C_BUFSTAT_FIFODEPTH_MASK (3 << I2C_BUFSTAT_FIFODEPTH_SHIFT)
#define I2C_OA_SHIFT (0) /* Bits 0-9: Own address */
#define I2C_OA_MASK (0x3ff << I2C_OA_SHIFT)
#define I2C_OA0_SELECT (1 << 0) /* Bit 0: Own address 0 */
#define I2C_OA1_SELECT (1 << 1) /* Bit 1: Own address 1 */
#define I2C_OA2_SELECT (1 << 2) /* Bit 2: Own address 2 */
#define I2C_OA3_SELECT (1 << 3) /* Bit 3: Own address 3 */
#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_I2C_H */
arch/arm/src/am335x/hardware/am335x_lcd.h
+12 -12
View File
@@ -69,7 +69,7 @@
#define AM335X_LCD_DMA_FB0_CEIL_OFFSET 0x0048 #define AM335X_LCD_DMA_FB0_CEIL_OFFSET 0x0048
#define AM335X_LCD_DMA_FB1_BASE_OFFSET 0x004c #define AM335X_LCD_DMA_FB1_BASE_OFFSET 0x004c
#define AM335X_LCD_DMA_FB1_CEIL_OFFSET 0x0050 #define AM335X_LCD_DMA_FB1_CEIL_OFFSET 0x0050
#define AM335X_LCD_SYSCONFIG_OFFSET 0x0054 #define AM335X_LCD_SYSC_OFFSET 0x0054
#define AM335X_LCD_IRQ_STAT_RAW_OFFSET 0x0058 #define AM335X_LCD_IRQ_STAT_RAW_OFFSET 0x0058
#define AM335X_LCD_IRQ_STAT_OFFSET 0x005c #define AM335X_LCD_IRQ_STAT_OFFSET 0x005c
#define AM335X_LCD_IRQ_EN_SET_OFFSET 0x0060 #define AM335X_LCD_IRQ_EN_SET_OFFSET 0x0060
@@ -105,7 +105,7 @@
#define AM335X_LCD_DMA_FB0_CEIL (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB0_CEIL_OFFSET) #define AM335X_LCD_DMA_FB0_CEIL (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB0_CEIL_OFFSET)
#define AM335X_LCD_DMA_FB1_BASE (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB1_BASE_OFFSET) #define AM335X_LCD_DMA_FB1_BASE (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB1_BASE_OFFSET)
#define AM335X_LCD_DMA_FB1_CEIL (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB1_CEIL_OFFSET) #define AM335X_LCD_DMA_FB1_CEIL (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB1_CEIL_OFFSET)
#define AM335X_LCD_SYSCONFIG (AM335X_LCD_VADDR + AM335X_LCD_SYSCONFIG_OFFSET) #define AM335X_LCD_SYSC (AM335X_LCD_VADDR + AM335X_LCD_SYSC_OFFSET)
#define AM335X_LCD_IRQ_STAT_RAW (AM335X_LCD_VADDR + AM335X_LCD_IRQ_STAT_RAW_OFFSET) #define AM335X_LCD_IRQ_STAT_RAW (AM335X_LCD_VADDR + AM335X_LCD_IRQ_STAT_RAW_OFFSET)
#define AM335X_LCD_IRQ_STAT (AM335X_LCD_VADDR + AM335X_LCD_IRQ_STAT_OFFSET) #define AM335X_LCD_IRQ_STAT (AM335X_LCD_VADDR + AM335X_LCD_IRQ_STAT_OFFSET)
#define AM335X_LCD_IRQ_EN_SET (AM335X_LCD_VADDR + AM335X_LCD_IRQ_EN_SET_OFFSET) #define AM335X_LCD_IRQ_EN_SET (AM335X_LCD_VADDR + AM335X_LCD_IRQ_EN_SET_OFFSET)
@@ -256,16 +256,16 @@
#define LCD_DMA_FB_CEIL_SHIFT (2) /* Bits 2-31: Frame Buffer Ceiling Address pointer */ #define LCD_DMA_FB_CEIL_SHIFT (2) /* Bits 2-31: Frame Buffer Ceiling Address pointer */
#define LCD_DMA_FB_CEIL_MASK (0x3fffffff << LCD_DMA_FB_BASE_SHIFT) #define LCD_DMA_FB_CEIL_MASK (0x3fffffff << LCD_DMA_FB_BASE_SHIFT)
#define LCD_SYSCONFIG_IDLE_SHIFT (2) /* Bits 2-3: Configuration of the local target state management mode */ #define LCD_SYSC_IDLE_SHIFT (2) /* Bits 2-3: Configuration of the local target state management mode */
#define LCD_SYSCONFIG_IDLE_MASK (3 << LCD_SYSCONFIG_IDLE_SHIFT) #define LCD_SYSC_IDLE_MASK (3 << LCD_SYSC_IDLE_SHIFT)
# define LCD_SYSCONFIG_IDLE_FORCE (0 << LCD_SYSCONFIG_IDLEMODE_SHIFT) /* Force-idle mode */ # define LCD_SYSC_IDLE_FORCE (0 << LCD_SYSC_IDLE_SHIFT) /* Force-idle mode */
# define LCD_SYSCONFIG_IDLE_NO (1 << LCD_SYSCONFIG_IDLEMODE_SHIFT) /* No-idle mode */ # define LCD_SYSC_IDLE_NO (1 << LCD_SYSC_IDLE_SHIFT) /* No-idle mode */
# define LCD_SYSCONFIG_IDLE_SMART (2 << LCD_SYSCONFIG_IDLEMODE_SHIFT) /* Smart-idle mode */ # define LCD_SYSC_IDLE_SMART (2 << LCD_SYSC_IDLE_SHIFT) /* Smart-idle mode */
#define LCD_SYSCONFIG_STANDBY_SHIFT (4) /* Bits 4-5: Configuration of the local initiator state management mode */ #define LCD_SYSC_STANDBY_SHIFT (4) /* Bits 4-5: Configuration of the local initiator state management mode */
#define LCD_SYSCONFIG_STANDBY_MASK (3 << LCD_SYSCONFIG_STANDBY_SHIFT) #define LCD_SYSC_STANDBY_MASK (3 << LCD_SYSC_STANDBY_SHIFT)
# define LCD_SYSCONFIG_STANDBY_FORCE (0 << LCD_SYSCONFIG_STANDBY_SHIFT) /* Force-standby mode */ # define LCD_SYSC_STANDBY_FORCE (0 << LCD_SYSC_STANDBY_SHIFT) /* Force-standby mode */
# define LCD_SYSCONFIG_STANDBY_NO (1 << LCD_SYSCONFIG_STANDBY_SHIFT) /* No-standby mode */ # define LCD_SYSC_STANDBY_NO (1 << LCD_SYSC_STANDBY_SHIFT) /* No-standby mode */
# define LCD_SYSCONFIG_STANDBY_SMART (2 << LCD_SYSCONFIG_STANDBY_SHIFT) /* Smart-standby mode */ # define LCD_SYSC_STANDBY_SMART (2 << LCD_SYSC_STANDBY_SHIFT) /* Smart-standby mode */
#define LCD_IRQ_DONE (1 << 0) /* Bit 0: Raster or LIDD Frame Done */ #define LCD_IRQ_DONE (1 << 0) /* Bit 0: Raster or LIDD Frame Done */
#define LCD_IRQ_RR_DONE (1 << 1) /* Bit 1: Raster Mode Frame Done */ #define LCD_IRQ_RR_DONE (1 << 1) /* Bit 1: Raster Mode Frame Done */
arch/arm/src/am335x/hardware/am335x_wdog.h
+54 -54
View File
@@ -49,57 +49,57 @@
/* Register offsets *****************************************************************/ /* Register offsets *****************************************************************/
#define AM335X_WDT_WIDR_OFFSET 0x0000 /* Watchdog Identification Register */ #define AM335X_WDT_IDR_OFFSET 0x0000 /* Watchdog Identification Register */
#define AM335X_WDT_WDSC_OFFSET 0x0010 /* Watchdog System Control Register */ #define AM335X_WDT_DSC_OFFSET 0x0010 /* Watchdog System Control Register */
#define AM335X_WDT_WDST_OFFSET 0x0014 /* Watchdog Status Register */ #define AM335X_WDT_DST_OFFSET 0x0014 /* Watchdog Status Register */
#define AM335X_WDT_WISR_OFFSET 0x0018 /* Watchdog Interrupt Status Register */ #define AM335X_WDT_ISR_OFFSET 0x0018 /* Watchdog Interrupt Status Register */
#define AM335X_WDT_WIER_OFFSET 0x001C /* Watchdog Interrupt Enable Register */ #define AM335X_WDT_IER_OFFSET 0x001c /* Watchdog Interrupt Enable Register */
#define AM335X_WDT_WCLR_OFFSET 0x0024 /* Watchdog Control Register */ #define AM335X_WDT_CLR_OFFSET 0x0024 /* Watchdog Control Register */
#define AM335X_WDT_WCRR_OFFSET 0x0028 /* Watchdog Counter Register */ #define AM335X_WDT_CRR_OFFSET 0x0028 /* Watchdog Counter Register */
#define AM335X_WDT_WLDR_OFFSET 0x002C /* Watchdog Load Register */ #define AM335X_WDT_LDR_OFFSET 0x002c /* Watchdog Load Register */
#define AM335X_WDT_WTGR_OFFSET 0x0030 /* Watchdog Trigger Register */ #define AM335X_WDT_TGR_OFFSET 0x0030 /* Watchdog Trigger Register */
#define AM335X_WDT_WWPS_OFFSET 0x0034 /* Watchdog Write Posting Bits Register */ #define AM335X_WDT_WPS_OFFSET 0x0034 /* Watchdog Write Posting Bits Register */
#define AM335X_WDT_WDLY_OFFSET 0x0044 /* Watchdog Delay Configuration Register */ #define AM335X_WDT_DLY_OFFSET 0x0044 /* Watchdog Delay Configuration Register */
#define AM335X_WDT_WSPR_OFFSET 0x0048 /* Watchdog Start/Stop Register */ #define AM335X_WDT_SPR_OFFSET 0x0048 /* Watchdog Start/Stop Register */
#define AM335X_WDT_WIRQSTATRAW_OFFSET 0x0054 /* Watchdog Raw Interrupt Status Register */ #define AM335X_WDT_IRQ_STAT_RAW_OFFSET 0x0054 /* Watchdog Raw Interrupt Status Register */
#define AM335X_WDT_WIRQSTAT_OFFSET 0x0058 /* Watchdog Interrupt Status Register */ #define AM335X_WDT_IRQ_STAT_OFFSET 0x0058 /* Watchdog Interrupt Status Register */
#define AM335X_WDT_WIRQENSET_OFFSET 0x005C /* Watchdog Interrupt Enable Set Register */ #define AM335X_WDT_IRQ_EN_SET_OFFSET 0x005c /* Watchdog Interrupt Enable Set Register */
#define AM335X_WDT_WIRQENCLR_OFFSET 0x0060 /* Watchdog Interrupt Enable Clear Register */ #define AM335X_WDT_IRQ_EN_CLR_OFFSET 0x0060 /* Watchdog Interrupt Enable Clear Register */
/* Register addresses ***************************************************************/ /* Register addresses ***************************************************************/
#define AM335X_WDT_WIDR (AM335X_WDT1_VADDR + AM335X_WDT_WIDR_OFFSET) #define AM335X_WDT_IDR (AM335X_WDT1_VADDR + AM335X_WDT_IDR_OFFSET)
#define AM335X_WDT_WDSC (AM335X_WDT1_VADDR + AM335X_WDT_WDSC_OFFSET) #define AM335X_WDT_DSC (AM335X_WDT1_VADDR + AM335X_WDT_DSC_OFFSET)
#define AM335X_WDT_WDST (AM335X_WDT1_VADDR + AM335X_WDT_WDST_OFFSET) #define AM335X_WDT_DST (AM335X_WDT1_VADDR + AM335X_WDT_DST_OFFSET)
#define AM335X_WDT_WISR (AM335X_WDT1_VADDR + AM335X_WDT_WISR_OFFSET) #define AM335X_WDT_ISR (AM335X_WDT1_VADDR + AM335X_WDT_ISR_OFFSET)
#define AM335X_WDT_WIER (AM335X_WDT1_VADDR + AM335X_WDT_WIER_OFFSET) #define AM335X_WDT_IER (AM335X_WDT1_VADDR + AM335X_WDT_IER_OFFSET)
#define AM335X_WDT_WCLR (AM335X_WDT1_VADDR + AM335X_WDT_WCLR_OFFSET) #define AM335X_WDT_CLR (AM335X_WDT1_VADDR + AM335X_WDT_CLR_OFFSET)
#define AM335X_WDT_WCRR (AM335X_WDT1_VADDR + AM335X_WDT_WCRR_OFFSET) #define AM335X_WDT_CRR (AM335X_WDT1_VADDR + AM335X_WDT_CRR_OFFSET)
#define AM335X_WDT_WLDR (AM335X_WDT1_VADDR + AM335X_WDT_WLDR_OFFSET) #define AM335X_WDT_LDR (AM335X_WDT1_VADDR + AM335X_WDT_LDR_OFFSET)
#define AM335X_WDT_WTGR (AM335X_WDT1_VADDR + AM335X_WDT_WTGR_OFFSET) #define AM335X_WDT_TGR (AM335X_WDT1_VADDR + AM335X_WDT_TGR_OFFSET)
#define AM335X_WDT_WWPS (AM335X_WDT1_VADDR + AM335X_WDT_WWPS_OFFSET) #define AM335X_WDT_WPS (AM335X_WDT1_VADDR + AM335X_WDT_WPS_OFFSET)
#define AM335X_WDT_WDLY (AM335X_WDT1_VADDR + AM335X_WDT_WDLY_OFFSET) #define AM335X_WDT_DLY (AM335X_WDT1_VADDR + AM335X_WDT_DLY_OFFSET)
#define AM335X_WDT_WSPR (AM335X_WDT1_VADDR + AM335X_WDT_WSPR_OFFSET) #define AM335X_WDT_SPR (AM335X_WDT1_VADDR + AM335X_WDT_SPR_OFFSET)
#define AM335X_WDT_WIRQSTATRAW (AM335X_WDT1_VADDR + AM335X_WDT_WIRQSTATRAW_OFFSET) #define AM335X_WDT_IRQ_STAT_RAW (AM335X_WDT1_VADDR + AM335X_WDT_IRQ_STAT_RAW_OFFSET)
#define AM335X_WDT_WIRQSTAT (AM335X_WDT1_VADDR + AM335X_WDT_WIRQSTAT_OFFSET) #define AM335X_WDT_IRQ_STAT (AM335X_WDT1_VADDR + AM335X_WDT_IRQ_STAT_OFFSET)
#define AM335X_WDT_WIRQENSET (AM335X_WDT1_VADDR + AM335X_WDT_WIRQENSET_OFFSET) #define AM335X_WDT_IRQ_EN_SET (AM335X_WDT1_VADDR + AM335X_WDT_IRQ_EN_SET_OFFSET)
#define AM335X_WDT_WIRQENCLR (AM335X_WDT1_VADDR + AM335X_WDT_WIRQENCLR_OFFSET) #define AM335X_WDT_IRQ_EN_CLR (AM335X_WDT1_VADDR + AM335X_WDT_IRQ_EN_CLR_OFFSET)
/* Register bit definitions *********************************************************/ /* Register bit definitions *********************************************************/
/* Watchdog System Control Register */ /* Watchdog System Control Register */
#define WDT_WDSC_SOFTRESET (1 << 1) /* Bit 1: Watchdog Software Reset */ #define WDT_DSC_SOFT_RST (1 << 1) /* Bit 1: Watchdog Software Reset */
#define WDT_WDSC_IDLEMODE_SHIFT (3) /* Bit 3-4: Watchdog Idle Mode */ #define WDT_DSC_IDLE_SHIFT (3) /* Bit 3-4: Watchdog Idle Mode */
# define WDT_WDSC_IDLEMODE_FORCE (0 << WDT_WDSC_IDLEMODE_SHIFT) /* Force-idle Mode */ # define WDT_DSC_IDLE_FORCE (0 << WDT_DSC_IDLE_SHIFT) /* Force-idle Mode */
# define WDT_WDSC_IDLEMODE_NO (1 << WDT_WDSC_IDLEMODE_SHIFT) /* No-idle Mode */ # define WDT_DSC_IDLE_NO (1 << WDT_DSC_IDLE_SHIFT) /* No-idle Mode */
# define WDT_WDSC_IDLEMODE_SMART (2 << WDT_WDSC_IDLEMODE_SHIFT) /* Smart-idle Mode */ # define WDT_DSC_IDLE_SMART (2 << WDT_DSC_IDLE_SHIFT) /* Smart-idle Mode */
# define WDT_WDSC_IDLEMODE_SMART_WKUP (3 << WDT_WDSC_IDLEMODE_SHIFT) /* Smart-idle Wakeup-capable Mode */ # define WDT_DSC_IDLE_SMART_WKUP (3 << WDT_DSC_IDLE_SHIFT) /* Smart-idle Wakeup-capable Mode */
#define WDT_WDSC_EMUFREE (1 << 5) /* Bit 5: Watchdog DEBUG Disable */ #define WDT_DSC_EMU_FREE (1 << 5) /* Bit 5: Watchdog DEBUG Disable */
/* Watchdog Status Register */ /* Watchdog Status Register */
#define WDT_WDST_RESETDONE (1 << 0) /* Bit 0: Watchdog Reset Completed */ #define WDT_DST_RST_DONE (1 << 0) /* Bit 0: Watchdog Reset Completed */
/* Watchdog Interrupt Registers */ /* Watchdog Interrupt Registers */
@@ -108,26 +108,26 @@
/* Watchdog Control Register */ /* Watchdog Control Register */
#define WDT_WCLR_PTV_SHIFT (2) /* Bits 2-4: Prescaler Value */ #define WDT_CLR_PTV_SHIFT (2) /* Bits 2-4: Prescaler Value */
#define WDT_WCLR_PTV_MASK (7 << WDT_WCLR_PTV_SHIFT) #define WDT_CLR_PTV_MASK (7 << WDT_CLR_PTV_SHIFT)
# define WDT_WCLR_PTV(n) ((uint32_t)(n) << WDT_WCLR_PTV_SHIFT) # define WDT_CLR_PTV(n) ((uint32_t)(n) << WDT_CLR_PTV_SHIFT)
#define WDT_WCLR_PRE_ENABLE (1 << 5) /* Bit 5: Prescaler Enabled */ #define WDT_CLR_PRE_ENABLE (1 << 5) /* Bit 5: Prescaler Enabled */
/* Watchdog Write Posting Bits Register */ /* Watchdog Write Posting Bits Register */
#define WDT_WWPS_W_PEND_WCLR (1 << 0) /* Bit 0: Write Pending for Register WCLR */ #define WDT_WPS_W_PEND_WCLR (1 << 0) /* Bit 0: Write Pending for Register WCLR */
#define WDT_WWPS_W_PEND_WCRR (1 << 1) /* Bit 1: Write pending for register WCRR */ #define WDT_WPS_W_PEND_WCRR (1 << 1) /* Bit 1: Write pending for register WCRR */
#define WDT_WWPS_W_PEND_WLDR (1 << 2) /* Bit 2: Write pending for register WLDR */ #define WDT_WPS_W_PEND_WLDR (1 << 2) /* Bit 2: Write pending for register WLDR */
#define WDT_WWPS_W_PEND_WTGR (1 << 3) /* Bit 3: Write pending for register WTGR */ #define WDT_WPS_W_PEND_WTGR (1 << 3) /* Bit 3: Write pending for register WTGR */
#define WDT_WWPS_W_PEND_WSPR (1 << 4) /* Bit 4: Write pending for register WSPR */ #define WDT_WPS_W_PEND_WSPR (1 << 4) /* Bit 4: Write pending for register WSPR */
#define WDT_WWPS_W_PEND_WDLY (1 << 5) /* Bit 5: Write pending for register WDLY */ #define WDT_WPS_W_PEND_WDLY (1 << 5) /* Bit 5: Write pending for register WDLY */
/* Watchdog Start/Stop Register */ /* Watchdog Start/Stop Register */
#define WDT_WSPR_START_FEED_A (0x0000bbbb) #define WDT_SPR_START_FEED_A (0x0000bbbb)
#define WDT_WSPR_START_FEED_B (0x00004444) #define WDT_SPR_START_FEED_B (0x00004444)
#define WDT_WSPR_STOP_FEED_A (0x0000aaaa) #define WDT_SPR_STOP_FEED_A (0x0000aaaa)
#define WDT_WSPR_STOP_FEED_B (0x00005555) #define WDT_SPR_STOP_FEED_B (0x00005555)
#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_WDOG_H */ #endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_WDOG_H */