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arch/z80/src/ez80/ez80_i2c.c: Cosmetic changes from code review. Also makes I2C and SPI configurable options.

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This commit is contained in:
Gregory Nutt
2019-06-04 06:49:45 -06:00
parent 6fbfd00396
commit 4a7f0166cf
3 changed files with 141 additions and 118 deletions
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arch/z80/src/ez80/Kconfig
+8
View File
@@ -22,6 +22,14 @@ config EZ80_UART2
select UART2_SERIALDRIVER select UART2_SERIALDRIVER
default n default n
config EZ80_I2C
bool "I2C"
default n
config EZ80_SPI
bool "SPI"
default n
config EZ80_EMAC config EZ80_EMAC
bool "Ethernet MAC" bool "Ethernet MAC"
default n default n
arch/z80/src/ez80/Make.defs
+8 -4
View File
@@ -53,14 +53,18 @@ endif
CHIP_SSRCS = CHIP_SSRCS =
CHIP_CSRCS = ez80_clock.c ez80_initialstate.c ez80_irq.c ez80_copystate.c CHIP_CSRCS = ez80_clock.c ez80_initialstate.c ez80_irq.c ez80_copystate.c
CHIP_CSRCS += ez80_schedulesigaction.c ez80_sigdeliver.c ez80_lowuart.c CHIP_CSRCS += ez80_schedulesigaction.c ez80_sigdeliver.c ez80_lowuart.c
CHIP_CSRCS += ez80_serial.c ez80_spi.c ez80_i2c.c ez80_registerdump.c CHIP_CSRCS += ez80_serial.c ez80_registerdump.c
ifneq ($(CONFIG_SCHED_TICKLESS),y) ifneq ($(CONFIG_EZ80_I2C),y)
CHIP_CSRCS += ez80_timerisr.c CHIP_CSRCS += ez80_i2c.c
endif
ifneq ($(CONFIG_EZ80_SPI),y)
CHIP_CSRCS += ez80_spi.c
endif endif
ifeq ($(CONFIG_ARCH_CHIP_EZ80F91),y) ifeq ($(CONFIG_ARCH_CHIP_EZ80F91),y)
ifeq ($(CONFIG_EZ80_EMAC),y) ifeq ($(CONFIG_EZ80_EMAC),y)
CHIP_CSRCS += ez80_emac.c CHIP_CSRCS += ez80_emac.c
endif endif
endif endif
arch/z80/src/ez80/ez80_i2c.c
+125 -114
View File
@@ -208,65 +208,65 @@ static uint16_t ez80_i2c_getccr(uint32_t fscl)
* fscl = sysclock / 10 / (M + 1) / 2**N * fscl = sysclock / 10 / (M + 1) / 2**N
* = fsamp / 10 / (M + 1) * = fsamp / 10 / (M + 1)
* *
* The fsmp must be >= 10 * fscl. The best solution is the smallest value of * The fsmp must be >= 10 * fscl. The best solution is the smallest value
* N so that the sampling rate is the highest subject to: * of N so that the sampling rate is the highest subject to:
* *
* The minimum value of the fsamp is given by: * The minimum value of the fsamp is given by:
*/ */
fsamp = 10 * fscl; fsamp = 10 * fscl;
/* Now, serarch for the smallest value of N that results in the actual /* Now, serarch for the smallest value of N that results in the actual
* fsamp >= the ideal fsamp. Fortunately, we only have to check at most * fsamp >= the ideal fsamp. Fortunately, we only have to check at most
* eight values. * eight values.
*/ */
if (fsamp >= EZ80_SYS_CLK_FREQ) if (fsamp >= EZ80_SYS_CLK_FREQ)
{ {
ftmp = EZ80_SYS_CLK_FREQ / 10; ftmp = EZ80_SYS_CLK_FREQ / 10;
n = 0; n = 0;
} }
else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 1)) else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 1))
{ {
ftmp = (EZ80_SYS_CLK_FREQ >> 1) / 10; ftmp = (EZ80_SYS_CLK_FREQ >> 1) / 10;
n = 1; n = 1;
} }
else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 2)) else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 2))
{ {
ftmp = (EZ80_SYS_CLK_FREQ >> 2) / 10; ftmp = (EZ80_SYS_CLK_FREQ >> 2) / 10;
n = 2; n = 2;
} }
else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 3)) else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 3))
{ {
ftmp = (EZ80_SYS_CLK_FREQ >> 3) / 10; ftmp = (EZ80_SYS_CLK_FREQ >> 3) / 10;
n = 3; n = 3;
} }
else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 4)) else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 4))
{ {
ftmp = (EZ80_SYS_CLK_FREQ >> 4) / 10; ftmp = (EZ80_SYS_CLK_FREQ >> 4) / 10;
n = 4; n = 4;
} }
else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 5)) else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 5))
{ {
ftmp = (EZ80_SYS_CLK_FREQ >> 5) / 10; ftmp = (EZ80_SYS_CLK_FREQ >> 5) / 10;
n = 5; n = 5;
} }
else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 6)) else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 6))
{ {
ftmp = (EZ80_SYS_CLK_FREQ >> 6) / 10; ftmp = (EZ80_SYS_CLK_FREQ >> 6) / 10;
n = 6; n = 6;
} }
else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 7)) else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 7))
{ {
ftmp = (EZ80_SYS_CLK_FREQ >> 7) / 10; ftmp = (EZ80_SYS_CLK_FREQ >> 7) / 10;
n = 7; n = 7;
} }
else else
{ {
ftmp = (EZ80_SYS_CLK_FREQ >> 7) / 10; ftmp = (EZ80_SYS_CLK_FREQ >> 7) / 10;
fscl = ftmp; fscl = ftmp;
n = 7; n = 7;
} }
/* Finally, get M: /* Finally, get M:
* *
@@ -291,9 +291,10 @@ static uint16_t ez80_i2c_getccr(uint32_t fscl)
* Name: ez80_i2c_waitiflg * Name: ez80_i2c_waitiflg
* *
* Description: * Description:
* In polled mode, we have to spin until the IFLG bit in the xxx register * In polled mode, we have to spin until the IFLG bit in the I2C_CTL
* goes to 1, signalling that the last send or receive is complete. This * register goes to 1, signaling that the last send or receive is
* could be used to generate an interrupt for a non-polled driver. * complete. This could be used to generate an interrupt for a non-
* polled driver.
* *
* Input Parameters: * Input Parameters:
* priv - Device-specific state data * priv - Device-specific state data
@@ -383,7 +384,7 @@ static void ez80_i2c_stop(void)
* Send the 8- or 11-bit address for either a read or a write transaction. * Send the 8- or 11-bit address for either a read or a write transaction.
* *
* Input Parameters: * Input Parameters:
* priv - Device-specific state data * priv - Device-specific state data
* readbit - 0 or I2C_READBIT * readbit - 0 or I2C_READBIT
* *
* Returned Value: * Returned Value:
@@ -410,7 +411,7 @@ static int ez80_i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit)
{ {
/* This error should never occur */ /* This error should never occur */
_err("ERROR: Bad START status: %02x\n", sr); i2cerr("ERROR: Bad START status: %02x\n", sr);
ez80_i2c_clriflg(); ez80_i2c_clriflg();
return -EIO; return -EIO;
} }
@@ -432,7 +433,7 @@ static int ez80_i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit)
sr = ez80_i2c_waitiflg(); sr = ez80_i2c_waitiflg();
if (sr != I2C_SR_MADDRWRACK && sr != I2C_SR_MADDRWR) if (sr != I2C_SR_MADDRWRACK && sr != I2C_SR_MADDRWR)
{ {
_err("ERROR: Bad ADDR8 status: %02x\n", sr); i2cerr("ERROR: Bad ADDR8 status: %02x\n", sr);
goto failure; goto failure;
} }
} }
@@ -451,7 +452,7 @@ static int ez80_i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit)
sr = ez80_i2c_waitiflg(); sr = ez80_i2c_waitiflg();
if (sr != I2C_SR_MADDRWRACK && sr != I2C_SR_MADDRWR) if (sr != I2C_SR_MADDRWRACK && sr != I2C_SR_MADDRWR)
{ {
_err("ERROR: Bad ADDR10H status: %02x\n", sr); i2cerr("ERROR: Bad ADDR10H status: %02x\n", sr);
goto failure; goto failure;
} }
@@ -465,7 +466,7 @@ static int ez80_i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit)
sr = ez80_i2c_waitiflg(); sr = ez80_i2c_waitiflg();
if (sr != I2C_SR_MADDR2WRACK && sr != I2C_SR_MADDR2WR) if (sr != I2C_SR_MADDR2WRACK && sr != I2C_SR_MADDR2WR)
{ {
_err("ERROR: Bad ADDR10L status: %02x\n", sr); i2cerr("ERROR: Bad ADDR10L status: %02x\n", sr);
goto failure; goto failure;
} }
} }
@@ -480,17 +481,18 @@ failure:
{ {
case I2C_SR_ARBLOST1: /* Arbitration lost in address or data byte */ case I2C_SR_ARBLOST1: /* Arbitration lost in address or data byte */
case I2C_SR_ARBLOST2: /* Arbitration lost in address as master, slave case I2C_SR_ARBLOST2: /* Arbitration lost in address as master, slave
* address and Write bit received, ACK transmitted */ * address and Write bit received, ACK
* transmitted */
case I2C_SR_ARBLOST3: /* Arbitration lost in address as master, General case I2C_SR_ARBLOST3: /* Arbitration lost in address as master, General
* Call address received, ACK transmitted */ * Call address received, ACK transmitted */
case I2C_SR_ARBLOST4: /* Arbitration lost in address as master, slave case I2C_SR_ARBLOST4: /* Arbitration lost in address as master, slave
* address and Read bit received, ACK transmitted */ * address and Read bit received, ACK transmitted */
_err("ERROR: Arbitration lost: %02x\n", sr); i2cerr("ERROR: Arbitration lost: %02x\n", sr);
ez80_i2c_clriflg(); ez80_i2c_clriflg();
return -EAGAIN; return -EAGAIN;
default: default:
_err("ERROR: Unexpected status: %02x\n", sr); i2cerr("ERROR: Unexpected status: %02x\n", sr);
ez80_i2c_clriflg(); ez80_i2c_clriflg();
return -EIO; return -EIO;
} }
@@ -511,7 +513,8 @@ failure:
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
* buffer - A pointer to a buffer of data to receive the data from the device * buffer - A pointer to a buffer of data to receive the data from the
* device
* buflen - The requested number of bytes to be read * buflen - The requested number of bytes to be read
* flags - Determines is a START and/or STOP indication is needed. * flags - Determines is a START and/or STOP indication is needed.
* *
@@ -598,61 +601,64 @@ static int ez80_i2c_read_transfer(FAR struct ez80_i2cdev_s *priv,
/* Data byte received in MASTER mode, ACK transmitted */ /* Data byte received in MASTER mode, ACK transmitted */
if (regval == I2C_SR_MDATARDACK) if (regval == I2C_SR_MDATARDACK)
{ {
/* Since we just ACKed the incoming byte, it must NOT be the last */ /* Since we just ACKed the incoming byte, it must NOT be the
* last
*/
DEBUGASSERT(count > 1); DEBUGASSERT(count > 1);
/* Receive the data and clear the IFLGS */ /* Receive the data and clear the IFLGS */
*ptr++ = inp(EZ80_I2C_DR); *ptr++ = inp(EZ80_I2C_DR);
ez80_i2c_clriflg(); ez80_i2c_clriflg();
} }
/* Data byte received in MASTER mode, NACK transmitted */ /* Data byte received in MASTER mode, NACK transmitted */
else if (regval == I2C_SR_MDATARDNAK) else if (regval == I2C_SR_MDATARDNAK)
{ {
/* Since we just NACKed the incoming byte, it must be the last */ /* Since we just NACKed the incoming byte, it must be the last */
DEBUGASSERT(count <= 1); DEBUGASSERT(count <= 1);
if ((flags & EZ80_NOSTOP) == 0) if ((flags & EZ80_NOSTOP) == 0)
{ {
/* When all bytes are received and the NACK has been sent, /* When all bytes are received and the NACK has been sent,
* then the microcontroller must write 1 to the STP bit in * then the microcontroller must write 1 to the STP bit in
* the I2C_CTL register. The I2C then transmits a STOP * the I2C_CTL register. The I2C then transmits a STOP
* condition, clears the STP bit and returns to an idle state. * condition, clears the STP bit and returns to an idle
* state.
*/ */
ez80_i2c_stop(); ez80_i2c_stop();
} }
ez80_i2c_clriflg(); ez80_i2c_clriflg();
return OK; return OK;
} }
/* Arbitration lost in address or data byte */ /* Arbitration lost in address or data byte */
else if (regval == I2C_SR_ARBLOST1) else if (regval == I2C_SR_ARBLOST1)
{ {
/* Clear the IFLG and break out of the inner loop. /* Clear the IFLG and break out of the inner loop.
* this will cause the whole transfer to start over * this will cause the whole transfer to start over
*/ */
_err("ERROR: Arbitration lost: %02x\n", regval); i2cerr("ERROR: Arbitration lost: %02x\n", regval);
ez80_i2c_clriflg(); ez80_i2c_clriflg();
break; break;
} }
/* Unexpected status response */ /* Unexpected status response */
else else
{ {
_err("ERROR: Unexpected status: %02x\n", regval); i2cerr("ERROR: Unexpected status: %02x\n", regval);
ez80_i2c_clriflg(); ez80_i2c_clriflg();
return-EIO; return -EIO;
} }
} }
} }
@@ -669,8 +675,9 @@ static int ez80_i2c_read_transfer(FAR struct ez80_i2cdev_s *priv,
* and pend until this write completes. Required. * and pend until this write completes. Required.
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
* buffer - A pointer to the read-only buffer of data to be written to device * buffer - A pointer to the read-only buffer of data to be written to
* device
* buflen - The number of bytes to send from the buffer * buflen - The number of bytes to send from the buffer
* flags - Determines is a START and/or STOP indication is needed. * flags - Determines is a START and/or STOP indication is needed.
* *
@@ -725,8 +732,8 @@ static int ez80_i2c_write_transfer(FAR struct ez80_i2cdev_s *priv,
ptr = buffer; ptr = buffer;
for (count = buflen; count; count--) for (count = buflen; count; count--)
{ {
/* Load the I2C_DR with next data byte and clear the IFLG. Clearing /* Load the I2C_DR with next data byte and clear the IFLG.
* the IFLAG will cause the data to be transferred. * Clearing the IFLAG will cause the data to be transferred.
*/ */
outp(EZ80_I2C_DR, *ptr++); outp(EZ80_I2C_DR, *ptr++);
@@ -737,15 +744,15 @@ static int ez80_i2c_write_transfer(FAR struct ez80_i2cdev_s *priv,
sr = ez80_i2c_waitiflg(); sr = ez80_i2c_waitiflg();
if (sr != I2C_SR_MDATAWRACK && sr != I2C_SR_MDATAWR) if (sr != I2C_SR_MDATAWRACK && sr != I2C_SR_MDATAWR)
{ {
_err("ERROR: Bad DATA status: %02x\n", sr); i2cerr("ERROR: Bad DATA status: %02x\n", sr);
ez80_i2c_clriflg(); ez80_i2c_clriflg();
if (sr == I2C_SR_ARBLOST1) if (sr == I2C_SR_ARBLOST1)
{ {
/* Arbitration lost, break out of the inner loop and /* Arbitration lost, break out of the inner loop and
* try sending the message again * try sending the message again
*/ */
break; break;
} }
/* Otherwise, it is fatal (shouldn't happen) */ /* Otherwise, it is fatal (shouldn't happen) */
@@ -879,7 +886,8 @@ static int ez80_i2c_transfer(FAR struct i2c_master_s *dev,
next = &msgs[i + 1]; next = &msgs[i + 1];
if ((msg->flags & I2C_M_NOSTART) != 0 && if ((msg->flags & I2C_M_NOSTART) != 0 &&
(msg->flags & (I2C_M_READ | I2C_M_TEN)) == (next->flags & (I2C_M_READ | I2C_M_TEN)) && (msg->flags & (I2C_M_READ | I2C_M_TEN)) ==
(next->flags & (I2C_M_READ | I2C_M_TEN)) &&
msg->addr == next->addr) msg->addr == next->addr)
{ {
nostop = true; nostop = true;
@@ -891,11 +899,13 @@ static int ez80_i2c_transfer(FAR struct i2c_master_s *dev,
flags |= (nostop) ? EZ80_NOSTOP : 0; flags |= (nostop) ? EZ80_NOSTOP : 0;
if ((msg->flags & I2C_M_READ) != 0) if ((msg->flags & I2C_M_READ) != 0)
{ {
ret = ez80_i2c_read_transfer(priv, msg->buffer, msg->length, flags); ret = ez80_i2c_read_transfer(priv, msg->buffer, msg->length,
flags);
} }
else else
{ {
ret = ez80_i2c_write_transfer(priv, msg->buffer, msg->length, flags); ret = ez80_i2c_write_transfer(priv, msg->buffer, msg->length,
flags);
} }
/* Check for I2C transfer errors */ /* Check for I2C transfer errors */
@@ -930,10 +940,10 @@ static int ez80_i2c_transfer(FAR struct i2c_master_s *dev,
* different frequency and slave address. * different frequency and slave address.
* *
* Input Parameters: * Input Parameters:
* Port number (for hardware that has mutiple I2C interfaces) * Port number (for hardware that has multiple I2C interfaces)
* *
* Returned Value: * Returned Value:
* Valid I2C device structre reference on succcess; a NULL on failure * Valid I2C device structure reference on success; a NULL on failure
* *
****************************************************************************/ ****************************************************************************/
@@ -947,7 +957,7 @@ FAR struct i2c_master_s *ez80_i2cbus_initialize(int port)
{ {
/* Set up some initial BRG value */ /* Set up some initial BRG value */
ccr = ez80_i2c_getccr(100*1000); ccr = ez80_i2c_getccr(100 * 1000);
ez80_i2c_setccr(ccr); ez80_i2c_setccr(ccr);
/* No GPIO setup is required -- I2C pints, SCL/SDA are not multiplexed */ /* No GPIO setup is required -- I2C pints, SCL/SDA are not multiplexed */
@@ -965,8 +975,9 @@ FAR struct i2c_master_s *ez80_i2cbus_initialize(int port)
/* Now, allocate an I2C instance for this caller */ /* Now, allocate an I2C instance for this caller */
i2c = (FAR struct ez80_i2cdev_s *)kmm_zalloc(sizeof(FAR struct ez80_i2cdev_s)); i2c = (FAR struct ez80_i2cdev_s *)
if (i2c) kmm_zalloc(sizeof(FAR struct ez80_i2cdev_s));
if (i2c != NULL)
{ {
/* Initialize the allocated instance */ /* Initialize the allocated instance */