diff --git a/arch/arm/include/stm32/stm32f10xxx_irq.h b/arch/arm/include/stm32/stm32f10xxx_irq.h index 3c62e1e2ea3..29f07b0fd88 100644 --- a/arch/arm/include/stm32/stm32f10xxx_irq.h +++ b/arch/arm/include/stm32/stm32f10xxx_irq.h @@ -120,7 +120,7 @@ # define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ # define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ # define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */ -# define STM32_IRQ_UART5 (69) /* 53: USART5 global interrupt */ +# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ # define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ # define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ # define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index c4e722f4ba8..ee4da50e45a 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -2160,63 +2160,47 @@ config STM32_TSC config STM32_USART1 bool "USART1" default n - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS select STM32_USART config STM32_USART2 bool "USART2" default n - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS select STM32_USART config STM32_USART3 bool "USART3" default n depends on STM32_HAVE_USART3 - select ARCH_HAVE_SERIAL_TERMIOS - select USART3_SERIALDRIVER select STM32_USART config STM32_UART4 bool "UART4" default n depends on STM32_HAVE_UART4 - select ARCH_HAVE_SERIAL_TERMIOS - select UART4_SERIALDRIVER select STM32_USART config STM32_UART5 bool "UART5" default n depends on STM32_HAVE_UART5 - select ARCH_HAVE_SERIAL_TERMIOS - select UART5_SERIALDRIVER select STM32_USART config STM32_USART6 bool "USART6" default n depends on STM32_HAVE_USART6 - select ARCH_HAVE_SERIAL_TERMIOS - select USART6_SERIALDRIVER select STM32_USART config STM32_UART7 bool "UART7" default n depends on STM32_HAVE_UART7 - select ARCH_HAVE_SERIAL_TERMIOS - select UART7_SERIALDRIVER select STM32_USART config STM32_UART8 bool "UART8" default n depends on STM32_HAVE_UART8 - select ARCH_HAVE_SERIAL_TERMIOS - select UART8_SERIALDRIVER select STM32_USART config STM32_USB @@ -5414,13 +5398,37 @@ endmenu config STM32_USART bool +config STM32_SERIALDRIVER + bool + +config STM32_1WIREDRIVER + bool + menu "U[S]ART Configuration" depends on STM32_USART +choice + prompt "USART1 Driver Configuration" + default STM32_USART1_SERIALDRIVER + depends on STM32_USART1 + +config STM32_USART1_SERIALDRIVER + bool "Standard serial driver" + select USART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART1 Driver Configuration + +if STM32_USART1_SERIALDRIVER + config USART1_RS485 bool "RS-485 on USART1" default n - depends on STM32_USART1 ---help--- Enable RS-485 interface on USART1. Your board config will have to provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be @@ -5438,14 +5446,34 @@ config USART1_RS485_DIR_POLARITY config USART1_RXDMA bool "USART1 Rx DMA" default n - depends on STM32_USART1 && (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) + depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors +endif # STM32_USART1_SERIALDRIVER + +choice + prompt "USART2 Driver Configuration" + default STM32_USART2_SERIALDRIVER + depends on STM32_USART2 + +config STM32_USART2_SERIALDRIVER + bool "Standard serial driver" + select USART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART2_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART2 Driver Configuration + +if STM32_USART2_SERIALDRIVER + config USART2_RS485 bool "RS-485 on USART2" default n - depends on STM32_USART2 ---help--- Enable RS-485 interface on USART2. Your board config will have to provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be @@ -5463,14 +5491,34 @@ config USART2_RS485_DIR_POLARITY config USART2_RXDMA bool "USART2 Rx DMA" default n - depends on STM32_USART2 && STM32_DMA1 + depends on STM32_DMA1 ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors +endif # STM32_USART2_SERIALDRIVER + +choice + prompt "USART3 Driver Configuration" + default STM32_USART3_SERIALDRIVER + depends on STM32_USART3 + +config STM32_USART3_SERIALDRIVER + bool "Standard serial driver" + select USART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART3_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART3 Driver Configuration + +if STM32_USART3_SERIALDRIVER + config USART3_RS485 bool "RS-485 on USART3" default n - depends on STM32_USART3 ---help--- Enable RS-485 interface on USART3. Your board config will have to provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be @@ -5488,14 +5536,34 @@ config USART3_RS485_DIR_POLARITY config USART3_RXDMA bool "USART3 Rx DMA" default n - depends on STM32_USART3 && STM32_DMA1 + depends on STM32_DMA1 ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors +endif # STM32_USART3_SERIALDRIVER + +choice + prompt "UART4 Driver Configuration" + default STM32_UART4_SERIALDRIVER + depends on STM32_UART4 + +config STM32_UART4_SERIALDRIVER + bool "Standard serial driver" + select UART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART1 Driver Configuration + +if STM32_UART4_SERIALDRIVER + config UART4_RS485 bool "RS-485 on UART4" default n - depends on STM32_UART4 ---help--- Enable RS-485 interface on UART4. Your board config will have to provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be @@ -5513,14 +5581,34 @@ config UART4_RS485_DIR_POLARITY config UART4_RXDMA bool "UART4 Rx DMA" default n - depends on STM32_UART4 && STM32_DMA1 + depends on STM32_DMA1 ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors +endif # STM32_UART4_SERIALDRIVER + +choice + prompt "UART5 Driver Configuration" + default STM32_UART5_SERIALDRIVER + depends on STM32_UART5 + +config STM32_UART5_SERIALDRIVER + bool "Standard serial driver" + select UART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART5 Driver Configuration + +if STM32_UART5_SERIALDRIVER + config UART5_RS485 bool "RS-485 on UART5" default n - depends on STM32_UART5 ---help--- Enable RS-485 interface on UART5. Your board config will have to provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be @@ -5538,14 +5626,34 @@ config UART5_RS485_DIR_POLARITY config UART5_RXDMA bool "UART5 Rx DMA" default n - depends on STM32_UART5 && STM32_DMA1 + depends on STM32_DMA1 ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors +endif # STM32_UART5_SERIALDRIVER + +choice + prompt "USART6 Driver Configuration" + default STM32_USART6_SERIALDRIVER + depends on STM32_USART6 + +config STM32_USART6_SERIALDRIVER + bool "Standard serial driver" + select USART6_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART6_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART6 Driver Configuration + +if STM32_USART6_SERIALDRIVER + config USART6_RS485 bool "RS-485 on USART6" default n - depends on STM32_USART6 ---help--- Enable RS-485 interface on USART6. Your board config will have to provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be @@ -5563,14 +5671,34 @@ config USART6_RS485_DIR_POLARITY config USART6_RXDMA bool "USART6 Rx DMA" default n - depends on STM32_USART6 && STM32_DMA2 + depends on STM32_DMA2 ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors +endif # STM32_USART6_SERIALDRIVER + +choice + prompt "UART7 Driver Configuration" + default STM32_UART7_SERIALDRIVER + depends on STM32_UART7 + +config STM32_UART7_SERIALDRIVER + bool "Standard serial driver" + select UART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART7 Driver Configuration + +if STM32_UART7_SERIALDRIVER + config UART7_RS485 bool "RS-485 on UART7" default n - depends on STM32_UART7 ---help--- Enable RS-485 interface on UART7. Your board config will have to provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be @@ -5588,14 +5716,34 @@ config UART7_RS485_DIR_POLARITY config UART7_RXDMA bool "UART7 Rx DMA" default n - depends on STM32_UART7 && STM32_DMA2 + depends on STM32_DMA2 ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors +endif # STM32_UART7_SERIALDRIVER + +choice + prompt "UART8 Driver Configuration" + default STM32_UART8_SERIALDRIVER + depends on STM32_UART7 + +config STM32_UART8_SERIALDRIVER + bool "Standard serial driver" + select UART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART8 Driver Configuration + +if STM32_UART8_SERIALDRIVER + config UART8_RS485 bool "RS-485 on UART8" default n - depends on STM32_UART8 ---help--- Enable RS-485 interface on UART8. Your board config will have to provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be @@ -5613,10 +5761,14 @@ config UART8_RS485_DIR_POLARITY config UART8_RXDMA bool "UART8 Rx DMA" default n - depends on STM32_UART8 && STM32_DMA2 + depends on STM32_DMA2 ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors +endif # STM32_UART8_SERIALDRIVER + +if STM32_SERIALDRIVER + config SERIAL_DISABLE_REORDERING bool "Disable reordering of ttySx devices." depends on STM32_USART1 || STM32_USART2 || STM32_USART3 || STM32_UART4 || STM32_UART5 || STM32_USART6 || STM32_UART7 || STM32_UART8 @@ -5661,8 +5813,6 @@ config STM32_SERIALBRK_BSDCOMPAT on because the SW starts the break and then the HW automatically clears the break. This makes it is difficult to sent a long break. -endmenu # U[S]ART Configuration - config STM32_USART_SINGLEWIRE bool "Single Wire Support" default n @@ -5671,6 +5821,9 @@ config STM32_USART_SINGLEWIRE Enable single wire UART support. The option enables support for the TIOCSSINGLEWIRE ioctl in the STM32 serial driver. +endif # STM32_SERIALDRIVER +endmenu # U[S]ART Configuration + menu "SPI Configuration" depends on STM32_SPI diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 64034976b5a..3d225f31ef9 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -211,6 +211,10 @@ ifeq ($(CONFIG_DAC),y) CHIP_CSRCS += stm32_dac.c endif +ifeq ($(CONFIG_STM32_1WIREDRIVER),y) +CHIP_CSRCS += stm32_1wire.c +endif + ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h b/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h index 24822c37d3e..0af150638a0 100644 --- a/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h +++ b/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h @@ -110,7 +110,7 @@ UNUSED(STM32_IRQ_RESERVED6) /* Vector 16+49: Reserved 6 */ VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */ VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* Vector 16+51: SPI3 global interrupt */ VECTOR(stm32_uart4, STM32_IRQ_UART4) /* Vector 16+52: USART2 global interrupt */ -VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: USART5 global interrupt */ +VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: UART5 global interrupt */ VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt */ VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */ VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* Vector 16+56: DMA2 Channel 1 global interrupt */ diff --git a/arch/arm/src/stm32/stm32_1wire.c b/arch/arm/src/stm32/stm32_1wire.c index d81feb7999e..018ff32c6f1 100644 --- a/arch/arm/src/stm32/stm32_1wire.c +++ b/arch/arm/src/stm32/stm32_1wire.c @@ -1,1333 +1,1338 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_1wire.c - * - * Copyright (C) 2016 Aleksandr Vyhovanec. All rights reserved. - * Author: Aleksandr Vyhovanec - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* Links: - * https://www.maximintegrated.com/en/app-notes/index.mvp/id/214 - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "up_arch.h" - -#include "stm32_rcc.h" -#include "stm32_1wire.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define BUS_TIMEOUT 5 /* tv_sec */ - -#define RESET_BAUD 9600 -#define RESET_TX 0xF0 -#define TIMESLOT_BAUD 115200 -#define READ_TX 0xFF -#define READ_RX1 0xFF -#define WRITE_TX0 0x00 -#define WRITE_TX1 0xFF - -#define PIN_OPENDRAIN(GPIO) ((GPIO) | GPIO_OPENDRAIN) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* 1-Wire bus task */ - -enum stm32_1wire_msg_e -{ - ONEWIRETASK_NONE = 0, - ONEWIRETASK_RESET, - ONEWIRETASK_WRITE, - ONEWIRETASK_READ -}; - -struct stm32_1wire_msg_s -{ - enum stm32_1wire_msg_e task; /* Task */ - uint8_t *buffer; /* Task buffer */ - int buflen; /* Buffer length */ -}; - -/* 1-Wire device hardware configuration */ - -struct stm32_1wire_config_s -{ - const uint32_t usartbase; /* Base address of USART registers */ - const uint32_t apbclock; /* PCLK 1 or 2 frequency */ - const uint32_t data_pin; /* GPIO configuration for DATA */ - const uint8_t irq; /* IRQ associated with this USART */ - int (*const vector)(int irq, void *context); /* Interrupt handler */ -}; - -/* 1-Wire device Private Data */ - -struct stm32_1wire_priv_s -{ - const struct stm32_1wire_config_s *config; /* Port configuration */ - volatile int refs; /* Referernce count */ - sem_t sem_excl; /* Mutual exclusion semaphore */ - sem_t sem_isr; /* Interrupt wait semaphore */ - int baud; /* Baud rate */ - const struct stm32_1wire_msg_s *msgs; /* Messages data */ - uint8_t *byte; /* Current byte */ - uint8_t bit; /* Current bit */ - volatile int result; /* Exchange result */ -}; - -/* 1-Wire device, Instance */ - -struct stm32_1wire_inst_s -{ - const struct onewire_ops_s *ops; /* Standard 1-Wire operations */ - struct stm32_1wire_priv_s *priv; /* Common driver private data structure */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static inline uint32_t stm32_1wire_in(struct stm32_1wire_priv_s *priv, int offset); -static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, int offset, uint32_t value); -static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv); -static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch); -static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv); -static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, bool on); -static int stm32_1wire_init(FAR struct stm32_1wire_priv_s *priv); -static int stm32_1wire_deinit(FAR struct stm32_1wire_priv_s *priv); -static inline void stm32_1wire_sem_init(FAR struct stm32_1wire_priv_s *priv); -static inline void stm32_1wire_sem_destroy(FAR struct stm32_1wire_priv_s *priv); -static inline void stm32_1wire_sem_wait(FAR struct stm32_1wire_priv_s *priv); -static inline void stm32_1wire_sem_post(FAR struct stm32_1wire_priv_s *priv); -static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, - FAR const struct stm32_1wire_msg_s *msgs, int count); -static int stm32_1wire_isr(struct stm32_1wire_priv_s *priv); - -#ifdef CONFIG_STM32_1WIRE1 -static int up_interrupt_1wire1(int irq, void *context); -#endif -#ifdef CONFIG_STM32_1WIRE2 -static int up_interrupt_1wire2(int irq, void *context); -#endif -#ifdef CONFIG_STM32_1WIRE3 -static int up_interrupt_1wire3(int irq, void *context); -#endif -#ifdef CONFIG_STM32_1WIRE4 -static int up_interrupt_1wire4(int irq, void *context); -#endif -#ifdef CONFIG_STM32_1WIRE5 -static int up_interrupt_1wire5(int irq, void *context); -#endif -#ifdef CONFIG_STM32_1WIRE6 -static int up_interrupt_1wire6(int irq, void *context); -#endif -#ifdef CONFIG_STM32_1WIRE7 -static int up_interrupt_1wire7(int irq, void *context); -#endif -#ifdef CONFIG_STM32_1WIRE8 -static int up_interrupt_1wire8(int irq, void *context); -#endif - -static int stm32_1wire_reset(FAR struct onewire_dev_s *dev); -static int stm32_1wire_write(FAR struct onewire_dev_s *dev, - const uint8_t *buffer, int buflen); -static int stm32_1wire_read(FAR struct onewire_dev_s *dev, uint8_t *buffer, - int buflen); -static int stm32_1wire_exchange(FAR struct onewire_dev_s *dev, bool reset, - const uint8_t *txbuffer, int txbuflen, - uint8_t *rxbuffer, int rxbuflen); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* 1-Wire device structures */ - -#ifdef CONFIG_STM32_1WIRE1 - -static const struct stm32_1wire_config_s stm32_1wire1_config = -{ - .usartbase = STM32_USART1_BASE, - .apbclock = STM32_PCLK2_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART1_TX), - .irq = STM32_IRQ_USART1, - .vector = up_interrupt_1wire1, -}; - -static struct stm32_1wire_priv_s stm32_1wire1_priv = -{ - .config = &stm32_1wire1_config, - .refs = 0, - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_1WIRE2 - -static const struct stm32_1wire_config_s stm32_1wire2_config = -{ - .usartbase = STM32_USART2_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART2_TX), - .irq = STM32_IRQ_USART2, - .vector = up_interrupt_1wire2, -}; - -static struct stm32_1wire_priv_s stm32_1wire2_priv = -{ - .config = &stm32_1wire2_config, - .refs = 0, - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_1WIRE3 - -static const struct stm32_1wire_config_s stm32_1wire3_config = -{ - .usartbase = STM32_USART3_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART3_TX), - .irq = STM32_IRQ_USART3, - .vector = up_interrupt_1wire3, -}; - -static struct stm32_1wire_priv_s stm32_1wire3_priv = -{ - .config = &stm32_1wire3_config, - .refs = 0, - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_1WIRE4 - -static const struct stm32_1wire_config_s stm32_1wire4_config = -{ - .usartbase = STM32_USART4_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART4_TX), - .irq = STM32_IRQ_USART4, - .vector = up_interrupt_1wire4, -}; - -static struct stm32_1wire_priv_s stm32_1wire4_priv = -{ - .config = &stm32_1wire4_config, - .refs = 0, - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_1WIRE5 - -static const struct stm32_1wire_config_s stm32_1wire5_config = -{ - .usartbase = STM32_USART5_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART5_TX), - .irq = STM32_IRQ_USART5, - .vector = up_interrupt_1wire5, -}; - -static struct stm32_1wire_priv_s stm32_1wire5_priv = -{ - .config = &stm32_1wire5_config, - .refs = 0, - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_1WIRE6 - -static const struct stm32_1wire_config_s stm32_1wire6_config = -{ - .usartbase = STM32_USART6_BASE, - .apbclock = STM32_PCLK2_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART6_TX), - .irq = STM32_IRQ_USART6, - .vector = up_interrupt_1wire6, -}; - -static struct stm32_1wire_priv_s stm32_1wire6_priv = -{ - .config = &stm32_1wire6_config, - .refs = 0, - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_1WIRE7 - -static const struct stm32_1wire_config_s stm32_1wire7_config = -{ - .usartbase = STM32_USART7_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART7_TX), - .irq = STM32_IRQ_USART7, - .vector = up_interrupt_1wire7, -}; - -static struct stm32_1wire_priv_s stm32_1wire7_priv = -{ - .config = &stm32_1wire7_config, - .refs = 0, - .msgs = NULL -}; - -#endif - -#ifdef CONFIG_STM32_1WIRE8 - -static const struct stm32_1wire_config_s stm32_1wire8_config = -{ - .usartbase = STM32_USART8_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART8_TX), - .irq = STM32_IRQ_USART8, - .vector = up_interrupt_1wire8, -}; - -static struct stm32_1wire_priv_s stm32_1wire8_priv = -{ - .config = &stm32_1wire8_config, - .refs = 0, - .msgs = NULL -}; - -#endif - -/* Device Structures, Instantiation */ - -static const struct onewire_ops_s stm32_1wire_ops = -{ - .reset = stm32_1wire_reset, - .write = stm32_1wire_write, - .read = stm32_1wire_read, - .exchange = stm32_1wire_exchange -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_1wire_in - ****************************************************************************/ - -static inline uint32_t stm32_1wire_in(struct stm32_1wire_priv_s *priv, - int offset) -{ - return getreg32(priv->config->usartbase + offset); -} - -/**************************************************************************** - * Name: stm32_1wire_out - ****************************************************************************/ - -static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, - int offset, uint32_t value) -{ - putreg32(value, priv->config->usartbase + offset); -} - -/**************************************************************************** - * Name: stm32_1wire_recv - * - * Description: - * This method will recv one byte on the USART - * - ****************************************************************************/ - -static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) -{ - return stm32_1wire_in(priv, STM32_USART_RDR_OFFSET) & 0xff; -} - -/**************************************************************************** - * Name: stm32_1wire_send - * - * Description: - * This method will send one byte on the USART - * - ****************************************************************************/ - -static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch) -{ - stm32_1wire_out(priv, STM32_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); -} - -/**************************************************************************** - * Name: stm32_1wire_set_baud - * - * Description: - * Set the serial line baud. - * - ****************************************************************************/ - -static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) -{ -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) - /* This first implementation is for U[S]ARTs that support oversampling - * by 8 in additional to the standard oversampling by 16. - */ - - uint32_t usartdiv8; - uint32_t cr1; - uint32_t brr; - - /* In case of oversampling by 8, the equation is: - * - * baud = 2 * fCK / usartdiv8 - * usartdiv8 = 2 * fCK / baud - */ - - usartdiv8 = ((priv->config->apbclock << 1) + (priv->baud >> 1)) / priv->baud; - - /* Baud rate for standard USART (SPI mode included): - * - * In case of oversampling by 16, the equation is: - * baud = fCK / usartdiv16 - * usartdiv16 = fCK / baud - * = 2 * usartdiv8 - */ - - /* Use oversamply by 8 only if the divisor is small. But what is small? */ - - cr1 = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - if (usartdiv8 > 100) - { - /* Use usartdiv16 */ - - brr = (usartdiv8 + 1) >> 1; - - /* Clear oversampling by 8 to enable oversampling by 16 */ - - cr1 &= ~USART_CR1_OVER8; - } - else - { - DEBUGASSERT(usartdiv8 >= 8); - - /* Perform mysterious operations on bits 0-3 */ - - brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); - - /* Set oversampling by 8 */ - - cr1 |= USART_CR1_OVER8; - } - - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); - stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); - -#else - - /* This second implementation is for U[S]ARTs that support fractional - * dividers. - */ - - uint32_t usartdiv32; - uint32_t mantissa; - uint32_t fraction; - uint32_t brr; - - /* Configure the USART Baud Rate. The baud rate for the receiver and - * transmitter (Rx and Tx) are both set to the same value as programmed - * in the Mantissa and Fraction values of USARTDIV. - * - * baud = fCK / (16 * usartdiv) - * usartdiv = fCK / (16 * baud) - * - * Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, 4, 5 - * or PCLK2 for USART1) - * - * First calculate (NOTE: all stand baud values are even so dividing by two - * does not lose precision): - * - * usartdiv32 = 32 * usartdiv = fCK / (baud/2) - */ - - usartdiv32 = priv->config->apbclock / (priv->baud >> 1); - - /* The mantissa part is then */ - - mantissa = usartdiv32 >> 5; - brr = mantissa << USART_BRR_MANT_SHIFT; - - /* The fractional remainder (with rounding) */ - - fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; - brr |= fraction << USART_BRR_FRAC_SHIFT; - stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); -#endif -} - -/**************************************************************************** - * Name: stm32_1wire_set_apb_clock - * - * Description: - * Enable or disable APB clock for the USART peripheral - * - * Input parameters: - * priv - A reference to the 1-Wire driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, - bool on) -{ - const struct stm32_1wire_config_s *config = priv->config; - uint32_t rcc_en; - uint32_t regaddr; - - /* Determine which USART to configure */ - - switch (config->usartbase) - { - default: - return; - -#ifdef CONFIG_STM32_1WIRE1 - case STM32_USART1_BASE: - rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif -#ifdef CONFIG_STM32_1WIRE2 - case STM32_USART2_BASE: - rcc_en = RCC_APB1ENR_USART2EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_1WIRE3 - case STM32_USART3_BASE: - rcc_en = RCC_APB1ENR_USART3EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_UART4 - case STM32_UART4_BASE: - rcc_en = RCC_APB1ENR_UART4EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_UART5 - case STM32_UART5_BASE: - rcc_en = RCC_APB1ENR_UART5EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_1WIRE6 - case STM32_USART6_BASE: - rcc_en = RCC_APB2ENR_USART6EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif -#ifdef CONFIG_STM32_UART7 - case STM32_UART7_BASE: - rcc_en = RCC_APB1ENR_UART7EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif -#ifdef CONFIG_STM32_UART8 - case STM32_UART8_BASE: - rcc_en = RCC_APB1ENR_UART8EN; - regaddr = STM32_RCC_APB1ENR; - break; -#endif - } - - /* Enable/disable APB 1/2 clock for USART */ - - if (on) - { - modifyreg32(regaddr, 0, rcc_en); - } - else - { - modifyreg32(regaddr, rcc_en, 0); - } -} - -/**************************************************************************** - * Name: stm32_1wire_init - * - * Description: - * Setup the 1-Wire hardware, ready for operation with defaults - * - ****************************************************************************/ - -static int stm32_1wire_init(FAR struct stm32_1wire_priv_s *priv) -{ - const struct stm32_1wire_config_s *config = priv->config; - uint32_t regval; - int ret; - - /* Enable USART APB1/2 clock */ - - stm32_1wire_set_apb_clock(priv, true); - - /* Configure CR2 */ - /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - /* Set LBDIE */ - - regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | - USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); - regval |= USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); - - /* Configure CR1 */ - /* Clear TE, REm, all interrupt enable bits, PCE, PS and M */ - /* Set RXNEIE */ - - regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS | - USART_CR1_PCE | USART_CR1_PS | USART_CR1_M); - regval |= USART_CR1_RXNEIE; - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure CR3 */ - /* Clear CTSE, RTSE, and all interrupt enable bits */ - /* Set ONEBIT, HDSEL and EIE */ - - regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - regval |= (USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); - - /* Set baud rate */ - - priv->baud = RESET_BAUD; - stm32_1wire_set_baud(priv); - - /* Enable Rx, Tx, and the USART */ - - regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure pins for USART use */ - - stm32_configgpio(config->data_pin); - - ret = irq_attach(config->irq, config->vector); - if (ret == OK) - { - up_enable_irq(config->irq); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_1wire_deinit - * - * Description: - * Shutdown the 1-Wire hardware - * - ****************************************************************************/ - -static int stm32_1wire_deinit(FAR struct stm32_1wire_priv_s *priv) -{ - const struct stm32_1wire_config_s *config = priv->config; - uint32_t regval; - - up_disable_irq(config->irq); - irq_detach(config->irq); - - /* Unconfigure GPIO pins */ - - stm32_unconfiggpio(config->data_pin); - - /* Disable RXNEIE, Rx, Tx, and the USART */ - - regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE); - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); - - /* Clear LBDIE */ - - regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); - regval &= ~USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); - - /* Clear ONEBIT, HDSEL and EIE */ - - regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); - - /* Disable USART APB1/2 clock */ - - stm32_1wire_set_apb_clock(priv, false); - - return OK; -} - -/**************************************************************************** - * Name: stm32_1wire_sem_init - * - * Description: - * Initialize semaphores - * - ****************************************************************************/ - -static inline void stm32_1wire_sem_init(FAR struct stm32_1wire_priv_s *priv) -{ - sem_init(&priv->sem_excl, 0, 1); - sem_init(&priv->sem_isr, 0, 0); -} - -/**************************************************************************** - * Name: stm32_1wire_sem_destroy - * - * Description: - * Destroy semaphores. - * - ****************************************************************************/ - -static inline void stm32_1wire_sem_destroy(FAR struct stm32_1wire_priv_s *priv) -{ - sem_destroy(&priv->sem_excl); - sem_destroy(&priv->sem_isr); -} - -/**************************************************************************** - * Name: stm32_1wire_sem_wait - * - * Description: - * Take the exclusive access, waiting as necessary - * - ****************************************************************************/ - -static inline void stm32_1wire_sem_wait(FAR struct stm32_1wire_priv_s *priv) -{ - while (sem_wait(&priv->sem_excl) != 0) - { - ASSERT(errno == EINTR); - } -} - -/**************************************************************************** - * Name: stm32_1wire_sem_post - * - * Description: - * Release the mutual exclusion semaphore - * - ****************************************************************************/ - -static inline void stm32_1wire_sem_post(FAR struct stm32_1wire_priv_s *priv) -{ - sem_post(&priv->sem_excl); -} - -/**************************************************************************** - * Name: stm32_1wire_exec - * - * Description: - * Execute 1-Wire task - ****************************************************************************/ -static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, - FAR const struct stm32_1wire_msg_s *msgs, - int count) -{ - irqstate_t irqs; - struct timespec abstime; - int ret; - - /* Lock out other clients */ - - stm32_1wire_sem_wait(priv); - - priv->result = ERROR; - - for (int indx = 0; indx < count; indx++) - { - switch (msgs[indx].task) - { - case ONEWIRETASK_NONE: - priv->result = OK; - break; - - case ONEWIRETASK_RESET: - /* Set baud rate */ - - priv->baud = RESET_BAUD; - stm32_1wire_set_baud(priv); - - /* Atomic */ - - irqs = irqsave(); - priv->msgs = &msgs[indx]; - stm32_1wire_send(priv, RESET_TX); - irqrestore(irqs); - - /* Wait */ - - clock_gettime(CLOCK_REALTIME, &abstime); - abstime.tv_sec += BUS_TIMEOUT; - sem_timedwait(&priv->sem_isr, &abstime); /* break on timeout if TX line closed to GND */ - break; - - case ONEWIRETASK_WRITE: - /* Set baud rate */ - - priv->baud = TIMESLOT_BAUD; - stm32_1wire_set_baud(priv); - - /* Atomic */ - - irqs = irqsave(); - priv->msgs = &msgs[indx]; - priv->byte = priv->msgs->buffer; - priv->bit = 0; - stm32_1wire_send(priv, (*priv->byte & (1 << priv->bit)) ? WRITE_TX1 : WRITE_TX0); - irqrestore(irqs); - - /* Wait */ - - clock_gettime(CLOCK_REALTIME, &abstime); - abstime.tv_sec += BUS_TIMEOUT; - sem_timedwait(&priv->sem_isr, &abstime); /* break on timeout if TX line closed to GND */ - break; - - case ONEWIRETASK_READ: - /* Set baud rate */ - - priv->baud = TIMESLOT_BAUD; - stm32_1wire_set_baud(priv); - - /* Atomic */ - - irqs = irqsave(); - priv->msgs = &msgs[indx]; - priv->byte = priv->msgs->buffer; - priv->bit = 0; - stm32_1wire_send(priv, READ_TX); - irqrestore(irqs); - - /* Wait */ - - clock_gettime(CLOCK_REALTIME, &abstime); - abstime.tv_sec += BUS_TIMEOUT; - sem_timedwait(&priv->sem_isr, &abstime); /* break on timeout if TX line closed to GND */ - break; - } - - if (priv->result != OK) /* break if error */ - { - break; - } - } - - /* Atomic */ - - irqs = irqsave(); - priv->msgs = NULL; - ret = priv->result; - irqrestore(irqs); - - /* Release the port for re-use by other clients */ - - stm32_1wire_sem_post(priv); - - return ret; -} - -/**************************************************************************** - * Name: stm32_1wire_isr - * - * Description: - * Common Interrupt Service Routine - ****************************************************************************/ - -static int stm32_1wire_isr(struct stm32_1wire_priv_s *priv) -{ - uint32_t sr, dr; - - /* Get the masked USART status word. */ - - sr = stm32_1wire_in(priv, STM32_USART_SR_OFFSET); - - /* Receive loop */ - - if ((sr & USART_SR_RXNE) != 0) - { - dr = stm32_1wire_recv(priv); - - if (priv->msgs != NULL) - { - switch (priv->msgs->task) - { - case ONEWIRETASK_NONE: - break; - - case ONEWIRETASK_RESET: - priv->msgs = NULL; - priv->result = (dr != RESET_TX) ? OK : -ENODEV; /* if read RESET_TX then no slave */ - sem_post(&priv->sem_isr); - break; - - case ONEWIRETASK_WRITE: - if (++priv->bit >= 8) - { - priv->bit = 0; - if (++priv->byte >= (priv->msgs->buffer + priv->msgs->buflen)) /* Done? */ - { - priv->msgs = NULL; - priv->result = OK; - sem_post(&priv->sem_isr); - break; - } - } - - /* Send next bit */ - - stm32_1wire_send(priv, (*priv->byte & (1 << priv->bit)) ? WRITE_TX1 : WRITE_TX0); - break; - - case ONEWIRETASK_READ: - if (dr == READ_RX1) - { - *priv->byte |= (1 << priv->bit); - } - else - { - *priv->byte &= ~(1 << priv->bit); - } - - if (++priv->bit >= 8) - { - priv->bit = 0; - if (++priv->byte >= (priv->msgs->buffer + priv->msgs->buflen)) /* Done? */ - { - priv->msgs = NULL; - priv->result = OK; - sem_post(&priv->sem_isr); - break; - } - } - - /* Recv next bit */ - - stm32_1wire_send(priv, READ_TX); - break; - } - } - } - - /* Bounce check. */ - - if ((sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0) - { -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) - /* These errors are cleared by writing the corresponding bit to the - * interrupt clear register (ICR). - */ - - stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, - (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); -#else - /* If an error occurs, read from DR to clear the error (data has - * been lost). If ORE is set along with RXNE then it tells you - * that the byte *after* the one in the data register has been - * lost, but the data register value is correct. That case will - * be handled above if interrupts are enabled. Otherwise, that - * good byte will be lost. - */ - - (void)stm32_1wire_recv(priv); -#endif - - if (priv->msgs != NULL) - { - priv->msgs = NULL; - priv->result = ERROR; - sem_post(&priv->sem_isr); - } - } - - /* Bounce check. LIN break detection */ - - if ((sr & USART_SR_LBD) != 0) - { - sr &= ~USART_SR_LBD; - stm32_1wire_out(priv, STM32_USART_SR_OFFSET, sr); - - if (priv->msgs != NULL) - { - priv->msgs = NULL; - priv->result = ERROR; - sem_post(&priv->sem_isr); - } - } - - return OK; -} - -#ifdef CONFIG_STM32_1WIRE1 -static int up_interrupt_1wire1(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire1_priv); -} -#endif -#ifdef CONFIG_STM32_1WIRE2 -static int up_interrupt_1wire2(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire2_priv); -} -#endif -#ifdef CONFIG_STM32_1WIRE3 -static int up_interrupt_1wire3(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire3_priv); -} -#endif -#ifdef CONFIG_STM32_1WIRE4 -static int up_interrupt_1wire4(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire4_priv); -} -#endif -#ifdef CONFIG_STM32_1WIRE5 -static int up_interrupt_1wire5(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire5_priv); -} -#endif -#ifdef CONFIG_STM32_1WIRE6 -static int up_interrupt_1wire6(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire6_priv); -} -#endif -#ifdef CONFIG_STM32_1WIRE7 -static int up_interrupt_1wire7(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire7_priv); -} -#endif -#ifdef CONFIG_STM32_1WIRE8 -static int up_interrupt_1wire8(int irq, void *context) -{ - return stm32_1wire_isr(&stm32_1wire8_priv); -} -#endif - -/**************************************************************************** - * Name: stm32_1wire_reset - * - * Description: - * 1-Wire reset pulse and presence detect. - * - ****************************************************************************/ - -static int stm32_1wire_reset(FAR struct onewire_dev_s *dev) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_RESET - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_write - * - * Description: - * Write 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_write(FAR struct onewire_dev_s *dev, const uint8_t *buffer, - int buflen) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_WRITE, - [0].buffer = (uint8_t *)buffer, - [0].buflen = buflen - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_read - * - * Description: - * Read 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_read(FAR struct onewire_dev_s *dev, uint8_t *buffer, int buflen) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_READ, - [0].buffer = buffer, - [0].buflen = buflen - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_exchange - * - * Description: - * 1-Wire reset pulse and presence detect, - * Write 1-Wire data, - * Read 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_exchange(FAR struct onewire_dev_s *dev, bool reset, - const uint8_t *txbuffer, int txbuflen, - uint8_t *rxbuffer, int rxbuflen) - -{ - int result = ERROR; - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - - if (reset) - { - const struct stm32_1wire_msg_s msgs[3] = - { - [0].task = ONEWIRETASK_RESET, - - [1].task = ONEWIRETASK_WRITE, - [1].buffer = (uint8_t *)txbuffer, - [1].buflen = txbuflen, - - [2].task = ONEWIRETASK_READ, - [2].buffer = rxbuffer, - [2].buflen = rxbuflen - }; - - result = stm32_1wire_process(priv, msgs, 3); - } - else - { - const struct stm32_1wire_msg_s msgs[2] = - { - [0].task = ONEWIRETASK_WRITE, - [0].buffer = (uint8_t *)txbuffer, - [0].buflen = txbuflen, - - [1].task = ONEWIRETASK_READ, - [1].buffer = rxbuffer, - [1].buflen = rxbuflen - }; - - result = stm32_1wire_process(priv, msgs, 2); - } - return result; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_1wireinitialize - * - * Description: - * Initialize one 1-Wire port - * - ****************************************************************************/ - -FAR struct onewire_dev_s *up_1wireinitialize(int port) -{ - struct stm32_1wire_priv_s *priv = NULL; /* Private data of device with multiple instances */ - struct stm32_1wire_inst_s *inst = NULL; /* Device, single instance */ - int irqs; - - /* Get 1-Wire private structure */ - - switch (port) - { -#ifdef CONFIG_STM32_1WIRE1 - case 1: - priv = &stm32_1wire1_priv; - break; -#endif -#ifdef CONFIG_STM32_1WIRE2 - case 2: - priv = &stm32_1wire2_priv; - break; -#endif -#ifdef CONFIG_STM32_1WIRE3 - case 3: - priv = &stm32_1wire3_priv; - break; -#endif -#ifdef CONFIG_STM32_1WIRE4 - case 4: - priv = &stm32_1wire4_priv; - break; -#endif -#ifdef CONFIG_STM32_1WIRE5 - case 5: - priv = &stm32_1wire5_priv; - break; -#endif -#ifdef CONFIG_STM32_1WIRE6 - case 6: - priv = &stm32_1wire6_priv; - break; -#endif -#ifdef CONFIG_STM32_1WIRE7 - case 7: - priv = &stm32_1wire7_priv; - break; -#endif -#ifdef CONFIG_STM32_1WIRE8 - case 8: - priv = &stm32_1wire8_priv; - break; -#endif - default: - return NULL; - } - - /* Allocate instance */ - - if (!(inst = kmm_malloc(sizeof(struct stm32_1wire_inst_s)))) - { - return NULL; - } - - /* Initialize instance */ - - inst->ops = &stm32_1wire_ops; - inst->priv = priv; - - /* Initialize private data for the first time, increment reference count, - * power-up hardware and configure GPIOs. - */ - - irqs = irqsave(); - - if (priv->refs++ == 0) - { - stm32_1wire_sem_init(priv); - stm32_1wire_init(priv); - } - - irqrestore(irqs); - return (struct onewire_dev_s *)inst; -} - -/**************************************************************************** - * Name: up_1wireuninitialize - * - * Description: - * Uninitialize an 1-Wire port - * - ****************************************************************************/ - -int up_1wireuninitialize(FAR struct onewire_dev_s *dev) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - int irqs; - - ASSERT(dev); - - /* Decrement reference count and check for underflow */ - - if (priv->refs == 0) - { - return ERROR; - } - - irqs = irqsave(); - - if (--priv->refs) - { - irqrestore(irqs); - kmm_free(priv); - return OK; - } - - irqrestore(irqs); - - /* Disable power and other HW resource (GPIO's) */ - - stm32_1wire_deinit(priv); - - /* Release unused resources */ - - stm32_1wire_sem_destroy(priv); - - /* Free instance */ - - kmm_free(dev); - return OK; -} +/**************************************************************************** + * arch/arm/src/stm32/stm32_1wire.c + * + * Copyright (C) 2016 Aleksandr Vyhovanec. All rights reserved. + * Author: Aleksandr Vyhovanec + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* Links: + * https://www.maximintegrated.com/en/app-notes/index.mvp/id/214 + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "up_arch.h" + +#include "stm32_rcc.h" +#include "stm32_1wire.h" + +#ifdef HAVE_1WIREDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BUS_TIMEOUT 5 /* tv_sec */ + +#define RESET_BAUD 9600 +#define RESET_TX 0xF0 +#define TIMESLOT_BAUD 115200 +#define READ_TX 0xFF +#define READ_RX1 0xFF +#define WRITE_TX0 0x00 +#define WRITE_TX1 0xFF + +#define PIN_OPENDRAIN(GPIO) ((GPIO) | GPIO_OPENDRAIN) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* 1-Wire bus task */ + +enum stm32_1wire_msg_e +{ + ONEWIRETASK_NONE = 0, + ONEWIRETASK_RESET, + ONEWIRETASK_WRITE, + ONEWIRETASK_READ +}; + +struct stm32_1wire_msg_s +{ + enum stm32_1wire_msg_e task; /* Task */ + uint8_t *buffer; /* Task buffer */ + int buflen; /* Buffer length */ +}; + +/* 1-Wire device hardware configuration */ + +struct stm32_1wire_config_s +{ + const uint32_t usartbase; /* Base address of USART registers */ + const uint32_t apbclock; /* PCLK 1 or 2 frequency */ + const uint32_t data_pin; /* GPIO configuration for DATA */ + const uint8_t irq; /* IRQ associated with this USART */ + int (*const vector)(int irq, void *context); /* Interrupt handler */ +}; + +/* 1-Wire device Private Data */ + +struct stm32_1wire_priv_s +{ + const struct stm32_1wire_config_s *config; /* Port configuration */ + volatile int refs; /* Referernce count */ + sem_t sem_excl; /* Mutual exclusion semaphore */ + sem_t sem_isr; /* Interrupt wait semaphore */ + int baud; /* Baud rate */ + const struct stm32_1wire_msg_s *msgs; /* Messages data */ + uint8_t *byte; /* Current byte */ + uint8_t bit; /* Current bit */ + volatile int result; /* Exchange result */ +}; + +/* 1-Wire device, Instance */ + +struct stm32_1wire_inst_s +{ + const struct onewire_ops_s *ops; /* Standard 1-Wire operations */ + struct stm32_1wire_priv_s *priv; /* Common driver private data structure */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint32_t stm32_1wire_in(struct stm32_1wire_priv_s *priv, int offset); +static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, int offset, uint32_t value); +static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv); +static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch); +static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv); +static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, bool on); +static int stm32_1wire_init(FAR struct stm32_1wire_priv_s *priv); +static int stm32_1wire_deinit(FAR struct stm32_1wire_priv_s *priv); +static inline void stm32_1wire_sem_init(FAR struct stm32_1wire_priv_s *priv); +static inline void stm32_1wire_sem_destroy(FAR struct stm32_1wire_priv_s *priv); +static inline void stm32_1wire_sem_wait(FAR struct stm32_1wire_priv_s *priv); +static inline void stm32_1wire_sem_post(FAR struct stm32_1wire_priv_s *priv); +static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, + FAR const struct stm32_1wire_msg_s *msgs, int count); +static int stm32_1wire_isr(struct stm32_1wire_priv_s *priv); + +#ifdef CONFIG_STM32_USART1_1WIREDRIVER +static int up_interrupt_1wire1(int irq, void *context); +#endif +#ifdef CONFIG_STM32_USART2_1WIREDRIVER +static int up_interrupt_1wire2(int irq, void *context); +#endif +#ifdef CONFIG_STM32_USART3_1WIREDRIVER +static int up_interrupt_1wire3(int irq, void *context); +#endif +#ifdef CONFIG_STM32_UART4_1WIREDRIVER +static int up_interrupt_1wire4(int irq, void *context); +#endif +#ifdef CONFIG_STM32_UART5_1WIREDRIVER +static int up_interrupt_1wire5(int irq, void *context); +#endif +#ifdef CONFIG_STM32_USART6_1WIREDRIVER +static int up_interrupt_1wire6(int irq, void *context); +#endif +#ifdef CONFIG_STM32_UART7_1WIREDRIVER +static int up_interrupt_1wire7(int irq, void *context); +#endif +#ifdef CONFIG_STM32_UART8_1WIREDRIVER +static int up_interrupt_1wire8(int irq, void *context); +#endif + +static int stm32_1wire_reset(FAR struct onewire_dev_s *dev); +static int stm32_1wire_write(FAR struct onewire_dev_s *dev, + const uint8_t *buffer, int buflen); +static int stm32_1wire_read(FAR struct onewire_dev_s *dev, uint8_t *buffer, + int buflen); +static int stm32_1wire_exchange(FAR struct onewire_dev_s *dev, bool reset, + const uint8_t *txbuffer, int txbuflen, + uint8_t *rxbuffer, int rxbuflen); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* 1-Wire device structures */ + +#ifdef CONFIG_STM32_USART1_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire1_config = +{ + .usartbase = STM32_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_USART1_TX), + .irq = STM32_IRQ_USART1, + .vector = up_interrupt_1wire1, +}; + +static struct stm32_1wire_priv_s stm32_1wire1_priv = +{ + .config = &stm32_1wire1_config, + .refs = 0, + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_USART2_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire2_config = +{ + .usartbase = STM32_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_USART2_TX), + .irq = STM32_IRQ_USART2, + .vector = up_interrupt_1wire2, +}; + +static struct stm32_1wire_priv_s stm32_1wire2_priv = +{ + .config = &stm32_1wire2_config, + .refs = 0, + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_USART3_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire3_config = +{ + .usartbase = STM32_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_USART3_TX), + .irq = STM32_IRQ_USART3, + .vector = up_interrupt_1wire3, +}; + +static struct stm32_1wire_priv_s stm32_1wire3_priv = +{ + .config = &stm32_1wire3_config, + .refs = 0, + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_UART4_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire4_config = +{ + .usartbase = STM32_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_UART4_TX), + .irq = STM32_IRQ_UART4, + .vector = up_interrupt_1wire4, +}; + +static struct stm32_1wire_priv_s stm32_1wire4_priv = +{ + .config = &stm32_1wire4_config, + .refs = 0, + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_UART5_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire5_config = +{ + .usartbase = STM32_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_UART5_TX), + .irq = STM32_IRQ_UART5, + .vector = up_interrupt_1wire5, +}; + +static struct stm32_1wire_priv_s stm32_1wire5_priv = +{ + .config = &stm32_1wire5_config, + .refs = 0, + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_USART6_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire6_config = +{ + .usartbase = STM32_USART6_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_USART6_TX), + .irq = STM32_IRQ_USART6, + .vector = up_interrupt_1wire6, +}; + +static struct stm32_1wire_priv_s stm32_1wire6_priv = +{ + .config = &stm32_1wire6_config, + .refs = 0, + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_UART7_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire7_config = +{ + .usartbase = STM32_UART7_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_UART7_TX), + .irq = STM32_IRQ_UART7, + .vector = up_interrupt_1wire7, +}; + +static struct stm32_1wire_priv_s stm32_1wire7_priv = +{ + .config = &stm32_1wire7_config, + .refs = 0, + .msgs = NULL +}; + +#endif + +#ifdef CONFIG_STM32_UART8_1WIREDRIVER + +static const struct stm32_1wire_config_s stm32_1wire8_config = +{ + .usartbase = STM32_UART8_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .data_pin = PIN_OPENDRAIN(GPIO_UART8_TX), + .irq = STM32_IRQ_UART8, + .vector = up_interrupt_1wire8, +}; + +static struct stm32_1wire_priv_s stm32_1wire8_priv = +{ + .config = &stm32_1wire8_config, + .refs = 0, + .msgs = NULL +}; + +#endif + +/* Device Structures, Instantiation */ + +static const struct onewire_ops_s stm32_1wire_ops = +{ + .reset = stm32_1wire_reset, + .write = stm32_1wire_write, + .read = stm32_1wire_read, + .exchange = stm32_1wire_exchange +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_1wire_in + ****************************************************************************/ + +static inline uint32_t stm32_1wire_in(struct stm32_1wire_priv_s *priv, + int offset) +{ + return getreg32(priv->config->usartbase + offset); +} + +/**************************************************************************** + * Name: stm32_1wire_out + ****************************************************************************/ + +static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, + int offset, uint32_t value) +{ + putreg32(value, priv->config->usartbase + offset); +} + +/**************************************************************************** + * Name: stm32_1wire_recv + * + * Description: + * This method will recv one byte on the USART + * + ****************************************************************************/ + +static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) +{ + return stm32_1wire_in(priv, STM32_USART_RDR_OFFSET) & 0xff; +} + +/**************************************************************************** + * Name: stm32_1wire_send + * + * Description: + * This method will send one byte on the USART + * + ****************************************************************************/ + +static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch) +{ + stm32_1wire_out(priv, STM32_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); +} + +/**************************************************************************** + * Name: stm32_1wire_set_baud + * + * Description: + * Set the serial line baud. + * + ****************************************************************************/ + +static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) +{ +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) + /* This first implementation is for U[S]ARTs that support oversampling + * by 8 in additional to the standard oversampling by 16. + */ + + uint32_t usartdiv8; + uint32_t cr1; + uint32_t brr; + + /* In case of oversampling by 8, the equation is: + * + * baud = 2 * fCK / usartdiv8 + * usartdiv8 = 2 * fCK / baud + */ + + usartdiv8 = ((priv->config->apbclock << 1) + (priv->baud >> 1)) / priv->baud; + + /* Baud rate for standard USART (SPI mode included): + * + * In case of oversampling by 16, the equation is: + * baud = fCK / usartdiv16 + * usartdiv16 = fCK / baud + * = 2 * usartdiv8 + */ + + /* Use oversamply by 8 only if the divisor is small. But what is small? */ + + cr1 = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); + if (usartdiv8 > 100) + { + /* Use usartdiv16 */ + + brr = (usartdiv8 + 1) >> 1; + + /* Clear oversampling by 8 to enable oversampling by 16 */ + + cr1 &= ~USART_CR1_OVER8; + } + else + { + DEBUGASSERT(usartdiv8 >= 8); + + /* Perform mysterious operations on bits 0-3 */ + + brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); + + /* Set oversampling by 8 */ + + cr1 |= USART_CR1_OVER8; + } + + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); + +#else + + /* This second implementation is for U[S]ARTs that support fractional + * dividers. + */ + + uint32_t usartdiv32; + uint32_t mantissa; + uint32_t fraction; + uint32_t brr; + + /* Configure the USART Baud Rate. The baud rate for the receiver and + * transmitter (Rx and Tx) are both set to the same value as programmed + * in the Mantissa and Fraction values of USARTDIV. + * + * baud = fCK / (16 * usartdiv) + * usartdiv = fCK / (16 * baud) + * + * Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, 4, 5 + * or PCLK2 for USART1) + * + * First calculate (NOTE: all stand baud values are even so dividing by two + * does not lose precision): + * + * usartdiv32 = 32 * usartdiv = fCK / (baud/2) + */ + + usartdiv32 = priv->config->apbclock / (priv->baud >> 1); + + /* The mantissa part is then */ + + mantissa = usartdiv32 >> 5; + brr = mantissa << USART_BRR_MANT_SHIFT; + + /* The fractional remainder (with rounding) */ + + fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; + brr |= fraction << USART_BRR_FRAC_SHIFT; + stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); +#endif +} + +/**************************************************************************** + * Name: stm32_1wire_set_apb_clock + * + * Description: + * Enable or disable APB clock for the USART peripheral + * + * Input parameters: + * priv - A reference to the 1-Wire driver state structure + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + ****************************************************************************/ + +static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, + bool on) +{ + const struct stm32_1wire_config_s *config = priv->config; + uint32_t rcc_en; + uint32_t regaddr; + + /* Determine which USART to configure */ + + switch (config->usartbase) + { + default: + return; + +#ifdef CONFIG_STM32_USART1_1WIREDRIVER + case STM32_USART1_BASE: + rcc_en = RCC_APB2ENR_USART1EN; + regaddr = STM32_RCC_APB2ENR; + break; +#endif +#ifdef CONFIG_STM32_USART2_1WIREDRIVER + case STM32_USART2_BASE: + rcc_en = RCC_APB1ENR_USART2EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART3_1WIREDRIVER + case STM32_USART3_BASE: + rcc_en = RCC_APB1ENR_USART3EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_UART4 + case STM32_UART4_BASE: + rcc_en = RCC_APB1ENR_UART4EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_UART5 + case STM32_UART5_BASE: + rcc_en = RCC_APB1ENR_UART5EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_USART6_1WIREDRIVER + case STM32_USART6_BASE: + rcc_en = RCC_APB2ENR_USART6EN; + regaddr = STM32_RCC_APB2ENR; + break; +#endif +#ifdef CONFIG_STM32_UART7 + case STM32_UART7_BASE: + rcc_en = RCC_APB1ENR_UART7EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif +#ifdef CONFIG_STM32_UART8 + case STM32_UART8_BASE: + rcc_en = RCC_APB1ENR_UART8EN; + regaddr = STM32_RCC_APB1ENR; + break; +#endif + } + + /* Enable/disable APB 1/2 clock for USART */ + + if (on) + { + modifyreg32(regaddr, 0, rcc_en); + } + else + { + modifyreg32(regaddr, rcc_en, 0); + } +} + +/**************************************************************************** + * Name: stm32_1wire_init + * + * Description: + * Setup the 1-Wire hardware, ready for operation with defaults + * + ****************************************************************************/ + +static int stm32_1wire_init(FAR struct stm32_1wire_priv_s *priv) +{ + const struct stm32_1wire_config_s *config = priv->config; + uint32_t regval; + int ret; + + /* Enable USART APB1/2 clock */ + + stm32_1wire_set_apb_clock(priv, true); + + /* Configure CR2 */ + /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ + /* Set LBDIE */ + + regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); + regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | + USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); + regval |= USART_CR2_LBDIE; + stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); + + /* Configure CR1 */ + /* Clear TE, REm, all interrupt enable bits, PCE, PS and M */ + /* Set RXNEIE */ + + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); + regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS | + USART_CR1_PCE | USART_CR1_PS | USART_CR1_M); + regval |= USART_CR1_RXNEIE; + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); + + /* Configure CR3 */ + /* Clear CTSE, RTSE, and all interrupt enable bits */ + /* Set ONEBIT, HDSEL and EIE */ + + regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); + regval |= (USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); + stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); + + /* Set baud rate */ + + priv->baud = RESET_BAUD; + stm32_1wire_set_baud(priv); + + /* Enable Rx, Tx, and the USART */ + + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); + regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); + + /* Configure pins for USART use */ + + stm32_configgpio(config->data_pin); + + ret = irq_attach(config->irq, config->vector); + if (ret == OK) + { + up_enable_irq(config->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_1wire_deinit + * + * Description: + * Shutdown the 1-Wire hardware + * + ****************************************************************************/ + +static int stm32_1wire_deinit(FAR struct stm32_1wire_priv_s *priv) +{ + const struct stm32_1wire_config_s *config = priv->config; + uint32_t regval; + + up_disable_irq(config->irq); + irq_detach(config->irq); + + /* Unconfigure GPIO pins */ + + stm32_unconfiggpio(config->data_pin); + + /* Disable RXNEIE, Rx, Tx, and the USART */ + + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); + regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); + + /* Clear LBDIE */ + + regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); + regval &= ~USART_CR2_LBDIE; + stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); + + /* Clear ONEBIT, HDSEL and EIE */ + + regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); + regval &= ~(USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); + stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); + + /* Disable USART APB1/2 clock */ + + stm32_1wire_set_apb_clock(priv, false); + + return OK; +} + +/**************************************************************************** + * Name: stm32_1wire_sem_init + * + * Description: + * Initialize semaphores + * + ****************************************************************************/ + +static inline void stm32_1wire_sem_init(FAR struct stm32_1wire_priv_s *priv) +{ + sem_init(&priv->sem_excl, 0, 1); + sem_init(&priv->sem_isr, 0, 0); +} + +/**************************************************************************** + * Name: stm32_1wire_sem_destroy + * + * Description: + * Destroy semaphores. + * + ****************************************************************************/ + +static inline void stm32_1wire_sem_destroy(FAR struct stm32_1wire_priv_s *priv) +{ + sem_destroy(&priv->sem_excl); + sem_destroy(&priv->sem_isr); +} + +/**************************************************************************** + * Name: stm32_1wire_sem_wait + * + * Description: + * Take the exclusive access, waiting as necessary + * + ****************************************************************************/ + +static inline void stm32_1wire_sem_wait(FAR struct stm32_1wire_priv_s *priv) +{ + while (sem_wait(&priv->sem_excl) != 0) + { + ASSERT(errno == EINTR); + } +} + +/**************************************************************************** + * Name: stm32_1wire_sem_post + * + * Description: + * Release the mutual exclusion semaphore + * + ****************************************************************************/ + +static inline void stm32_1wire_sem_post(FAR struct stm32_1wire_priv_s *priv) +{ + sem_post(&priv->sem_excl); +} + +/**************************************************************************** + * Name: stm32_1wire_exec + * + * Description: + * Execute 1-Wire task + ****************************************************************************/ +static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, + FAR const struct stm32_1wire_msg_s *msgs, + int count) +{ + irqstate_t irqs; + struct timespec abstime; + int indx; + int ret; + + /* Lock out other clients */ + + stm32_1wire_sem_wait(priv); + + priv->result = ERROR; + + for (indx = 0; indx < count; indx++) + { + switch (msgs[indx].task) + { + case ONEWIRETASK_NONE: + priv->result = OK; + break; + + case ONEWIRETASK_RESET: + /* Set baud rate */ + + priv->baud = RESET_BAUD; + stm32_1wire_set_baud(priv); + + /* Atomic */ + + irqs = enter_critical_section(); + priv->msgs = &msgs[indx]; + stm32_1wire_send(priv, RESET_TX); + leave_critical_section(irqs); + + /* Wait */ + + clock_gettime(CLOCK_REALTIME, &abstime); + abstime.tv_sec += BUS_TIMEOUT; + sem_timedwait(&priv->sem_isr, &abstime); /* break on timeout if TX line closed to GND */ + break; + + case ONEWIRETASK_WRITE: + /* Set baud rate */ + + priv->baud = TIMESLOT_BAUD; + stm32_1wire_set_baud(priv); + + /* Atomic */ + + irqs = enter_critical_section(); + priv->msgs = &msgs[indx]; + priv->byte = priv->msgs->buffer; + priv->bit = 0; + stm32_1wire_send(priv, (*priv->byte & (1 << priv->bit)) ? WRITE_TX1 : WRITE_TX0); + leave_critical_section(irqs); + + /* Wait */ + + clock_gettime(CLOCK_REALTIME, &abstime); + abstime.tv_sec += BUS_TIMEOUT; + sem_timedwait(&priv->sem_isr, &abstime); /* break on timeout if TX line closed to GND */ + break; + + case ONEWIRETASK_READ: + /* Set baud rate */ + + priv->baud = TIMESLOT_BAUD; + stm32_1wire_set_baud(priv); + + /* Atomic */ + + irqs = enter_critical_section(); + priv->msgs = &msgs[indx]; + priv->byte = priv->msgs->buffer; + priv->bit = 0; + stm32_1wire_send(priv, READ_TX); + leave_critical_section(irqs); + + /* Wait */ + + clock_gettime(CLOCK_REALTIME, &abstime); + abstime.tv_sec += BUS_TIMEOUT; + sem_timedwait(&priv->sem_isr, &abstime); /* break on timeout if TX line closed to GND */ + break; + } + + if (priv->result != OK) /* break if error */ + { + break; + } + } + + /* Atomic */ + + irqs = enter_critical_section(); + priv->msgs = NULL; + ret = priv->result; + leave_critical_section(irqs); + + /* Release the port for re-use by other clients */ + + stm32_1wire_sem_post(priv); + + return ret; +} + +/**************************************************************************** + * Name: stm32_1wire_isr + * + * Description: + * Common Interrupt Service Routine + ****************************************************************************/ + +static int stm32_1wire_isr(struct stm32_1wire_priv_s *priv) +{ + uint32_t sr, dr; + + /* Get the masked USART status word. */ + + sr = stm32_1wire_in(priv, STM32_USART_SR_OFFSET); + + /* Receive loop */ + + if ((sr & USART_SR_RXNE) != 0) + { + dr = stm32_1wire_recv(priv); + + if (priv->msgs != NULL) + { + switch (priv->msgs->task) + { + case ONEWIRETASK_NONE: + break; + + case ONEWIRETASK_RESET: + priv->msgs = NULL; + priv->result = (dr != RESET_TX) ? OK : -ENODEV; /* if read RESET_TX then no slave */ + sem_post(&priv->sem_isr); + break; + + case ONEWIRETASK_WRITE: + if (++priv->bit >= 8) + { + priv->bit = 0; + if (++priv->byte >= (priv->msgs->buffer + priv->msgs->buflen)) /* Done? */ + { + priv->msgs = NULL; + priv->result = OK; + sem_post(&priv->sem_isr); + break; + } + } + + /* Send next bit */ + + stm32_1wire_send(priv, (*priv->byte & (1 << priv->bit)) ? WRITE_TX1 : WRITE_TX0); + break; + + case ONEWIRETASK_READ: + if (dr == READ_RX1) + { + *priv->byte |= (1 << priv->bit); + } + else + { + *priv->byte &= ~(1 << priv->bit); + } + + if (++priv->bit >= 8) + { + priv->bit = 0; + if (++priv->byte >= (priv->msgs->buffer + priv->msgs->buflen)) /* Done? */ + { + priv->msgs = NULL; + priv->result = OK; + sem_post(&priv->sem_isr); + break; + } + } + + /* Recv next bit */ + + stm32_1wire_send(priv, READ_TX); + break; + } + } + } + + /* Bounce check. */ + + if ((sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0) + { +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) + /* These errors are cleared by writing the corresponding bit to the + * interrupt clear register (ICR). + */ + + stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, + (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); +#else + /* If an error occurs, read from DR to clear the error (data has + * been lost). If ORE is set along with RXNE then it tells you + * that the byte *after* the one in the data register has been + * lost, but the data register value is correct. That case will + * be handled above if interrupts are enabled. Otherwise, that + * good byte will be lost. + */ + + (void)stm32_1wire_recv(priv); +#endif + + if (priv->msgs != NULL) + { + priv->msgs = NULL; + priv->result = ERROR; + sem_post(&priv->sem_isr); + } + } + + /* Bounce check. LIN break detection */ + + if ((sr & USART_SR_LBD) != 0) + { + sr &= ~USART_SR_LBD; + stm32_1wire_out(priv, STM32_USART_SR_OFFSET, sr); + + if (priv->msgs != NULL) + { + priv->msgs = NULL; + priv->result = ERROR; + sem_post(&priv->sem_isr); + } + } + + return OK; +} + +#ifdef CONFIG_STM32_USART1_1WIREDRIVER +static int up_interrupt_1wire1(int irq, void *context) +{ + return stm32_1wire_isr(&stm32_1wire1_priv); +} +#endif +#ifdef CONFIG_STM32_USART2_1WIREDRIVER +static int up_interrupt_1wire2(int irq, void *context) +{ + return stm32_1wire_isr(&stm32_1wire2_priv); +} +#endif +#ifdef CONFIG_STM32_USART3_1WIREDRIVER +static int up_interrupt_1wire3(int irq, void *context) +{ + return stm32_1wire_isr(&stm32_1wire3_priv); +} +#endif +#ifdef CONFIG_STM32_UART4_1WIREDRIVER +static int up_interrupt_1wire4(int irq, void *context) +{ + return stm32_1wire_isr(&stm32_1wire4_priv); +} +#endif +#ifdef CONFIG_STM32_UART5_1WIREDRIVER +static int up_interrupt_1wire5(int irq, void *context) +{ + return stm32_1wire_isr(&stm32_1wire5_priv); +} +#endif +#ifdef CONFIG_STM32_USART6_1WIREDRIVER +static int up_interrupt_1wire6(int irq, void *context) +{ + return stm32_1wire_isr(&stm32_1wire6_priv); +} +#endif +#ifdef CONFIG_STM32_UART7_1WIREDRIVER +static int up_interrupt_1wire7(int irq, void *context) +{ + return stm32_1wire_isr(&stm32_1wire7_priv); +} +#endif +#ifdef CONFIG_STM32_UART8_1WIREDRIVER +static int up_interrupt_1wire8(int irq, void *context) +{ + return stm32_1wire_isr(&stm32_1wire8_priv); +} +#endif + +/**************************************************************************** + * Name: stm32_1wire_reset + * + * Description: + * 1-Wire reset pulse and presence detect. + * + ****************************************************************************/ + +static int stm32_1wire_reset(FAR struct onewire_dev_s *dev) +{ + struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; + const struct stm32_1wire_msg_s msgs[1] = + { + [0].task = ONEWIRETASK_RESET + }; + + return stm32_1wire_process(priv, msgs, 1); +} + +/**************************************************************************** + * Name: stm32_1wire_write + * + * Description: + * Write 1-Wire data + * + ****************************************************************************/ + +static int stm32_1wire_write(FAR struct onewire_dev_s *dev, const uint8_t *buffer, + int buflen) +{ + struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; + const struct stm32_1wire_msg_s msgs[1] = + { + [0].task = ONEWIRETASK_WRITE, + [0].buffer = (uint8_t *)buffer, + [0].buflen = buflen + }; + + return stm32_1wire_process(priv, msgs, 1); +} + +/**************************************************************************** + * Name: stm32_1wire_read + * + * Description: + * Read 1-Wire data + * + ****************************************************************************/ + +static int stm32_1wire_read(FAR struct onewire_dev_s *dev, uint8_t *buffer, int buflen) +{ + struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; + const struct stm32_1wire_msg_s msgs[1] = + { + [0].task = ONEWIRETASK_READ, + [0].buffer = buffer, + [0].buflen = buflen + }; + + return stm32_1wire_process(priv, msgs, 1); +} + +/**************************************************************************** + * Name: stm32_1wire_exchange + * + * Description: + * 1-Wire reset pulse and presence detect, + * Write 1-Wire data, + * Read 1-Wire data + * + ****************************************************************************/ + +static int stm32_1wire_exchange(FAR struct onewire_dev_s *dev, bool reset, + const uint8_t *txbuffer, int txbuflen, + uint8_t *rxbuffer, int rxbuflen) + +{ + int result = ERROR; + struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; + + if (reset) + { + const struct stm32_1wire_msg_s msgs[3] = + { + [0].task = ONEWIRETASK_RESET, + + [1].task = ONEWIRETASK_WRITE, + [1].buffer = (uint8_t *)txbuffer, + [1].buflen = txbuflen, + + [2].task = ONEWIRETASK_READ, + [2].buffer = rxbuffer, + [2].buflen = rxbuflen + }; + + result = stm32_1wire_process(priv, msgs, 3); + } + else + { + const struct stm32_1wire_msg_s msgs[2] = + { + [0].task = ONEWIRETASK_WRITE, + [0].buffer = (uint8_t *)txbuffer, + [0].buflen = txbuflen, + + [1].task = ONEWIRETASK_READ, + [1].buffer = rxbuffer, + [1].buflen = rxbuflen + }; + + result = stm32_1wire_process(priv, msgs, 2); + } + return result; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_1wireinitialize + * + * Description: + * Initialize one 1-Wire port + * + ****************************************************************************/ + +FAR struct onewire_dev_s *up_1wireinitialize(int port) +{ + struct stm32_1wire_priv_s *priv = NULL; /* Private data of device with multiple instances */ + struct stm32_1wire_inst_s *inst = NULL; /* Device, single instance */ + int irqs; + + /* Get 1-Wire private structure */ + + switch (port) + { +#ifdef CONFIG_STM32_USART1_1WIREDRIVER + case 1: + priv = &stm32_1wire1_priv; + break; +#endif +#ifdef CONFIG_STM32_USART2_1WIREDRIVER + case 2: + priv = &stm32_1wire2_priv; + break; +#endif +#ifdef CONFIG_STM32_USART3_1WIREDRIVER + case 3: + priv = &stm32_1wire3_priv; + break; +#endif +#ifdef CONFIG_STM32_UART4_1WIREDRIVER + case 4: + priv = &stm32_1wire4_priv; + break; +#endif +#ifdef CONFIG_STM32_UART5_1WIREDRIVER + case 5: + priv = &stm32_1wire5_priv; + break; +#endif +#ifdef CONFIG_STM32_USART6_1WIREDRIVER + case 6: + priv = &stm32_1wire6_priv; + break; +#endif +#ifdef CONFIG_STM32_UART7_1WIREDRIVER + case 7: + priv = &stm32_1wire7_priv; + break; +#endif +#ifdef CONFIG_STM32_UART8_1WIREDRIVER + case 8: + priv = &stm32_1wire8_priv; + break; +#endif + default: + return NULL; + } + + /* Allocate instance */ + + if (!(inst = kmm_malloc(sizeof(struct stm32_1wire_inst_s)))) + { + return NULL; + } + + /* Initialize instance */ + + inst->ops = &stm32_1wire_ops; + inst->priv = priv; + + /* Initialize private data for the first time, increment reference count, + * power-up hardware and configure GPIOs. + */ + + irqs = enter_critical_section(); + + if (priv->refs++ == 0) + { + stm32_1wire_sem_init(priv); + stm32_1wire_init(priv); + } + + leave_critical_section(irqs); + return (struct onewire_dev_s *)inst; +} + +/**************************************************************************** + * Name: up_1wireuninitialize + * + * Description: + * Uninitialize an 1-Wire port + * + ****************************************************************************/ + +int up_1wireuninitialize(FAR struct onewire_dev_s *dev) +{ + struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; + int irqs; + + ASSERT(dev); + + /* Decrement reference count and check for underflow */ + + if (priv->refs == 0) + { + return ERROR; + } + + irqs = enter_critical_section(); + + if (--priv->refs) + { + leave_critical_section(irqs); + kmm_free(priv); + return OK; + } + + leave_critical_section(irqs); + + /* Disable power and other HW resource (GPIO's) */ + + stm32_1wire_deinit(priv); + + /* Release unused resources */ + + stm32_1wire_sem_destroy(priv); + + /* Free instance */ + + kmm_free(dev); + return OK; +} + +#endif /* HAVE_1WIREDRIVER */ diff --git a/arch/arm/src/stm32/stm32_1wire.h b/arch/arm/src/stm32/stm32_1wire.h index 3052849ac05..b8bb3989230 100644 --- a/arch/arm/src/stm32/stm32_1wire.h +++ b/arch/arm/src/stm32/stm32_1wire.h @@ -1,113 +1,63 @@ -/************************************************************************************ - * arch/arm/src/stm32/stm32_1wire.h - * - * Copyright (C) 2016 Aleksandr Vyhovanec. All rights reserved. - * Author: Aleksandr Vyhovanec - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_1WIRE_H -#define __ARCH_ARM_SRC_STM32_STM32_1WIRE_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "chip/stm32l15xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "chip/stm32f10xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "chip/stm32f20xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) -# include "chip/stm32f30xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F40XX) -# include "chip/stm32f40xxx_uart.h" -#else -# error "Unsupported STM32 UART" -#endif - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Check 1-Wire and U(S)ART conflicting */ - -#if defined(CONFIG_STM32_1WIRE1) && defined(CONFIG_STM32_USART1) -# undef CONFIG_STM32_1WIRE1 -#endif -#if defined(CONFIG_STM32_1WIRE2) && defined(CONFIG_STM32_USART2) -# undef CONFIG_STM32_1WIRE2 -#endif -#if defined(CONFIG_STM32_1WIRE3) && defined(CONFIG_STM32_USART3) -# undef CONFIG_STM32_1WIRE3 -#endif -#if defined(CONFIG_STM32_1WIRE4) && defined(CONFIG_STM32_UART4) -# undef CONFIG_STM32_1WIRE4 -#endif -#if defined(CONFIG_STM32_1WIRE5) && defined(CONFIG_STM32_UART5) -# undef CONFIG_STM32_1WIRE5 -#endif -#if defined(CONFIG_STM32_1WIRE6) && defined(CONFIG_STM32_USART6) -# undef CONFIG_STM32_1WIRE6 -#endif -#if defined(CONFIG_STM32_1WIRE7) && defined(CONFIG_STM32_UART7) -# undef CONFIG_STM32_1WIRE7 -#endif -#if defined(CONFIG_STM32_1WIRE8) && defined(CONFIG_STM32_UART8) -# undef CONFIG_STM32_1WIRE8 -#endif - -/* Is there a 1-Wire enabled? */ - -#if defined(CONFIG_STM32_1WIRE1) || defined(CONFIG_STM32_1WIRE2) || \ - defined(CONFIG_STM32_1WIRE3) || defined(CONFIG_STM32_1WIRE4) || \ - defined(CONFIG_STM32_1WIRE5) || defined(CONFIG_STM32_1WIRE6) || \ - defined(CONFIG_STM32_1WIRE7) || defined(CONFIG_STM32_1WIRE8) -# define HAVE_1WIRE 1 -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_STM32_1WIRE_H */ +/************************************************************************************ + * arch/arm/src/stm32/stm32_1wire.h + * + * Copyright (C) 2016 Aleksandr Vyhovanec. All rights reserved. + * Author: Aleksandr Vyhovanec + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_1WIRE_H +#define __ARCH_ARM_SRC_STM32_STM32_1WIRE_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "stm32_uart.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32_STM32_1WIRE_H */ diff --git a/arch/arm/src/stm32/stm32_lowputc.c b/arch/arm/src/stm32/stm32_lowputc.c index fcde5cd477f..0bffb74808a 100644 --- a/arch/arm/src/stm32/stm32_lowputc.c +++ b/arch/arm/src/stm32/stm32_lowputc.c @@ -436,7 +436,7 @@ void up_lowputc(char ch) void stm32_lowsetup(void) { -#if defined(HAVE_UART) +#if defined(HAVE_SERIALDRIVER) uint32_t mapr; #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) uint32_t cr; @@ -559,7 +559,7 @@ void stm32_lowsetup(void) putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ -#endif /* HAVE_UART */ +#endif /* HAVE_SERIALDRIVER */ } #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \ @@ -568,7 +568,7 @@ void stm32_lowsetup(void) void stm32_lowsetup(void) { -#if defined(HAVE_UART) +#if defined(HAVE_SERIALDRIVER) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) uint32_t cr; #endif @@ -638,7 +638,7 @@ void stm32_lowsetup(void) putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ -#endif /* HAVE_UART */ +#endif /* HAVE_SERIALDRIVER */ } #else diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index f1fc2baf1b1..eeb5a846a7b 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -272,7 +272,7 @@ #endif #ifdef USE_SERIALDRIVER -#ifdef HAVE_UART +#ifdef HAVE_SERIALDRIVER /**************************************************************************** * Private Types @@ -386,28 +386,28 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif -#ifdef CONFIG_STM32_USART1 +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static int up_interrupt_usart1(int irq, void *context); #endif -#ifdef CONFIG_STM32_USART2 +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static int up_interrupt_usart2(int irq, void *context); #endif -#ifdef CONFIG_STM32_USART3 +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static int up_interrupt_usart3(int irq, void *context); #endif -#ifdef CONFIG_STM32_UART4 +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static int up_interrupt_uart4(int irq, void *context); #endif -#ifdef CONFIG_STM32_UART5 +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static int up_interrupt_uart5(int irq, void *context); #endif -#ifdef CONFIG_STM32_USART6 +#ifdef CONFIG_STM32_USART6_SERIALDRIVER static int up_interrupt_usart6(int irq, void *context); #endif -#ifdef CONFIG_STM32_UART7 +#ifdef CONFIG_STM32_UART7_SERIALDRIVER static int up_interrupt_uart7(int irq, void *context); #endif -#ifdef CONFIG_STM32_UART8 +#ifdef CONFIG_STM32_UART8_SERIALDRIVER static int up_interrupt_uart8(int irq, void *context); #endif @@ -459,7 +459,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32_USART1 +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -467,7 +467,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32_USART2 +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -475,7 +475,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32_USART3 +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -483,7 +483,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32_UART4 +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -491,7 +491,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32_UART5 +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -499,7 +499,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32_USART6 +#ifdef CONFIG_STM32_USART6_SERIALDRIVER static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[CONFIG_USART6_TXBUFSIZE]; # ifdef CONFIG_USART6_RXDMA @@ -507,7 +507,7 @@ static char g_usart6rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32_UART7 +#ifdef CONFIG_STM32_UART7_SERIALDRIVER static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE]; # ifdef CONFIG_UART7_RXDMA @@ -515,7 +515,7 @@ static char g_uart7rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32_UART8 +#ifdef CONFIG_STM32_UART8_SERIALDRIVER static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE]; static char g_uart8txbuffer[CONFIG_UART8_TXBUFSIZE]; # ifdef CONFIG_UART8_RXDMA @@ -525,7 +525,7 @@ static char g_uart8rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32_USART1 +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct up_dev_s g_usart1priv = { .dev = @@ -587,7 +587,7 @@ static struct up_dev_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32_USART2 +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct up_dev_s g_usart2priv = { .dev = @@ -649,7 +649,7 @@ static struct up_dev_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32_USART3 +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static struct up_dev_s g_usart3priv = { .dev = @@ -711,7 +711,7 @@ static struct up_dev_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32_UART4 +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static struct up_dev_s g_uart4priv = { .dev = @@ -777,7 +777,7 @@ static struct up_dev_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32_UART5 +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static struct up_dev_s g_uart5priv = { .dev = @@ -843,7 +843,7 @@ static struct up_dev_s g_uart5priv = /* This describes the state of the STM32 USART6 port. */ -#ifdef CONFIG_STM32_USART6 +#ifdef CONFIG_STM32_USART6_SERIALDRIVER static struct up_dev_s g_usart6priv = { .dev = @@ -905,7 +905,7 @@ static struct up_dev_s g_usart6priv = /* This describes the state of the STM32 UART7 port. */ -#ifdef CONFIG_STM32_UART7 +#ifdef CONFIG_STM32_UART7_SERIALDRIVER static struct up_dev_s g_uart7priv = { .dev = @@ -940,11 +940,11 @@ static struct up_dev_s g_uart7priv = .usartbase = STM32_UART7_BASE, .tx_gpio = GPIO_UART7_TX, .rx_gpio = GPIO_UART7_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART7_OFLOWCONTROL) +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART7_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_UART7_CTS, #endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART7_IFLOWCONTROL) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART7_RTS, #endif @@ -967,7 +967,7 @@ static struct up_dev_s g_uart7priv = /* This describes the state of the STM32 UART8 port. */ -#ifdef CONFIG_STM32_UART8 +#ifdef CONFIG_STM32_UART8_SERIALDRIVER static struct up_dev_s g_uart8priv = { .dev = @@ -1002,11 +1002,11 @@ static struct up_dev_s g_uart8priv = .usartbase = STM32_UART8_BASE, .tx_gpio = GPIO_UART8_TX, .rx_gpio = GPIO_UART8_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART8_OFLOWCONTROL) +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART8_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_UART8_CTS, #endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART8_IFLOWCONTROL) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART8_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART8_RTS, #endif @@ -1031,28 +1031,28 @@ static struct up_dev_s g_uart8priv = static struct up_dev_s * const uart_devs[STM32_NUSART] = { -#ifdef CONFIG_STM32_USART1 +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32_USART2 +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32_USART3 +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32_UART4 +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [3] = &g_uart4priv, #endif -#ifdef CONFIG_STM32_UART5 +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [4] = &g_uart5priv, #endif -#ifdef CONFIG_STM32_USART6 +#ifdef CONFIG_STM32_USART6_SERIALDRIVER [5] = &g_usart6priv, #endif -#ifdef CONFIG_STM32_UART7 +#ifdef CONFIG_STM32_UART7_SERIALDRIVER [6] = &g_uart7priv, #endif -#ifdef CONFIG_STM32_UART8 +#ifdef CONFIG_STM32_UART8_SERIALDRIVER [7] = &g_uart8priv, #endif }; @@ -1376,49 +1376,49 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32_USART1 +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32_USART2 +#ifdef CONFIG_STM32_USART2_SERIALDRIVER case STM32_USART2_BASE: rcc_en = RCC_APB1ENR_USART2EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32_USART3 +#ifdef CONFIG_STM32_USART3_SERIALDRIVER case STM32_USART3_BASE: rcc_en = RCC_APB1ENR_USART3EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32_UART4 +#ifdef CONFIG_STM32_UART4_SERIALDRIVER case STM32_UART4_BASE: rcc_en = RCC_APB1ENR_UART4EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32_UART5 +#ifdef CONFIG_STM32_UART5_SERIALDRIVER case STM32_UART5_BASE: rcc_en = RCC_APB1ENR_UART5EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32_USART6 +#ifdef CONFIG_STM32_USART6_SERIALDRIVER case STM32_USART6_BASE: rcc_en = RCC_APB2ENR_USART6EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32_UART7 +#ifdef CONFIG_STM32_UART7_SERIALDRIVER case STM32_UART7_BASE: rcc_en = RCC_APB1ENR_UART7EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32_UART8 +#ifdef CONFIG_STM32_UART8_SERIALDRIVER case STM32_UART8_BASE: rcc_en = RCC_APB1ENR_UART8EN; regaddr = STM32_RCC_APB1ENR; @@ -2579,56 +2579,56 @@ static bool up_txready(struct uart_dev_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32_USART1 +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static int up_interrupt_usart1(int irq, void *context) { return up_interrupt_common(&g_usart1priv); } #endif -#ifdef CONFIG_STM32_USART2 +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static int up_interrupt_usart2(int irq, void *context) { return up_interrupt_common(&g_usart2priv); } #endif -#ifdef CONFIG_STM32_USART3 +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static int up_interrupt_usart3(int irq, void *context) { return up_interrupt_common(&g_usart3priv); } #endif -#ifdef CONFIG_STM32_UART4 +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static int up_interrupt_uart4(int irq, void *context) { return up_interrupt_common(&g_uart4priv); } #endif -#ifdef CONFIG_STM32_UART5 +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static int up_interrupt_uart5(int irq, void *context) { return up_interrupt_common(&g_uart5priv); } #endif -#ifdef CONFIG_STM32_USART6 +#ifdef CONFIG_STM32_USART6_SERIALDRIVER static int up_interrupt_usart6(int irq, void *context) { return up_interrupt_common(&g_usart6priv); } #endif -#ifdef CONFIG_STM32_UART7 +#ifdef CONFIG_STM32_UART7_SERIALDRIVER static int up_interrupt_uart7(int irq, void *context) { return up_interrupt_common(&g_uart7priv); } #endif -#ifdef CONFIG_STM32_UART8 +#ifdef CONFIG_STM32_UART8_SERIALDRIVER static int up_interrupt_uart8(int irq, void *context) { return up_interrupt_common(&g_uart8priv); @@ -2771,7 +2771,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, return OK; } #endif -#endif /* HAVE_UART */ +#endif /* HAVE_SERIALDRIVER */ #endif /* USE_SERIALDRIVER */ /**************************************************************************** @@ -2793,7 +2793,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, #ifdef USE_EARLYSERIALINIT void up_earlyserialinit(void) { -#ifdef HAVE_UART +#ifdef HAVE_SERIALDRIVER unsigned i; /* Disable all USART interrupts */ @@ -2826,7 +2826,7 @@ void up_earlyserialinit(void) void up_serialinit(void) { -#ifdef HAVE_UART +#ifdef HAVE_SERIALDRIVER char devname[16]; unsigned i; unsigned minor = 0; diff --git a/arch/arm/src/stm32/stm32_uart.h b/arch/arm/src/stm32/stm32_uart.h index 56ae3035439..76fc41e0ba0 100644 --- a/arch/arm/src/stm32/stm32_uart.h +++ b/arch/arm/src/stm32/stm32_uart.h @@ -90,18 +90,97 @@ # undef CONFIG_STM32_USART1 #endif -/* Is there a USART enabled? */ +/* Sanity checks */ -#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \ - defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_UART4) || \ - defined(CONFIG_STM32_UART5) || defined(CONFIG_STM32_USART6) || \ - defined(CONFIG_STM32_UART7) || defined(CONFIG_STM32_UART8) -# define HAVE_UART 1 +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_USART6) +# undef CONFIG_STM32_USART6_SERIALDRIVER +# undef CONFIG_STM32_USART6_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_UART7) +# undef CONFIG_STM32_UART7_SERIALDRIVER +# undef CONFIG_STM32_UART7_1WIREDRIVER +#endif +#if !defined(CONFIG_STM32_UART8) +# undef CONFIG_STM32_UART8_SERIALDRIVER +# undef CONFIG_STM32_UART8_1WIREDRIVER +#endif + +/* Check 1-Wire and U(S)ART conflicts */ + +#if defined(CONFIG_STM32_USART1_1WIREDRIVER) && defined(CONFIG_STM32_USART1_SERIALDRIVER) +# error Both CONFIG_STM32_USART1_1WIREDRIVER and CONFIG_STM32_USART1_SERIALDRIVER defined +# undef CONFIG_STM32_USART1_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART2_1WIREDRIVER) && defined(CONFIG_STM32_USART2_SERIALDRIVER) +# error Both CONFIG_STM32_USART2_1WIREDRIVER and CONFIG_STM32_USART2_SERIALDRIVER defined +# undef CONFIG_STM32_USART2_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART3_1WIREDRIVER) && defined(CONFIG_STM32_USART3_SERIALDRIVER) +# error Both CONFIG_STM32_USART3_1WIREDRIVER and CONFIG_STM32_USART3_SERIALDRIVER defined +# undef CONFIG_STM32_USART3_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_UART4_1WIREDRIVER) && defined(CONFIG_STM32_UART4_SERIALDRIVER) +# error Both CONFIG_STM32_UART4_1WIREDRIVER and CONFIG_STM32_UART4_SERIALDRIVER defined +# undef CONFIG_STM32_UART4_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_UART5_1WIREDRIVER) && defined(CONFIG_STM32_UART5_SERIALDRIVER) +# error Both CONFIG_STM32_UART5_1WIREDRIVER and CONFIG_STM32_UART5_SERIALDRIVER defined +# undef CONFIG_STM32_UART5_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_USART6_1WIREDRIVER) && defined(CONFIG_STM32_USART6_SERIALDRIVER) +# error Both CONFIG_STM32_USART6_1WIREDRIVER and CONFIG_STM32_USART6_SERIALDRIVER defined +# undef CONFIG_STM32_USART6_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_UART7_1WIREDRIVER) && defined(CONFIG_STM32_UART7_SERIALDRIVER) +# error Both CONFIG_STM32_UART7_1WIREDRIVER and CONFIG_STM32_UART7_SERIALDRIVER defined +# undef CONFIG_STM32_UART7_1WIREDRIVER +#endif +#if defined(CONFIG_STM32_UART8_1WIREDRIVER) && defined(CONFIG_STM32_UART8_SERIALDRIVER) +# error Both CONFIG_STM32_UART8_1WIREDRIVER and CONFIG_STM32_UART8_SERIALDRIVER defined +# undef CONFIG_STM32_UART8_1WIREDRIVER +#endif + +/* Is the serial driver enabled? */ + +#if defined(CONFIG_STM32_USART1_SERIALDRIVER) || defined(CONFIG_STM32_USART2_SERIALDRIVER) || \ + defined(CONFIG_STM32_USART3_SERIALDRIVER) || defined(CONFIG_STM32_UART4_SERIALDRIVER) || \ + defined(CONFIG_STM32_UART5_SERIALDRIVER) || defined(CONFIG_STM32_USART6_SERIALDRIVER) || \ + defined(CONFIG_STM32_UART7_SERIALDRIVER) || defined(CONFIG_STM32_UART8_SERIALDRIVER) +# define HAVE_SERIALDRIVER 1 +#endif + +/* Is the 1-Wire driver? */ + +#if defined(CONFIG_STM32_USART1_1WIREDRIVER) || defined(CONFIG_STM32_USART2_1WIREDRIVER) || \ + defined(CONFIG_STM32_USART3_1WIREDRIVER) || defined(CONFIG_STM32_UART4_1WIREDRIVER) || \ + defined(CONFIG_STM32_UART5_1WIREDRIVER) || defined(CONFIG_STM32_USART6_1WIREDRIVER) || \ + defined(CONFIG_STM32_UART7_1WIREDRIVER) || defined(CONFIG_STM32_UART8_1WIREDRIVER) +# define HAVE_1WIREDRIVER 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -111,7 +190,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -121,7 +200,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -131,7 +210,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -141,7 +220,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -151,7 +230,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -161,7 +240,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7) +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -172,7 +251,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8) +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -197,7 +276,7 @@ /* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX configuration */ -#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA) +#if !defined(HAVE_SERIALDRIVER) || !defined(CONFIG_ARCH_DMA) # undef CONFIG_USART1_RXDMA # undef CONFIG_USART2_RXDMA # undef CONFIG_USART3_RXDMA @@ -210,35 +289,35 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32_USART1 +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32_USART2 +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32_USART3 +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32_UART4 +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32_UART5 +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif -#ifndef CONFIG_STM32_USART6 +#ifndef CONFIG_STM32_USART6_SERIALDRIVER # undef CONFIG_USART6_RXDMA #endif -#ifndef CONFIG_STM32_UART7 +#ifndef CONFIG_STM32_UART7_SERIALDRIVER # undef CONFIG_UART7_RXDMA #endif -#ifndef CONFIG_STM32_UART8 +#ifndef CONFIG_STM32_UART8_SERIALDRIVER # undef CONFIG_UART8_RXDMA #endif @@ -276,21 +355,21 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) +#elif defined(CONFIG_STM32_UART7_SERIALDRIVER) && !defined(CONFIG_UART7_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) +#elif defined(CONFIG_STM32_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif