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riscv/saveusercontext: Fix FPU state save

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Ville Juven
2023-06-01 15:37:57 +03:00
committed by Xiang Xiao
parent 0ea9debfce
commit 4a468b8d3b
1 changed files with 4 additions and 1 deletions
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arch/risc-v/src/common/riscv_saveusercontext.S
+4 -1
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@@ -56,7 +56,10 @@ up_saveusercontext:
REGSTORE sp, REG_X2(a0) /* original SP */ REGSTORE sp, REG_X2(a0) /* original SP */
REGSTORE x1, REG_EPC(a0) REGSTORE x1, REG_EPC(a0)
riscv_savefpu a0 #ifdef CONFIG_ARCH_FPU
addi a0, a0, INT_XCPT_SIZE /* Save FPU after integer regs */
riscv_savefpu a0
#endif
li a0, 0 li a0, 0
jr ra jr ra