basic support for QSPI in STM32L4; verified via 'examples/media'

arch/arm/src/stm32l4/Kconfig

@@ -179,9 +179,38 @@ config STM32L4_FMC
 	bool "FMC"
 	default n
 
-config STM32L4_QUADSPI
+config STM32L4_QSPI
 	bool "QuadSPI"
 	default n
+	---help---
+		The STM32L4 QSPI block is intended to support one serial NOR flash device
+
+if STM32L4_QSPI
+
+config STM32L4_QSPI_FLASH_SIZE
+	int "Size of attached serial flash, bytes"
+	default 16777216
+	range 1 2147483648
+	---help---
+		The STM32L4 QSPI peripheral requires the size of the Flash be specified
+
+config STM32L4_QSPI_FIFO_THESHOLD
+	int "Number of bytes before asserting FIFO threshold flag"
+	default 4
+	range 1 16
+	---help---
+		The STM32L4 QSPI peripheral requires that the FIFO threshold be specified
+		I would leave it at the default value of 4 unless you know what you are doing.
+
+config STM32L4_QSPI_CSHT
+	int "Number of cycles Chip Select must be inactive between transactions"
+	default 1
+	range 1 8
+	---help---
+		The STM32L4 QSPI peripheral requires that it be specified the minimum number
+		of AHB cycles that Chip Select be held inactive between transactions.
+		
+endif
 
 comment "APB1 Peripherals"
 

arch/arm/src/stm32l4/Make.defs

@@ -157,3 +157,7 @@ endif
 ifeq ($(CONFIG_STM32L4_RNG),y)
 CHIP_CSRCS += stm32l4_rng.c
 endif
+
+ifeq ($(CONFIG_STM32L4_QSPI),y)
+CHIP_CSRCS += stm32l4_qspi.c
+endif

arch/arm/src/stm32l4/chip/stm32l4_qspi.h

@@ -0,0 +1,239 @@
+/****************************************************************************
+ * arch/arm/src/stm32l4/chip/stm32l4_qspi.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: dev@ziggurat29.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_QSPI_H
+#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_QSPI_H
+
+/****************************************************************************************
+ * Included Files
+ ****************************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/stm32l4/chip.h>
+
+#include "chip/stm32l4_memorymap.h"
+
+/****************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************/
+/* General Characteristics **************************************************************/
+
+#define STM32L4_QSPI_MINBITS            8         /* Minimum word width */
+#define STM32L4_QSPI_MAXBITS            32        /* Maximum word width */
+
+
+/* QSPI register offsets ****************************************************************/
+
+#define STM32L4_QUADSPI_CR_OFFSET       0x0000    /* Control Register */
+#define STM32L4_QUADSPI_DCR_OFFSET      0x0004    /* Device Configuration Register */
+#define STM32L4_QUADSPI_SR_OFFSET       0x0008    /* Status Register */
+#define STM32L4_QUADSPI_FCR_OFFSET      0x000c    /* Flag Clear Register */
+#define STM32L4_QUADSPI_DLR_OFFSET      0x0010    /* Data Length Register */
+#define STM32L4_QUADSPI_CCR_OFFSET      0x0014    /* Communication Configuration Register */
+#define STM32L4_QUADSPI_AR_OFFSET       0x0018    /* Address Register */
+#define STM32L4_QUADSPI_ABR_OFFSET      0x001c    /* Alternate Bytes Register */
+#define STM32L4_QUADSPI_DR_OFFSET       0x0020    /* Data Register */
+#define STM32L4_QUADSPI_PSMKR_OFFSET    0x0024    /* Polling Status mask Register */
+#define STM32L4_QUADSPI_PSMAR_OFFSET    0x0028    /* Polling Status match Register */
+#define STM32L4_QUADSPI_PIR_OFFSET      0x002c    /* Polling Interval Register */
+#define STM32L4_QUADSPI_LPTR_OFFSET     0x0030    /* Low-Power Timeout Register */
+
+/* QSPI register addresses **************************************************************/
+
+#define STM32L4_QUADSPI_CR       (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CR_OFFSET)    /* Control Register */
+#define STM32L4_QUADSPI_DCR      (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DCR_OFFSET)   /* Device Configuration Register */
+#define STM32L4_QUADSPI_SR       (STM32L4_QSPI_BASE+STM32L4_QUADSPI_SR_OFFSET)    /* Status Register */
+#define STM32L4_QUADSPI_FCR      (STM32L4_QSPI_BASE+STM32L4_QUADSPI_FCR_OFFSET)   /* Flag Clear Register */
+#define STM32L4_QUADSPI_DLR      (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DLR_OFFSET)   /* Data Length Register */
+#define STM32L4_QUADSPI_CCR      (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CCR_OFFSET)   /* Communication Configuration Register */
+#define STM32L4_QUADSPI_AR       (STM32L4_QSPI_BASE+STM32L4_QUADSPI_AR_OFFSET)    /* Address Register */
+#define STM32L4_QUADSPI_ABR      (STM32L4_QSPI_BASE+STM32L4_QUADSPI_ABR_OFFSET)   /* Alternate Bytes Register */
+#define STM32L4_QUADSPI_DR       (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DR_OFFSET)    /* Data Register */
+#define STM32L4_QUADSPI_PSMKR    (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */
+#define STM32L4_QUADSPI_PSMAR    (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */
+#define STM32L4_QUADSPI_PIR      (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PIR_OFFSET)   /* Polling Interval Register */
+#define STM32L4_QUADSPI_LPTR     (STM32L4_QSPI_BASE+STM32L4_QUADSPI_LPTR_OFFSET)  /* Low-Power Timeout Register */
+
+/* QSPI register bit definitions ********************************************************/
+
+/* Control Register */
+
+#define QSPI_CR_EN                 (1 << 0)   /* Bit 0:  QSPI Enable */
+#define QSPI_CR_ABORT              (1 << 1)   /* Bit 1:  Abort request */
+#define QSPI_CR_DMAEN              (1 << 2)   /* Bit 2:  DMA enable */
+#define QSPI_CR_TCEN               (1 << 3)   /* Bit 3:  Timeout counter enable */
+#define QSPI_CR_SSHIFT             (1 << 4)   /* Bit 4:  Sample shift */
+#define QSPI_CR_FTHRES_SHIFT       (8)        /* Bits 8-15: FIFO threshold level */
+#define QSPI_CR_FTHRES_MASK        (0xff << QSPI_CR_FTHRES_SHIFT)
+#define QSPI_CR_TEIE               (1 << 16)  /* Bit 16:  Transfer error interrupt enable */
+#define QSPI_CR_TCIE               (1 << 17)  /* Bit 17:  Transfer complete interrupt enable */
+#define QSPI_CR_FTIE               (1 << 18)  /* Bit 18:  FIFO threshold interrupt enable */
+#define QSPI_CR_SMIE               (1 << 19)  /* Bit 19:  Status match interrupt enable */
+#define QSPI_CR_TOIE               (1 << 20)  /* Bit 20:  TimeOut interrupt enable */
+#define QSPI_CR_APMS               (1 << 22)  /* Bit 22:  Automatic poll mode stop */
+#define QSPI_CR_PMM                (1 << 23)  /* Bit 23:  Polling match mode */
+#define QSPI_CR_PRESCALER_SHIFT    (24)       /* Bits 24-31: Clock prescaler */
+#define QSPI_CR_PRESCALER_MASK     (0xff << QSPI_CR_PRESCALER_SHIFT)
+
+/* Device Configuration Register */
+
+#define QSPI_DCR_CKMODE            (1 << 0)   /* Bit 0:  Mode 0 / mode 3 */
+#define QSPI_DCR_CSHT_SHIFT        (8)        /* Bits 8-10: Chip select high time */
+#define QSPI_DCR_CSHT_MASK         (0x7 << QSPI_DCR_CSHT_SHIFT)
+#define QSPI_DCR_FSIZE_SHIFT       (16)       /* Bits 16-20: Flash memory size */
+#define QSPI_DCR_FSIZE_MASK        (0x1f << QSPI_DCR_FSIZE_SHIFT)
+
+/* Status Register */
+
+#define QSPI_SR_TEF                (1 << 0)   /* Bit 0:  Transfer error flag */
+#define QSPI_SR_TCF                (1 << 1)   /* Bit 1:  Transfer complete flag */
+#define QSPI_SR_FTF                (1 << 2)   /* Bit 2:  FIFO threshold flag */
+#define QSPI_SR_SMF                (1 << 3)   /* Bit 3:  Status match flag */
+#define QSPI_SR_TOF                (1 << 4)   /* Bit 4:  Timeout flag */
+#define QSPI_SR_BUSY               (1 << 5)   /* Bit 5:  Busy */
+#define QSPI_SR_FLEVEL_SHIFT       (8)        /* Bits 8-12: FIFO threshold level */
+#define QSPI_SR_FLEVEL_MASK        (0x1f << QSPI_SR_FLEVEL_SHIFT)
+
+/* Flag Clear Register */
+
+#define QSPI_FCR_CTEF              (1 << 0)   /* Bit 0:  Clear Transfer error flag */
+#define QSPI_FCR_CTCF              (1 << 1)   /* Bit 1:  Clear Transfer complete flag */
+#define QSPI_FCR_CSMF              (1 << 3)   /* Bit 3:  Clear Status match flag */
+#define QSPI_FCR_CTOF              (1 << 4)   /* Bit 4:  Clear Timeout flag */
+
+/* Data Length Register */
+
+/* Communication Configuration Register */
+
+#define CCR_IMODE_NONE      0   /* No instruction */
+#define CCR_IMODE_SINGLE    1   /* Instruction on a single line */
+#define CCR_IMODE_DUAL      2   /* Instruction on two lines */
+#define CCR_IMODE_QUAD      3   /* Instruction on four lines */
+
+#define CCR_ADMODE_NONE     0   /* No address */
+#define CCR_ADMODE_SINGLE   1   /* Address on a single line */
+#define CCR_ADMODE_DUAL     2   /* Address on two lines */
+#define CCR_ADMODE_QUAD     3   /* Address on four lines */
+
+#define CCR_ADSIZE_8        0   /* 8-bit address */
+#define CCR_ADSIZE_16       1   /* 16-bit address */
+#define CCR_ADSIZE_24       2   /* 24-bit address */
+#define CCR_ADSIZE_32       3   /* 32-bit address */
+
+#define CCR_ABMODE_NONE     0   /* No alternate bytes */
+#define CCR_ABMODE_SINGLE   1   /* Alternate bytes on a single line */
+#define CCR_ABMODE_DUAL     2   /* Alternate bytes on two lines */
+#define CCR_ABMODE_QUAD     3   /* Alternate bytes on four lines */
+
+#define CCR_ABSIZE_8        0   /* 8-bit alternate byte */
+#define CCR_ABSIZE_16       1   /* 16-bit alternate bytes */
+#define CCR_ABSIZE_24       2   /* 24-bit alternate bytes */
+#define CCR_ABSIZE_32       3   /* 32-bit alternate bytes */
+
+#define CCR_DMODE_NONE      0   /* No data */
+#define CCR_DMODE_SINGLE    1   /* Data on a single line */
+#define CCR_DMODE_DUAL      2   /* Data on two lines */
+#define CCR_DMODE_QUAD      3   /* Data on four lines */
+
+#define CCR_FMODE_INDWR     0   /* Indirect write mode */
+#define CCR_FMODE_INDRD     1   /* Indirect read mode */
+#define CCR_FMODE_AUTOPOLL  2   /* Automatic polling mode */
+#define CCR_FMODE_MEMMAP    3   /* Memory-mapped mode */
+
+#define QSPI_CCR_INSTRUCTION_SHIFT (0)        /* Bits 0-7: Instruction */
+#define QSPI_CCR_INSTRUCTION_MASK  (0xff << QSPI_CCR_INSTRUCTION_SHIFT)
+#  define QSPI_CCR_INST(n)         ((uint32_t)(n) << QSPI_CCR_INSTRUCTION_SHIFT)
+#define QSPI_CCR_IMODE_SHIFT       (8)        /* Bits 8-9: Instruction mode */
+#define QSPI_CCR_IMODE_MASK        (0x3 << QSPI_CCR_IMODE_SHIFT)
+#  define QSPI_CCR_IMODE(n)        ((uint32_t)(n) << QSPI_CCR_IMODE_SHIFT)
+#define QSPI_CCR_ADMODE_SHIFT      (10)        /* Bits 10-11: Address mode */
+#define QSPI_CCR_ADMODE_MASK       (0x3 << QSPI_CCR_ADMODE_SHIFT)
+#  define QSPI_CCR_ADMODE(n)       ((uint32_t)(n) << QSPI_CCR_ADMODE_SHIFT)
+#define QSPI_CCR_ADSIZE_SHIFT      (12)        /* Bits 12-13: Address size */
+#define QSPI_CCR_ADSIZE_MASK       (0x3 << QSPI_CCR_ADSIZE_SHIFT)
+#  define QSPI_CCR_ADSIZE(n)       ((uint32_t)(n) << QSPI_CCR_ADSIZE_SHIFT)
+#define QSPI_CCR_ABMODE_SHIFT      (14)        /* Bits 14-15: Alternate bytes mode */
+#define QSPI_CCR_ABMODE_MASK       (0x3 << QSPI_CCR_ABMODE_SHIFT)
+#  define QSPI_CCR_ABMODE(n)       ((uint32_t)(n) << QSPI_CCR_ABMODE_SHIFT)
+#define QSPI_CCR_ABSIZE_SHIFT      (16)        /* Bits 16-17: Alternate bytes size */
+#define QSPI_CCR_ABSIZE_MASK       (0x3 << QSPI_CCR_ABSIZE_SHIFT)
+#  define QSPI_CCR_ABSIZE(n)       ((uint32_t)(n) << QSPI_CCR_ABSIZE_SHIFT)
+#define QSPI_CCR_DCYC_SHIFT        (18)        /* Bits 18-23: Number of dummy cycles */
+#define QSPI_CCR_DCYC_MASK         (0x1f << QSPI_CCR_DCYC_SHIFT)
+#  define QSPI_CCR_DCYC(n)         ((uint32_t)(n) << QSPI_CCR_DCYC_SHIFT)
+#define QSPI_CCR_DMODE_SHIFT       (24)        /* Bits 24-25: Data mode */
+#define QSPI_CCR_DMODE_MASK        (0x3 << QSPI_CCR_DMODE_SHIFT)
+#  define QSPI_CCR_DMODE(n)        ((uint32_t)(n) << QSPI_CCR_DMODE_SHIFT)
+#define QSPI_CCR_FMODE_SHIFT       (26)        /* Bits 26-27: Functional mode */
+#define QSPI_CCR_FMODE_MASK        (0x3 << QSPI_CCR_FMODE_SHIFT)
+#  define QSPI_CCR_FMODE(n)        ((uint32_t)(n) << QSPI_CCR_FMODE_SHIFT)
+#define QSPI_CCR_SIOO              (1 << 28)   /* Bit 28:  Send instruction only once mode */
+#define QSPI_CCR_DDRM              (1 << 31)   /* Bit 31:  Double data rate mode */
+
+/* Address Register */
+
+/* Alternate Bytes Register */
+
+/* Data Register */
+
+/* Polling Status mask Register */
+
+/* Polling Status match Register */
+
+/* Polling Interval Register */
+
+#define QSPI_PIR_INTERVAL_SHIFT    (0)        /* Bits 0-15: Polling interval */
+#define QSPI_PIR_INTERVAL_MASK     (0xFFff << QSPI_PIR_INTERVAL_SHIFT)
+
+/* Low-Power Timeout Register */
+
+#define QSPI_LPTR_TIMEOUT_SHIFT    (0)        /* Bits 0-15: Timeout period */
+#define QSPI_LPTR_TIMEOUT_MASK     (0xFFff << QSPI_PIR_INTERVAL_SHIFT)
+
+/****************************************************************************************
+ * Public Types
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Data
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Functions
+ ****************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_QSPI_H */
+
+

arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h

@@ -359,18 +359,18 @@
 
 /* QUADSPI */
 
-#define GPIO_QUADSPI_NCS_1      (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_QSPI_NCS_1         (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
-#define GPIO_QUADSPI_NCS_2      (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11)
+#define GPIO_QSPI_NCS_2         (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11)
-#define GPIO_QUADSPI_CLK_1      (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_QSPI_CLK_1         (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_QUADSPI_CLK_2      (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10)
+#define GPIO_QSPI_CLK_2         (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10)
-#define GPIO_QUADSPI_BK1_IO0_1  (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_QSPI_BK1_IO0_1     (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
-#define GPIO_QUADSPI_BK1_IO0_2  (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12)
+#define GPIO_QSPI_BK1_IO0_2     (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12)
-#define GPIO_QUADSPI_BK1_IO1_1  (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_QSPI_BK1_IO1_1     (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
-#define GPIO_QUADSPI_BK1_IO1_2  (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13)
+#define GPIO_QSPI_BK1_IO1_2     (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13)
-#define GPIO_QUADSPI_BK1_IO2_1  (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_QSPI_BK1_IO2_1     (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_QUADSPI_BK1_IO2_2  (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14)
+#define GPIO_QSPI_BK1_IO2_2     (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14)
-#define GPIO_QUADSPI_BK1_IO3_1  (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_QSPI_BK1_IO3_1     (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN6)
-#define GPIO_QUADSPI_BK1_IO3_2  (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN15)
+#define GPIO_QSPI_BK1_IO3_2     (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN15)
 
 /* RTC */
 

arch/arm/src/stm32l4/stm32l4_qspi.h

@@ -0,0 +1,107 @@
+/****************************************************************************
+ * arch/arm/src/stm32l4/stm32l4_qspi.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: dev@ziggurat29.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_QSPI_H
+#define __ARCH_ARM_SRC_STM32L4_STM32L4_QSPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "chip.h"
+
+#ifdef CONFIG_STM32L4_QSPI
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32l4_qspi_initialize
+ *
+ * Description:
+ *   Initialize the selected QSPI port in master mode
+ *
+ * Input Parameter:
+ *   intf - Interface number(must be zero)
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+struct qspi_dev_s;
+FAR struct qspi_dev_s *stm32l4_qspi_initialize(int intf);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_STM32L4_QSPI */
+#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_QSPI_H */

arch/arm/src/stm32l4/stm32l4x6xx_rcc.c

@@ -259,7 +259,7 @@ static inline void rcc_enableahb3(void)
 #endif
 
 
-#ifdef CONFIG_STM32L4_QUADSPI
+#ifdef CONFIG_STM32L4_QSPI
   /* QuadSPI module clock enable */
 
   regval |= RCC_AHB3ENR_QSPIEN;

configs/stm32l476vg-disco/include/board.h

@@ -137,6 +137,21 @@
 
 #endif
 
+/* Quad SPI pin mapping */
+
+#define GPIO_QSPI_CS         (GPIO_QSPI_NCS_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
+#define GPIO_QSPI_IO0        (GPIO_QSPI_BK1_IO0_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
+#define GPIO_QSPI_IO1        (GPIO_QSPI_BK1_IO1_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
+#define GPIO_QSPI_IO2        (GPIO_QSPI_BK1_IO2_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
+#define GPIO_QSPI_IO3        (GPIO_QSPI_BK1_IO3_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
+#define GPIO_QSPI_SCK        (GPIO_QSPI_CLK_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
+
+//XXX hmm, elsewhere
+//#define QSPI_USE_INTERRUPTS  1
+//XXX hmm, better? (2^(23+1)); this is the value that goes into FSIZE
+//#define QSPI_FLASH_SIZE      23
+
+
 /* SPI
  */
 

configs/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h

@@ -67,6 +67,9 @@
 #define STM32L4_LSI_FREQUENCY     32000
 #define STM32L4_LSE_FREQUENCY     32768
 
+#define BOARD_AHB_FREQUENCY       80000000ul
+
+
 /* XXX review the STM32L4_BOARD_USEHSI usage, it has too much influence in
  * stm32l4x6xx_rcc.c.  I suspect it is fine for it to turn on and off that
  * ocillator, but really that's all it should do (e.g. it also controls

configs/stm32l476vg-disco/nsh/Make.defs

@@ -105,6 +105,10 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
   LDFLAGS += -g
 endif
 
+LDFLAGS += -Map=${TOPDIR}/nuttx.map
+#CFLAGS += -Wa,-adhln
+#CXXFLAGS += -Wa,-adhln
+
 HOSTCC = gcc
 HOSTINCLUDES = -I.
 HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe

configs/stm32l476vg-disco/nsh/defconfig

@@ -49,10 +49,10 @@ CONFIG_DEBUG_VERBOSE=y
 #
 # Subsystem Debug Options
 #
-CONFIG_DEBUG_BINFMT=y
+# CONFIG_DEBUG_BINFMT is not set
-CONFIG_DEBUG_FS=y
+# CONFIG_DEBUG_FS is not set
-CONFIG_DEBUG_GRAPHICS=y
+# CONFIG_DEBUG_GRAPHICS is not set
-CONFIG_DEBUG_LIB=y
+# CONFIG_DEBUG_LIB is not set
 # CONFIG_DEBUG_MM is not set
 # CONFIG_DEBUG_SCHED is not set
 
@@ -65,11 +65,11 @@ CONFIG_DEBUG_LIB=y
 #
 # Driver Debug Options
 #
-CONFIG_DEBUG_LEDS=y
+# CONFIG_DEBUG_LEDS is not set
-CONFIG_DEBUG_ANALOG=y
+# CONFIG_DEBUG_ANALOG is not set
-CONFIG_DEBUG_GPIO=y
+# CONFIG_DEBUG_GPIO is not set
 # CONFIG_DEBUG_RTC is not set
-CONFIG_DEBUG_SPI=y
+# CONFIG_DEBUG_SPI is not set
 CONFIG_ARCH_HAVE_STACKCHECK=y
 # CONFIG_STACK_COLORATION is not set
 CONFIG_DEBUG_SYMBOLS=y
@@ -143,6 +143,7 @@ CONFIG_ARCH_CORTEXM4=y
 # CONFIG_ARCH_CORTEXR7F is not set
 CONFIG_ARCH_FAMILY="armv7-m"
 CONFIG_ARCH_CHIP="stm32l4"
+# CONFIG_ARM_TOOLCHAIN_IAR is not set
 CONFIG_ARM_TOOLCHAIN_GNU=y
 # CONFIG_ARMV7M_USEBASEPRI is not set
 CONFIG_ARCH_HAVE_CMNVECTOR=y
@@ -165,6 +166,7 @@ CONFIG_ARMV7M_HAVE_ITCM=y
 CONFIG_ARMV7M_HAVE_DTCM=y
 # CONFIG_ARMV7M_ITCM is not set
 # CONFIG_ARMV7M_DTCM is not set
+# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set
 # CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
 # CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
 # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set
@@ -224,7 +226,10 @@ CONFIG_STM32L4_RNG=y
 # AHB3 Peripherals
 #
 # CONFIG_STM32L4_FMC is not set
-# CONFIG_STM32L4_QUADSPI is not set
+CONFIG_STM32L4_QSPI=y
+CONFIG_STM32L4_QSPI_FLASH_SIZE=16777216
+CONFIG_STM32L4_QSPI_FIFO_THESHOLD=4
+CONFIG_STM32L4_QSPI_CSHT=1
 
 #
 # APB1 Peripherals
@@ -372,7 +377,14 @@ CONFIG_NSH_MMCSDMINOR=0
 #
 # Board-Specific Options
 #
-# CONFIG_LIB_BOARDCTL is not set
+CONFIG_LIB_BOARDCTL=y
+# CONFIG_BOARDCTL_RESET is not set
+# CONFIG_BOARDCTL_UNIQUEID is not set
+# CONFIG_BOARDCTL_TSCTEST is not set
+# CONFIG_BOARDCTL_ADCTEST is not set
+# CONFIG_BOARDCTL_PWMTEST is not set
+# CONFIG_BOARDCTL_GRAPHICS is not set
+# CONFIG_BOARDCTL_IOCTL is not set
 
 #
 # RTOS Features
@@ -532,7 +544,38 @@ CONFIG_RTC_IOCTL=y
 # CONFIG_PCA9635PW is not set
 # CONFIG_MMCSD is not set
 # CONFIG_MODEM is not set
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+
+#
+# MTD Configuration
+#
+# CONFIG_MTD_PARTITION is not set
+# CONFIG_MTD_SECT512 is not set
+# CONFIG_MTD_BYTE_WRITE is not set
+# CONFIG_MTD_PROGMEM is not set
+# CONFIG_MTD_CONFIG is not set
+
+#
+# MTD Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+# CONFIG_RAMMTD is not set
+# CONFIG_FILEMTD is not set
+# CONFIG_MTD_AT24XX is not set
+# CONFIG_MTD_AT25 is not set
+# CONFIG_MTD_AT45DB is not set
+# CONFIG_MTD_M25P is not set
+# CONFIG_MTD_S25FL1 is not set
+CONFIG_MTD_N25QXXX=y
+CONFIG_N25QXXX_QSPIMODE=0
+CONFIG_N25QXXX_QSPI_FREQUENCY=80000000
+# CONFIG_N25QXXX_SECTOR512 is not set
+# CONFIG_MTD_SMART is not set
+# CONFIG_MTD_RAMTRON is not set
+# CONFIG_MTD_SST25 is not set
+# CONFIG_MTD_SST25XX is not set
+# CONFIG_MTD_SST39FV is not set
+# CONFIG_MTD_W25 is not set
 # CONFIG_EEPROM is not set
 # CONFIG_PIPES is not set
 # CONFIG_PM is not set
@@ -603,7 +646,12 @@ CONFIG_USART2_2STOP=0
 #
 # System Logging
 #
-# CONFIG_RAMLOG is not set
+CONFIG_RAMLOG=y
+CONFIG_RAMLOG_SYSLOG=y
+# CONFIG_RAMLOG_CONSOLE is not set
+CONFIG_RAMLOG_BUFSIZE=8192
+# CONFIG_RAMLOG_CRLF is not set
+CONFIG_RAMLOG_NONBLOCKING=y
 # CONFIG_SYSLOG_CONSOLE is not set
 
 #
@@ -628,25 +676,41 @@ CONFIG_USART2_2STOP=0
 # CONFIG_DISABLE_MOUNTPOINT is not set
 # CONFIG_FS_AUTOMOUNTER is not set
 # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set
-# CONFIG_FS_READABLE is not set
+CONFIG_FS_READABLE=y
-# CONFIG_FS_WRITABLE is not set
+CONFIG_FS_WRITABLE=y
 # CONFIG_FS_NAMED_SEMAPHORES is not set
 CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 # CONFIG_FS_RAMMAP is not set
-# CONFIG_FS_FAT is not set
+CONFIG_FS_FAT=y
+# CONFIG_FAT_LCNAMES is not set
+# CONFIG_FAT_LFN is not set
+# CONFIG_FS_FATTIME is not set
+# CONFIG_FAT_FORCE_INDIRECT is not set
+# CONFIG_FAT_DMAMEMORY is not set
+# CONFIG_FAT_DIRECT_RETRY is not set
 # CONFIG_FS_NXFFS is not set
 # CONFIG_FS_ROMFS is not set
 # CONFIG_FS_TMPFS is not set
 # CONFIG_FS_SMARTFS is not set
 # CONFIG_FS_BINFS is not set
-# CONFIG_FS_PROCFS is not set
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+
+#
+# Exclude individual procfs entries
+#
+# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set
+# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set
+# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set
+# CONFIG_FS_PROCFS_EXCLUDE_MTD is not set
 # CONFIG_FS_UNIONFS is not set
 
 #
 # System Logging
 #
-# CONFIG_SYSLOG is not set
+CONFIG_SYSLOG=y
 # CONFIG_SYSLOG_TIMESTAMP is not set
+# CONFIG_SYSLOG_CHAR is not set
 
 #
 # Graphics Support
@@ -707,6 +771,8 @@ CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048
 # CONFIG_LIBC_STRERROR is not set
 # CONFIG_LIBC_PERROR_STDOUT is not set
+CONFIG_LIBC_TMPDIR="/tmp"
+CONFIG_LIBC_MAX_TMPFILE=32
 CONFIG_ARCH_LOWPUTC=y
 # CONFIG_LIBC_LOCALTIME is not set
 # CONFIG_TIME_EXTENDED is not set
@@ -716,6 +782,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
 CONFIG_ARCH_HAVE_TLS=y
 # CONFIG_TLS is not set
 # CONFIG_LIBC_NETDB is not set
+# CONFIG_NETDB_HOSTFILE is not set
 
 #
 # Non-standard Library Support
@@ -771,6 +838,14 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7"
 # CONFIG_EXAMPLES_CXXTEST is not set
 # CONFIG_EXAMPLES_DHCPD is not set
 # CONFIG_EXAMPLES_ELF is not set
+CONFIG_EXAMPLES_FSTEST=y
+CONFIG_EXAMPLES_FSTEST_MAXNAME=32
+CONFIG_EXAMPLES_FSTEST_MAXFILE=8192
+CONFIG_EXAMPLES_FSTEST_MAXIO=347
+CONFIG_EXAMPLES_FSTEST_MAXOPEN=512
+CONFIG_EXAMPLES_FSTEST_MOUNTPT="/mnt/n25qxxx"
+CONFIG_EXAMPLES_FSTEST_NLOOPS=1
+CONFIG_EXAMPLES_FSTEST_VERBOSE=y
 # CONFIG_EXAMPLES_FTPC is not set
 # CONFIG_EXAMPLES_FTPD is not set
 # CONFIG_EXAMPLES_HELLO is not set
@@ -779,7 +854,9 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7"
 # CONFIG_EXAMPLES_HIDKBD is not set
 # CONFIG_EXAMPLES_KEYPADTEST is not set
 # CONFIG_EXAMPLES_IGMP is not set
-# CONFIG_EXAMPLES_MEDIA is not set
+CONFIG_EXAMPLES_MEDIA=y
+CONFIG_EXAMPLES_MEDIA_DEVPATH="/dev/mtd0"
+CONFIG_EXAMPLES_MEDIA_BLOCKSIZE=512
 # CONFIG_EXAMPLES_MM is not set
 # CONFIG_EXAMPLES_MODBUS is not set
 # CONFIG_EXAMPLES_MOUNT is not set
@@ -823,6 +900,7 @@ CONFIG_EXAMPLES_NSAMPLES=8
 # CONFIG_EXAMPLES_TIFF is not set
 # CONFIG_EXAMPLES_TOUCHSCREEN is not set
 # CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
 # CONFIG_EXAMPLES_USBTERM is not set
 # CONFIG_EXAMPLES_WATCHDOG is not set
 
@@ -830,6 +908,7 @@ CONFIG_EXAMPLES_NSAMPLES=8
 # File System Utilities
 #
 # CONFIG_FSUTILS_INIFILE is not set
+# CONFIG_FSUTILS_PASSWD is not set
 
 #
 # GPS Utilities
@@ -845,6 +924,7 @@ CONFIG_EXAMPLES_NSAMPLES=8
 #
 # Interpreters
 #
+# CONFIG_INTERPRETERS_BAS is not set
 # CONFIG_INTERPRETERS_FICL is not set
 # CONFIG_INTERPRETERS_PCODE is not set
 # CONFIG_INTERPRETERS_MICROPYTHON is not set
@@ -911,6 +991,7 @@ CONFIG_NSH_DISABLE_LOSMART=y
 # CONFIG_NSH_DISABLE_LS is not set
 # CONFIG_NSH_DISABLE_MB is not set
 # CONFIG_NSH_DISABLE_MKDIR is not set
+# CONFIG_NSH_DISABLE_MKFATFS is not set
 # CONFIG_NSH_DISABLE_MKFIFO is not set
 # CONFIG_NSH_DISABLE_MKRD is not set
 # CONFIG_NSH_DISABLE_MH is not set
@@ -940,6 +1021,7 @@ CONFIG_NSH_DISABLE_LOSMART=y
 # CONFIG_NSH_CMDOPT_DF_H is not set
 CONFIG_NSH_CODECS_BUFSIZE=128
 # CONFIG_NSH_CMDOPT_HEXDUMP is not set
+CONFIG_NSH_PROC_MOUNTPOINT="/proc"
 CONFIG_NSH_FILEIOSIZE=512
 
 #
@@ -954,7 +1036,7 @@ CONFIG_NSH_FILEIOSIZE=512
 #
 CONFIG_NSH_CONSOLE=y
 # CONFIG_NSH_ALTCONDEV is not set
-# CONFIG_NSH_ARCHINIT is not set
+CONFIG_NSH_ARCHINIT=y
 # CONFIG_NSH_LOGIN is not set
 # CONFIG_NSH_CONSOLE_LOGIN is not set
 
@@ -974,6 +1056,7 @@ CONFIG_NSH_CONSOLE=y
 # CONFIG_SYSTEM_CLE is not set
 # CONFIG_SYSTEM_CUTERM is not set
 # CONFIG_SYSTEM_INSTALL is not set
+# CONFIG_SYSTEM_FLASH_ERASEALL is not set
 # CONFIG_SYSTEM_HEX2BIN is not set
 # CONFIG_SYSTEM_HEXED is not set
 # CONFIG_SYSTEM_RAMTEST is not set

configs/stm32l476vg-disco/src/stm32_appinit.c

@@ -39,9 +39,12 @@
 
 #include <nuttx/config.h>
 
+#include <sys/types.h>
+#include <sys/mount.h>
 #include <stdio.h>
 #include <syslog.h>
 #include <errno.h>
+#include <debug.h>
 
 #include <nuttx/arch.h>
 #include <nuttx/board.h>
@@ -51,8 +54,45 @@
 
 #include <arch/board/board.h>
 
+#include <nuttx/fs/fs.h>
+#include <nuttx/fs/ramdisk.h>
+#include <nuttx/fs/nxffs.h>
+#include <nuttx/binfmt/elf.h>
+#include <nuttx/i2c/i2c_master.h>
+
 #include "stm32l476vg-disco.h"
 
+/* Conditional logic in stm32l476vg-disco.h will determine if certain features
+ * are supported.  Tests for these features need to be made after including
+ * stm32l476vg-disco.h.
+ */
+
+#ifdef HAVE_RTC_DRIVER
+#  include <nuttx/timers/rtc.h>
+#  include "stm32l4_rtc.h"
+#endif
+
+#if defined(HAVE_N25QXXX) || defined(HAVE_PROGMEM_CHARDEV)
+#  include <nuttx/mtd/mtd.h>
+#endif
+
+#ifdef HAVE_N25QXXX
+#  include <nuttx/spi/qspi.h>
+#  include "stm32l4_qspi.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Debug ********************************************************************/
+
+#ifdef CONFIG_BOARD_INITIALIZE
+#  define SYSLOG lldbg
+#else
+#  define SYSLOG dbg
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -61,17 +101,159 @@
  * Name: board_app_initialize
  *
  * Description:
- *   Perform architecture specific initialization
+ *   Application initialization stub for boardctl()
  *
  ****************************************************************************/
 
+#ifdef CONFIG_LIB_BOARDCTL
 int board_app_initialize(void)
 {
+#ifdef HAVE_RTC_DRIVER
+  FAR struct rtc_lowerhalf_s *lower;
+#endif
+#ifdef HAVE_N25QXXX
+  FAR struct qspi_dev_s *qspi;
+#endif
+#if defined(HAVE_N25QXXX) || defined(HAVE_PROGMEM_CHARDEV)
+  FAR struct mtd_dev_s *mtd;
+#endif
+#if defined(HAVE_N25QXXX_CHARDEV) || defined(HAVE_PROGMEM_CHARDEV)
+  char blockdev[18];
+  char chardev[12];
+#endif
+  int ret;
+
+  (void)ret;
+  
   /* Configure CPU load estimation */
 
 #ifdef CONFIG_SCHED_INSTRUMENTATION
   cpuload_initialize_once();
 #endif
 
+#ifdef HAVE_PROC
+  /* mount the proc filesystem */
+
+  syslog(LOG_INFO, "Mounting procfs to /proc\n");
+
+  ret = mount(NULL, CONFIG_NSH_PROC_MOUNTPOINT, "procfs", 0, NULL);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to mount the PROC filesystem: %d (%d)\n",
+             ret, errno);
+      return ret;
+    }
+#endif
+
+#ifdef HAVE_RTC_DRIVER
+  /* Instantiate the STM32 lower-half RTC driver */
+
+  lower = stm32l4_rtc_lowerhalf();
+  if (!lower)
+    {
+      sdbg("ERROR: Failed to instantiate the RTC lower-half driver\n");
+      return -ENOMEM;
+    }
+  else
+    {
+      /* Bind the lower half driver and register the combined RTC driver
+       * as /dev/rtc0
+       */
+
+      ret = rtc_initialize(0, lower);
+      if (ret < 0)
+        {
+          sdbg("ERROR: Failed to bind/register the RTC driver: %d\n", ret);
+          return ret;
+        }
+    }
+#endif
+
+#ifdef HAVE_N25QXXX
+  /* Create an instance of the STM32L4 QSPI device driver */
+
+  qspi = stm32l4_qspi_initialize(0);
+  if (!qspi)
+    {
+      SYSLOG("ERROR: sam_qspi_initialize failed\n");
+    }
+  else
+    {
+      /* Use the QSPI device instance to initialize the
+       * N25QXXX device.
+       */
+
+      mtd = n25qxxx_initialize(qspi, true);
+      if (!mtd)
+        {
+          SYSLOG("ERROR: n25qxxx_initialize failed\n");
+        }
+
+#ifdef HAVE_N25QXXX_SMARTFS
+      /* Configure the device with no partition support */
+
+      ret = smart_initialize(N25QXXX_SMART_MINOR, mtd, NULL);
+      if (ret != OK)
+        {
+          SYSLOG("ERROR: Failed to initialize SmartFS: %d\n", ret);
+        }
+
+#elif defined(HAVE_N25QXXX_NXFFS)
+      /* Initialize to provide NXFFS on the N25QXXX MTD interface */
+
+      ret = nxffs_initialize(mtd);
+      if (ret < 0)
+        {
+         SYSLOG("ERROR: NXFFS initialization failed: %d\n", ret);
+        }
+
+      /* Mount the file system at /mnt/n25qxxx */
+
+      ret = mount(NULL, "/mnt/n25qxxx", "nxffs", 0, NULL);
+      if (ret < 0)
+        {
+          SYSLOG("ERROR: Failed to mount the NXFFS volume: %d\n", errno);
+          return ret;
+        }
+
+#else /* if  defined(HAVE_N25QXXX_CHARDEV) */
+      /* Use the FTL layer to wrap the MTD driver as a block driver */
+
+      ret = ftl_initialize(N25QXXX_MTD_MINOR, mtd);
+      if (ret < 0)
+        {
+          SYSLOG("ERROR: Failed to initialize the FTL layer: %d\n", ret);
+          return ret;
+        }
+
+      /* Use the minor number to create device paths */
+
+      snprintf(blockdev, 18, "/dev/mtdblock%d", N25QXXX_MTD_MINOR);
+      snprintf(chardev, 12, "/dev/mtd%d", N25QXXX_MTD_MINOR);
+
+      /* Now create a character device on the block device */
+
+      /* NOTE:  for this to work, you will need to make sure that
+       * CONFIG_FS_WRITABLE is set in the config.  It's not a user-
+       * visible setting, but you can make it set by selecting an
+       * arbitrary writeable file system (you don't have to actually
+       * use it, just select it so that the block device created via
+       * ftl_initialize() will be writeable).  Personally, I chose FAT,
+       * because SMARTFS and NXFFS will cause the other code branches
+       * above to become active.
+       */
+
+      ret = bchdev_register(blockdev, chardev, false);
+      if (ret < 0)
+        {
+          SYSLOG("ERROR: bchdev_register %s failed: %d\n", chardev, ret);
+          return ret;
+        }
+#endif
+    }
+#endif
+
   return OK;
 }
+#endif /* CONFIG_LIB_BOARDCTL */

configs/stm32l476vg-disco/src/stm32l476vg-disco.h

@@ -53,6 +53,84 @@
  ************************************************************************************/
 /* Configuration ********************************************************************/
 
+#define HAVE_PROC             1
+#define HAVE_RTC_DRIVER       1
+#define HAVE_N25QXXX          1
+#define HAVE_N25QXXX_NXFFS    1
+#define HAVE_N25QXXX_SMARTFS  1
+#define HAVE_N25QXXX_CHARDEV  1
+#define HAVE_PROGMEM_CHARDEV  1
+
+#if !defined(CONFIG_FS_PROCFS)
+#  undef HAVE_PROC
+#endif
+
+#if defined(HAVE_PROC) && defined(CONFIG_DISABLE_MOUNTPOINT)
+#  warning Mountpoints disabled.  No procfs support
+#  undef HAVE_PROC
+#endif
+
+/* Check if we can support the RTC driver */
+
+#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER)
+#  undef HAVE_RTC_DRIVER
+#endif
+
+/* N25QXXX QuadSPI FLASH */
+
+#ifndef CONFIG_MTD_N25QXXX
+#  undef HAVE_N25QXXX
+#  undef HAVE_N25QXXX_NXFFS
+#  undef HAVE_N25QXXX_SMARTFS
+#  undef HAVE_N25QXXX_CHARDEV
+#endif
+
+#ifndef CONFIG_STM32L4_QSPI
+#  undef HAVE_N25QXXX
+#  undef HAVE_N25QXXX_NXFFS
+#  undef HAVE_N25QXXX_SMARTFS
+#  undef HAVE_N25QXXX_CHARDEV
+#endif
+
+#ifndef CONFIG_FS_NXFFS
+#  undef HAVE_N25QXXX_NXFFS
+#endif
+
+#if !defined(CONFIG_MTD_SMART) || !defined(CONFIG_FS_SMARTFS)
+#  undef HAVE_N25QXXX_SMARTFS
+#endif
+
+#if defined(HAVE_N25QXXX_NXFFS) && defined(HAVE_N25QXXX_SMARTFS)
+#  undef HAVE_N25QXXX_NXFFS
+#endif
+
+#if defined(HAVE_N25QXXX_NXFFS) || defined(HAVE_N25QXXX_SMARTFS)
+#  undef HAVE_N25QXXX_CHARDEV
+#endif
+
+/* On-chip Programming Memory */
+
+#if !defined(CONFIG_STM32L4_PROGMEM) || !defined(CONFIG_MTD_PROGMEM)
+#  undef HAVE_PROGMEM_CHARDEV
+#endif
+
+/* If both the N25QXXX FLASH and SmartFS, then this is the minor device
+ * number of the Smart block driver (/dev/smartN)
+ */
+
+#define N25QXXX_SMART_MINOR 0
+
+/* If the N25QXXX FLASH is enabled but not SmartFS, then the N25QXXX will be
+ * wrapped as a character device.  This is the minor number of both the
+ * block device (/dev/mtdblockN) and the character device (/dev/mtdN).
+ */
+
+#define N25QXXX_MTD_MINOR 0
+
+/* This is the on-chip progmem memroy driver minor number */
+
+#define PROGMEM_MTD_MINOR 1
+
 /* LED.
  * LD4: the red LED on PB2
  * LD5: the green LED on PE8
@@ -110,7 +188,7 @@
 
 /* XXX IS this 'unshifted'? */
 
-#define NUCLEO_I2C_OBDEV_CS43L22   0x94
+#define DISCO_I2C_OBDEV_CS43L22   0x94
 
 /************************************************************************************
  * Public Data