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SAMA5: Rename most EMAC definitions to EMAC0 to handle the SAMA5D4 which has to EMAC modules and no GMAC

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This commit is contained in:
Gregory Nutt
2014-06-04 12:04:24 -06:00
parent dad0da617a
commit 495b190e50
23 changed files with 609 additions and 367 deletions
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arch/arm/src/sama5/Kconfig
+277 -82
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File diff suppressed because it is too large Load Diff
arch/arm/src/sama5/Make.defs
+1 -1
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@@ -190,7 +190,7 @@ endif
ifeq ($(CONFIG_NET),y)
CHIP_CSRCS += sam_ethernet.c
ifeq ($(CONFIG_SAMA5_EMAC),y)
ifeq ($(CONFIG_SAMA5_EMAC0),y)
CHIP_CSRCS += sam_emac.c
endif
ifeq ($(CONFIG_SAMA5_GMAC),y)
arch/arm/src/sama5/chip/sam_emac.h
+93 -46
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@@ -99,52 +99,99 @@
/* EMAC Register Addresses **********************************************************/
#define SAM_EMAC_NCR (SAM_EMAC_VBASE+SAM_EMAC_NCR_OFFSET)
#define SAM_EMAC_NCFGR (SAM_EMAC_VBASE+SAM_EMAC_NCFGR_OFFSET)
#define SAM_EMAC_NSR (SAM_EMAC_VBASE+SAM_EMAC_NSR_OFFSET)
#define SAM_EMAC_TSR (SAM_EMAC_VBASE+SAM_EMAC_TSR_OFFSET)
#define SAM_EMAC_RBQP (SAM_EMAC_VBASE+SAM_EMAC_RBQP_OFFSET)
#define SAM_EMAC_TBQP (SAM_EMAC_VBASE+SAM_EMAC_TBQP_OFFSET)
#define SAM_EMAC_RSR (SAM_EMAC_VBASE+SAM_EMAC_RSR_OFFSET)
#define SAM_EMAC_ISR (SAM_EMAC_VBASE+SAM_EMAC_ISR_OFFSET)
#define SAM_EMAC_IER (SAM_EMAC_VBASE+SAM_EMAC_IER_OFFSET)
#define SAM_EMAC_IDR (SAM_EMAC_VBASE+SAM_EMAC_IDR_OFFSET)
#define SAM_EMAC_IMR (SAM_EMAC_VBASE+SAM_EMAC_IMR_OFFSET)
#define SAM_EMAC_MAN (SAM_EMAC_VBASE+SAM_EMAC_MAN_OFFSET)
#define SAM_EMAC_PTR (SAM_EMAC_VBASE+SAM_EMAC_PTR_OFFSET)
#define SAM_EMAC_PFR (SAM_EMAC_VBASE+SAM_EMAC_PFR_OFFSET)
#define SAM_EMAC_FTO (SAM_EMAC_VBASE+SAM_EMAC_FTO_OFFSET)
#define SAM_EMAC_SCF (SAM_EMAC_VBASE+SAM_EMAC_SCF_OFFSET)
#define SAM_EMAC_MCF (SAM_EMAC_VBASE+SAM_EMAC_MCF_OFFSET)
#define SAM_EMAC_FRO (SAM_EMAC_VBASE+SAM_EMAC_FRO_OFFSET)
#define SAM_EMAC_FCSE (SAM_EMAC_VBASE+SAM_EMAC_FCSE_OFFSET)
#define SAM_EMAC_ALE (SAM_EMAC_VBASE+SAM_EMAC_ALE_OFFSET)
#define SAM_EMAC_DTF (SAM_EMAC_VBASE+SAM_EMAC_DTF_OFFSET)
#define SAM_EMAC_LCOL (SAM_EMAC_VBASE+SAM_EMAC_LCOL_OFFSET)
#define SAM_EMAC_ECOL (SAM_EMAC_VBASE+SAM_EMAC_ECOL_OFFSET)
#define SAM_EMAC_TUND (SAM_EMAC_VBASE+SAM_EMAC_TUND_OFFSET)
#define SAM_EMAC_CSE (SAM_EMAC_VBASE+SAM_EMAC_CSE_OFFSET)
#define SAM_EMAC_RRE (SAM_EMAC_VBASE+SAM_EMAC_RRE_OFFSET)
#define SAM_EMAC_ROV (SAM_EMAC_VBASE+SAM_EMAC_ROV_OFFSET)
#define SAM_EMAC_RSE (SAM_EMAC_VBASE+SAM_EMAC_RSE_OFFSET)
#define SAM_EMAC_ELE (SAM_EMAC_VBASE+SAM_EMAC_ELE_OFFSET)
#define SAM_EMAC_RJA (SAM_EMAC_VBASE+SAM_EMAC_RJA_OFFSET)
#define SAM_EMAC_USF (SAM_EMAC_VBASE+SAM_EMAC_USF_OFFSET)
#define SAM_EMAC_STE (SAM_EMAC_VBASE+SAM_EMAC_STE_OFFSET)
#define SAM_EMAC_RLE (SAM_EMAC_VBASE+SAM_EMAC_RLE_OFFSET)
#define SAM_EMAC_HRB (SAM_EMAC_VBASE+SAM_EMAC_HRB_OFFSET)
#define SAM_EMAC_HRT (SAM_EMAC_VBASE+SAM_EMAC_HRT_OFFSET)
#define SAM_EMAC_SA1B (SAM_EMAC_VBASE+SAM_EMAC_SA1B_OFFSET)
#define SAM_EMAC_SA1T (SAM_EMAC_VBASE+SAM_EMAC_SA1T_OFFSET)
#define SAM_EMAC_SA2B (SAM_EMAC_VBASE+SAM_EMAC_SA2B_OFFSET)
#define SAM_EMAC_SA2T (SAM_EMAC_VBASE+SAM_EMAC_SA2T_OFFSET)
#define SAM_EMAC_SA3B (SAM_EMAC_VBASE+SAM_EMAC_SA3B_OFFSET)
#define SAM_EMAC_SA3T (SAM_EMAC_VBASE+SAM_EMAC_SA3T_OFFSET)
#define SAM_EMAC_SA4B (SAM_EMAC_VBASE+SAM_EMAC_SA4B_OFFSET)
#define SAM_EMAC_SA4T (SAM_EMAC_VBASE+SAM_EMAC_SA4T_OFFSET)
#define SAM_EMAC_TID (SAM_EMAC_VBASE+SAM_EMAC_TID_OFFSET)
#define SAM_EMAC_USRIO (SAM_EMAC_VBASE+SAM_EMAC_USRIO_OFFSET)
#define SAM_EMAC_WOL (SAM_EMAC_VBASE+SAM_EMAC_WOL_OFFSET)
#define SAM_EMAC0_NCR (SAM_EMAC0_VBASE+SAM_EMAC_NCR_OFFSET)
#define SAM_EMAC0_NCFGR (SAM_EMAC0_VBASE+SAM_EMAC_NCFGR_OFFSET)
#define SAM_EMAC0_NSR (SAM_EMAC0_VBASE+SAM_EMAC_NSR_OFFSET)
#define SAM_EMAC0_TSR (SAM_EMAC0_VBASE+SAM_EMAC_TSR_OFFSET)
#define SAM_EMAC0_RBQP (SAM_EMAC0_VBASE+SAM_EMAC_RBQP_OFFSET)
#define SAM_EMAC0_TBQP (SAM_EMAC0_VBASE+SAM_EMAC_TBQP_OFFSET)
#define SAM_EMAC0_RSR (SAM_EMAC0_VBASE+SAM_EMAC_RSR_OFFSET)
#define SAM_EMAC0_ISR (SAM_EMAC0_VBASE+SAM_EMAC_ISR_OFFSET)
#define SAM_EMAC0_IER (SAM_EMAC0_VBASE+SAM_EMAC_IER_OFFSET)
#define SAM_EMAC0_IDR (SAM_EMAC0_VBASE+SAM_EMAC_IDR_OFFSET)
#define SAM_EMAC0_IMR (SAM_EMAC0_VBASE+SAM_EMAC_IMR_OFFSET)
#define SAM_EMAC0_MAN (SAM_EMAC0_VBASE+SAM_EMAC_MAN_OFFSET)
#define SAM_EMAC0_PTR (SAM_EMAC0_VBASE+SAM_EMAC_PTR_OFFSET)
#define SAM_EMAC0_PFR (SAM_EMAC0_VBASE+SAM_EMAC_PFR_OFFSET)
#define SAM_EMAC0_FTO (SAM_EMAC0_VBASE+SAM_EMAC_FTO_OFFSET)
#define SAM_EMAC0_SCF (SAM_EMAC0_VBASE+SAM_EMAC_SCF_OFFSET)
#define SAM_EMAC0_MCF (SAM_EMAC0_VBASE+SAM_EMAC_MCF_OFFSET)
#define SAM_EMAC0_FRO (SAM_EMAC0_VBASE+SAM_EMAC_FRO_OFFSET)
#define SAM_EMAC0_FCSE (SAM_EMAC0_VBASE+SAM_EMAC_FCSE_OFFSET)
#define SAM_EMAC0_ALE (SAM_EMAC0_VBASE+SAM_EMAC_ALE_OFFSET)
#define SAM_EMAC0_DTF (SAM_EMAC0_VBASE+SAM_EMAC_DTF_OFFSET)
#define SAM_EMAC0_LCOL (SAM_EMAC0_VBASE+SAM_EMAC_LCOL_OFFSET)
#define SAM_EMAC0_ECOL (SAM_EMAC0_VBASE+SAM_EMAC_ECOL_OFFSET)
#define SAM_EMAC0_TUND (SAM_EMAC0_VBASE+SAM_EMAC_TUND_OFFSET)
#define SAM_EMAC0_CSE (SAM_EMAC0_VBASE+SAM_EMAC_CSE_OFFSET)
#define SAM_EMAC0_RRE (SAM_EMAC0_VBASE+SAM_EMAC_RRE_OFFSET)
#define SAM_EMAC0_ROV (SAM_EMAC0_VBASE+SAM_EMAC_ROV_OFFSET)
#define SAM_EMAC0_RSE (SAM_EMAC0_VBASE+SAM_EMAC_RSE_OFFSET)
#define SAM_EMAC0_ELE (SAM_EMAC0_VBASE+SAM_EMAC_ELE_OFFSET)
#define SAM_EMAC0_RJA (SAM_EMAC0_VBASE+SAM_EMAC_RJA_OFFSET)
#define SAM_EMAC0_USF (SAM_EMAC0_VBASE+SAM_EMAC_USF_OFFSET)
#define SAM_EMAC0_STE (SAM_EMAC0_VBASE+SAM_EMAC_STE_OFFSET)
#define SAM_EMAC0_RLE (SAM_EMAC0_VBASE+SAM_EMAC_RLE_OFFSET)
#define SAM_EMAC0_HRB (SAM_EMAC0_VBASE+SAM_EMAC_HRB_OFFSET)
#define SAM_EMAC0_HRT (SAM_EMAC0_VBASE+SAM_EMAC_HRT_OFFSET)
#define SAM_EMAC0_SA1B (SAM_EMAC0_VBASE+SAM_EMAC_SA1B_OFFSET)
#define SAM_EMAC0_SA1T (SAM_EMAC0_VBASE+SAM_EMAC_SA1T_OFFSET)
#define SAM_EMAC0_SA2B (SAM_EMAC0_VBASE+SAM_EMAC_SA2B_OFFSET)
#define SAM_EMAC0_SA2T (SAM_EMAC0_VBASE+SAM_EMAC_SA2T_OFFSET)
#define SAM_EMAC0_SA3B (SAM_EMAC0_VBASE+SAM_EMAC_SA3B_OFFSET)
#define SAM_EMAC0_SA3T (SAM_EMAC0_VBASE+SAM_EMAC_SA3T_OFFSET)
#define SAM_EMAC0_SA4B (SAM_EMAC0_VBASE+SAM_EMAC_SA4B_OFFSET)
#define SAM_EMAC0_SA4T (SAM_EMAC0_VBASE+SAM_EMAC_SA4T_OFFSET)
#define SAM_EMAC0_TID (SAM_EMAC0_VBASE+SAM_EMAC_TID_OFFSET)
#define SAM_EMAC0_USRIO (SAM_EMAC0_VBASE+SAM_EMAC_USRIO_OFFSET)
#define SAM_EMAC0_WOL (SAM_EMAC0_VBASE+SAM_EMAC_WOL_OFFSET)
#define SAM_EMAC1_NCR (SAM_EMAC1_VBASE+SAM_EMAC_NCR_OFFSET)
#define SAM_EMAC1_NCFGR (SAM_EMAC1_VBASE+SAM_EMAC_NCFGR_OFFSET)
#define SAM_EMAC1_NSR (SAM_EMAC1_VBASE+SAM_EMAC_NSR_OFFSET)
#define SAM_EMAC1_TSR (SAM_EMAC1_VBASE+SAM_EMAC_TSR_OFFSET)
#define SAM_EMAC1_RBQP (SAM_EMAC1_VBASE+SAM_EMAC_RBQP_OFFSET)
#define SAM_EMAC1_TBQP (SAM_EMAC1_VBASE+SAM_EMAC_TBQP_OFFSET)
#define SAM_EMAC1_RSR (SAM_EMAC1_VBASE+SAM_EMAC_RSR_OFFSET)
#define SAM_EMAC1_ISR (SAM_EMAC1_VBASE+SAM_EMAC_ISR_OFFSET)
#define SAM_EMAC1_IER (SAM_EMAC1_VBASE+SAM_EMAC_IER_OFFSET)
#define SAM_EMAC1_IDR (SAM_EMAC1_VBASE+SAM_EMAC_IDR_OFFSET)
#define SAM_EMAC1_IMR (SAM_EMAC1_VBASE+SAM_EMAC_IMR_OFFSET)
#define SAM_EMAC1_MAN (SAM_EMAC1_VBASE+SAM_EMAC_MAN_OFFSET)
#define SAM_EMAC1_PTR (SAM_EMAC1_VBASE+SAM_EMAC_PTR_OFFSET)
#define SAM_EMAC1_PFR (SAM_EMAC1_VBASE+SAM_EMAC_PFR_OFFSET)
#define SAM_EMAC1_FTO (SAM_EMAC1_VBASE+SAM_EMAC_FTO_OFFSET)
#define SAM_EMAC1_SCF (SAM_EMAC1_VBASE+SAM_EMAC_SCF_OFFSET)
#define SAM_EMAC1_MCF (SAM_EMAC1_VBASE+SAM_EMAC_MCF_OFFSET)
#define SAM_EMAC1_FRO (SAM_EMAC1_VBASE+SAM_EMAC_FRO_OFFSET)
#define SAM_EMAC1_FCSE (SAM_EMAC1_VBASE+SAM_EMAC_FCSE_OFFSET)
#define SAM_EMAC1_ALE (SAM_EMAC1_VBASE+SAM_EMAC_ALE_OFFSET)
#define SAM_EMAC1_DTF (SAM_EMAC1_VBASE+SAM_EMAC_DTF_OFFSET)
#define SAM_EMAC1_LCOL (SAM_EMAC1_VBASE+SAM_EMAC_LCOL_OFFSET)
#define SAM_EMAC1_ECOL (SAM_EMAC1_VBASE+SAM_EMAC_ECOL_OFFSET)
#define SAM_EMAC1_TUND (SAM_EMAC1_VBASE+SAM_EMAC_TUND_OFFSET)
#define SAM_EMAC1_CSE (SAM_EMAC1_VBASE+SAM_EMAC_CSE_OFFSET)
#define SAM_EMAC1_RRE (SAM_EMAC1_VBASE+SAM_EMAC_RRE_OFFSET)
#define SAM_EMAC1_ROV (SAM_EMAC1_VBASE+SAM_EMAC_ROV_OFFSET)
#define SAM_EMAC1_RSE (SAM_EMAC1_VBASE+SAM_EMAC_RSE_OFFSET)
#define SAM_EMAC1_ELE (SAM_EMAC1_VBASE+SAM_EMAC_ELE_OFFSET)
#define SAM_EMAC1_RJA (SAM_EMAC1_VBASE+SAM_EMAC_RJA_OFFSET)
#define SAM_EMAC1_USF (SAM_EMAC1_VBASE+SAM_EMAC_USF_OFFSET)
#define SAM_EMAC1_STE (SAM_EMAC1_VBASE+SAM_EMAC_STE_OFFSET)
#define SAM_EMAC1_RLE (SAM_EMAC1_VBASE+SAM_EMAC_RLE_OFFSET)
#define SAM_EMAC1_HRB (SAM_EMAC1_VBASE+SAM_EMAC_HRB_OFFSET)
#define SAM_EMAC1_HRT (SAM_EMAC1_VBASE+SAM_EMAC_HRT_OFFSET)
#define SAM_EMAC1_SA1B (SAM_EMAC1_VBASE+SAM_EMAC_SA1B_OFFSET)
#define SAM_EMAC1_SA1T (SAM_EMAC1_VBASE+SAM_EMAC_SA1T_OFFSET)
#define SAM_EMAC1_SA2B (SAM_EMAC1_VBASE+SAM_EMAC_SA2B_OFFSET)
#define SAM_EMAC1_SA2T (SAM_EMAC1_VBASE+SAM_EMAC_SA2T_OFFSET)
#define SAM_EMAC1_SA3B (SAM_EMAC1_VBASE+SAM_EMAC_SA3B_OFFSET)
#define SAM_EMAC1_SA3T (SAM_EMAC1_VBASE+SAM_EMAC_SA3T_OFFSET)
#define SAM_EMAC1_SA4B (SAM_EMAC1_VBASE+SAM_EMAC_SA4B_OFFSET)
#define SAM_EMAC1_SA4T (SAM_EMAC1_VBASE+SAM_EMAC_SA4T_OFFSET)
#define SAM_EMAC1_TID (SAM_EMAC1_VBASE+SAM_EMAC_TID_OFFSET)
#define SAM_EMAC1_USRIO (SAM_EMAC1_VBASE+SAM_EMAC_USRIO_OFFSET)
#define SAM_EMAC1_WOL (SAM_EMAC1_VBASE+SAM_EMAC_WOL_OFFSET)
/* EMAC Register Bit Definitions ****************************************************/
arch/arm/src/sama5/chip/sama5d3x_memorymap.h
+2 -2
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@@ -129,7 +129,7 @@
# define SAM_USART2_OFFSET 0x00020000 /* 0x00020000-0x00023fff: USART2 */
# define SAM_USART3_OFFSET 0x00024000 /* 0x00024000-0x00027fff: USART3 */
# define SAM_UART1_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: UART1 */
# define SAM_EMAC_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: EMAC */
# define SAM_EMAC0_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: EMAC */
# define SAM_UDPHS_OFFSET 0x00030000 /* 0x00030000-0x00033fff: UDPHS */
# define SAM_SHA_OFFSET 0x00034000 /* 0x00034000-0x00037fff: SHA */
# define SAM_AES_OFFSET 0x00038000 /* 0x00038000-0x0003bfff: AES */
@@ -414,7 +414,7 @@
#define SAM_USART2_VBASE (SAM_PERIPHB_VSECTION+SAM_USART2_OFFSET)
#define SAM_USART3_VBASE (SAM_PERIPHB_VSECTION+SAM_USART3_OFFSET)
#define SAM_UART1_VBASE (SAM_PERIPHB_VSECTION+SAM_UART1_OFFSET)
#define SAM_EMAC_VBASE (SAM_PERIPHB_VSECTION+SAM_EMAC_OFFSET)
#define SAM_EMAC0_VBASE (SAM_PERIPHB_VSECTION+SAM_EMAC0_OFFSET)
#define SAM_UDPHS_VBASE (SAM_PERIPHB_VSECTION+SAM_UDPHS_OFFSET)
#define SAM_SHA_VBASE (SAM_PERIPHB_VSECTION+SAM_SHA_OFFSET)
#define SAM_AES_VBASE (SAM_PERIPHB_VSECTION+SAM_AES_OFFSET)
arch/arm/src/sama5/chip/sama5d3x_pinmap.h
+10 -10
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@@ -133,16 +133,16 @@
/* RMII Ethernet 10/100 - EMAC */
#define PIO_EMAC_CRSDV (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN5) /* Type: GPIO */
#define PIO_EMAC_MDC (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN8) /* Type: GPIO */
#define PIO_EMAC_MDIO (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN9) /* Type: GPIO */
#define PIO_EMAC_REFCK (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN7) /* Type: GPIO */
#define PIO_EMAC_RX0 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN2) /* Type: GPIO */
#define PIO_EMAC_RX1 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN3) /* Type: GPIO */
#define PIO_EMAC_RXER (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN6) /* Type: GPIO */
#define PIO_EMAC_TX0 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN0) /* Type: GPIO */
#define PIO_EMAC_TX1 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN1) /* Type: GPIO */
#define PIO_EMAC_TXEN (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN4) /* Type: GPIO */
#define PIO_EMAC0_CRSDV (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN5) /* Type: GPIO */
#define PIO_EMAC0_MDC (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN8) /* Type: GPIO */
#define PIO_EMAC0_MDIO (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN9) /* Type: GPIO */
#define PIO_EMAC0_REFCK (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN7) /* Type: GPIO */
#define PIO_EMAC0_RX0 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN2) /* Type: GPIO */
#define PIO_EMAC0_RX1 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN3) /* Type: GPIO */
#define PIO_EMAC0_RXER (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN6) /* Type: GPIO */
#define PIO_EMAC0_TX0 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN0) /* Type: GPIO */
#define PIO_EMAC0_TX1 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN1) /* Type: GPIO */
#define PIO_EMAC0_TXEN (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN4) /* Type: GPIO */
/* GIgabit Ethernet 10/100/1000 - GMAC */
arch/arm/src/sama5/chip/sama5d4x_memorymap.h
+4 -4
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@@ -121,7 +121,7 @@
# define SAM_TWI0_OFFSET 0x00014000 /* 0x00014000-0x00017fff: TWI0 */
# define SAM_TWI1_OFFSET 0x00018000 /* 0x00018000-0x0001bfff: TWI1 */
# define SAM_TC012_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: TC channels 0, 1, and 2 */
# define SAM_GMAC0_OFFSET 0x00020000 /* 0x00020000-0x00023fff: GMAC */
# define SAM_EMAC0_OFFSET 0x00020000 /* 0x00020000-0x00023fff: GMAC 0 */
# define SAM_TWI2_OFFSET 0x00024000 /* 0x00024000-0x00027fff: TWI2 */
# define SAM_SFR_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: SFR */
# define SAM_USART0_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: USART0 */
@@ -139,7 +139,7 @@
# define SAM_SPI2_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: SPI2 */
# define SAM_TC345_OFFSET 0x00020000 /* 0x00020000-0x00023fff: TC channels 3, 4, and 5 */
# define SAM_TC678_OFFSET 0x00024000 /* 0x00024000-0x00027fff: TC channels 6, 7, and 8 */
# define SAM_GMAC1_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: GMAC */
# define SAM_EMAC1_OFFSET 0x00028000 /* 0x00028000-0x0002bfff: GMAC 1 */
# define SAM_UDPHS_OFFSET 0x0002c000 /* 0x0002c000-0x0002ffff: UDPHS */
# define SAM_TRNG_OFFSET 0x00030000 /* 0x00030000-0x0003efff: TRNG */
# define SAM_ADC_OFFSET 0x00034000 /* 0x00034000-0x00037fff: ADC */
@@ -390,7 +390,7 @@
#define SAM_TWI0_VBASE (SAM_PERIPHB_VSECTION+SAM_TWI0_OFFSET)
#define SAM_TWI1_VBASE (SAM_PERIPHB_VSECTION+SAM_TWI1_OFFSET)
#define SAM_TC012_VBASE (SAM_PERIPHB_VSECTION+SAM_TC012_OFFSET)
#define SAM_GMAC0_VBASE (SAM_PERIPHB_VSECTION+SAM_GMAC0_OFFSET)
#define SAM_EMAC0_VBASE (SAM_PERIPHB_VSECTION+SAM_EMAC0_OFFSET)
#define SAM_TWI2_VBASE (SAM_PERIPHB_VSECTION+SAM_TWI2_OFFSET)
#define SAM_SFR_VBASE (SAM_PERIPHB_VSECTION+SAM_SFR_OFFSET)
#define SAM_USART0_VBASE (SAM_PERIPHB_VSECTION+SAM_USART0_OFFSET)
@@ -407,7 +407,7 @@
#define SAM_SPI2_VBASE (SAM_PERIPHC_VSECTION+SAM_SPI2_OFFSET)
#define SAM_TC345_VBASE (SAM_PERIPHC_VSECTION+SAM_TC345_OFFSET)
#define SAM_TC678_VBASE (SAM_PERIPHC_VSECTION+SAM_TC678_OFFSET)
#define SAM_GMAC1_VBASE (SAM_PERIPHC_VSECTION+SAM_GMAC1_OFFSET)
#define SAM_EMAC1_VBASE (SAM_PERIPHC_VSECTION+SAM_EMAC1_OFFSET)
#define SAM_UDPHS_VBASE (SAM_PERIPHC_VSECTION+SAM_UDPHS_OFFSET)
#define SAM_TRNG_VBASE (SAM_PERIPHC_VSECTION+SAM_TRNG_OFFSET)
#define SAM_ADC_VBASE (SAM_PERIPHC_VSECTION+SAM_ADC_OFFSET)
arch/arm/src/sama5/chip/sama5d4x_pinmap.h
+10 -10
View File
@@ -135,16 +135,16 @@
/* RMII Ethernet 10/100 - EMAC */
#define PIO_EMAC_CRSDV (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN5) /* Type: GPIO */
#define PIO_EMAC_MDC (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN8) /* Type: GPIO */
#define PIO_EMAC_MDIO (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN9) /* Type: GPIO */
#define PIO_EMAC_REFCK (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN7) /* Type: GPIO */
#define PIO_EMAC_RX0 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN2) /* Type: GPIO */
#define PIO_EMAC_RX1 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN3) /* Type: GPIO */
#define PIO_EMAC_RXER (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN6) /* Type: GPIO */
#define PIO_EMAC_TX0 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN0) /* Type: GPIO */
#define PIO_EMAC_TX1 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN1) /* Type: GPIO */
#define PIO_EMAC_TXEN (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN4) /* Type: GPIO */
#define PIO_EMAC0_CRSDV (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN5) /* Type: GPIO */
#define PIO_EMAC0_MDC (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN8) /* Type: GPIO */
#define PIO_EMAC0_MDIO (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN9) /* Type: GPIO */
#define PIO_EMAC0_REFCK (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN7) /* Type: GPIO */
#define PIO_EMAC0_RX0 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN2) /* Type: GPIO */
#define PIO_EMAC0_RX1 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN3) /* Type: GPIO */
#define PIO_EMAC0_RXER (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN6) /* Type: GPIO */
#define PIO_EMAC0_TX0 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN0) /* Type: GPIO */
#define PIO_EMAC0_TX1 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN1) /* Type: GPIO */
#define PIO_EMAC0_TXEN (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN4) /* Type: GPIO */
/* GIgabit Ethernet 10/100/1000 - GMAC */
arch/arm/src/sama5/sam_emac.c
+161 -161
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/sama5/sam_ethernet.c
+2 -2
View File
@@ -109,7 +109,7 @@ static inline void up_gmac_initialize(void)
*
****************************************************************************/
#ifdef CONFIG_SAMA5_EMAC
#ifdef CONFIG_SAMA5_EMAC0
static inline void up_emac_initialize(void)
{
int ret;
@@ -162,4 +162,4 @@ void up_netinitialize(void)
#endif
}
#endif /* CONFIG_NET && CONFIG_SAMA5_EMAC */
#endif /* CONFIG_NET && CONFIG_SAMA5_EMAC0 */
arch/arm/src/sama5/sam_ethernet.h
+6 -6
View File
@@ -60,11 +60,11 @@
# undef CONFIG_SAMA5_GMAC_ISETH0
#endif
#ifndef CONFIG_SAMA5_EMAC
# undef CONFIG_SAMA5_EMAC_ISETH0
#ifndef CONFIG_SAMA5_EMAC0
# undef CONFIG_SAMA5_EMAC0_ISETH0
#endif
#if defined(CONFIG_SAMA5_GMAC_ISETH0) && defined(CONFIG_SAMA5_EMAC_ISETH0)
#if defined(CONFIG_SAMA5_GMAC_ISETH0) && defined(CONFIG_SAMA5_EMAC0_ISETH0)
# error GMAC and EMAC cannot both be ETH0
#endif
@@ -94,7 +94,7 @@
# endif
#endif
#if defined(CONFIG_SAMA5_EMAC_ISETH0)
#if defined(CONFIG_SAMA5_EMAC0_ISETH0)
# if defined(CONFIG_ETH0_PHY_DM9161)
# define SAMA5_EMAC_PHY_DM9161 1
# elif defined(CONFIG_ETH0_PHY_LAN8700)
@@ -106,7 +106,7 @@
# else
# error ETH0 PHY unrecognized
# endif
#elif defined(CONFIG_SAMA5_EMAC)
#elif defined(CONFIG_SAMA5_EMAC0)
# if defined(CONFIG_ETH1_PHY_DM9161)
# define SAMA5_EMAC_PHY_DM9161 1
# elif defined(CONFIG_ETH1_PHY_LAN8700)
@@ -172,7 +172,7 @@ int sam_gmac_initialize(void);
*
****************************************************************************/
#ifdef CONFIG_SAMA5_EMAC
#ifdef CONFIG_SAMA5_EMAC0
int sam_emac_initialize(void);
#endif
arch/arm/src/sama5/sam_isi.c
+1 -1
View File
@@ -180,4 +180,4 @@ int sam_isi_initialize(void)
#warning Missing logic
}
#endif /* CONFIG_SAMA5_ISI && CONFIG_SAMA5_EMAC */
#endif /* CONFIG_SAMA5_ISI && CONFIG_SAMA5_EMAC0 */
arch/arm/src/sama5/sam_pck.c
+1 -1
View File
@@ -238,4 +238,4 @@ void sam_pck_enable(enum pckid_e pckid, bool enable)
putreg32(regval, regaddr);
}
#endif /* CONFIG_SAMA5_ISI && CONFIG_SAMA5_EMAC */
#endif /* CONFIG_SAMA5_ISI && CONFIG_SAMA5_EMAC0 */
configs/sama5d3-xplained/README.txt
+14 -14
View File
@@ -752,21 +752,21 @@ Networking
-----------------------------
System Type -> SAMA5 Peripheral Support
CONFIG_SAMA5_EMAC=y : Enable the EMAC peripheral
CONFIG_SAMA5_EMAC0=y : Enable the EMAC peripheral
System Type -> EMAC device driver options
CONFIG_SAMA5_EMAC_NRXBUFFERS=16 : Set aside some RS and TX buffers
CONFIG_SAMA5_EMAC_NTXBUFFERS=4
CONFIG_SAMA5_EMAC_PHYADDR=1 : KSZ9031 PHY is at address 1
CONFIG_SAMA5_EMAC_AUTONEG=y : Use autonegotiation
CONFIG_SAMA5_EMAC_RMII=y : Either MII or RMII interface should work
CONFIG_SAMA5_EMAC_PHYSR=30 : Address of PHY status register on KSZ9031
CONFIG_SAMA5_EMAC_PHYSR_ALTCONFIG=y : Needed for KSZ9031
CONFIG_SAMA5_EMAC_PHYSR_ALTMODE=0x7 : " " " " " "
CONFIG_SAMA5_EMAC_PHYSR_10HD=0x1 : " " " " " "
CONFIG_SAMA5_EMAC_PHYSR_100HD=0x2 : " " " " " "
CONFIG_SAMA5_EMAC_PHYSR_10FD=0x5 : " " " " " "
CONFIG_SAMA5_EMAC_PHYSR_100FD=0x6 : " " " " " "
CONFIG_SAMA5_EMAC0_NRXBUFFERS=16 : Set aside some RS and TX buffers
CONFIG_SAMA5_EMAC0_NTXBUFFERS=4
CONFIG_SAMA5_EMAC0_PHYADDR=1 : KSZ9031 PHY is at address 1
CONFIG_SAMA5_EMAC0_AUTONEG=y : Use autonegotiation
CONFIG_SAMA5_EMAC0_RMII=y : Either MII or RMII interface should work
CONFIG_SAMA5_EMAC0_PHYSR=30 : Address of PHY status register on KSZ9031
CONFIG_SAMA5_EMAC0_PHYSR_ALTCONFIG=y : Needed for KSZ9031
CONFIG_SAMA5_EMAC0_PHYSR_ALTMODE=0x7 : " " " " " "
CONFIG_SAMA5_EMAC0_PHYSR_10HD=0x1 : " " " " " "
CONFIG_SAMA5_EMAC0_PHYSR_100HD=0x2 : " " " " " "
CONFIG_SAMA5_EMAC0_PHYSR_10FD=0x5 : " " " " " "
CONFIG_SAMA5_EMAC0_PHYSR_100FD=0x6 : " " " " " "
PHY selection. Later in the configuration steps, you will need to select
the KSZ9031 PHY for EMAC (See below)
@@ -2477,7 +2477,7 @@ SAMA5D3-Xplained Configuration Options
CONFIG_SAMA5_UHPHS - USB Host High Speed
CONFIG_SAMA5_UDPHS - USB Device High Speed
CONFIG_SAMA5_GMAC - Gigabit Ethernet MAC
CONFIG_SAMA5_EMAC - Ethernet MAC
CONFIG_SAMA5_EMAC0 - Ethernet MAC 0
CONFIG_SAMA5_LCDC - LCD Controller
CONFIG_SAMA5_ISI - Image Sensor Interface
CONFIG_SAMA5_SSC0 - Synchronous Serial Controller 0
configs/sama5d3-xplained/include/board.h
+1 -1
View File
@@ -334,7 +334,7 @@ void sam_boardinitialize(void);
*
************************************************************************************/
#if defined(CONFIG_NET) && (defined(CONFIG_SAMA5_EMAC) || defined(CONFIG_SAMA5_GMAC)) && \
#if defined(CONFIG_NET) && (defined(CONFIG_SAMA5_EMAC0) || defined(CONFIG_SAMA5_GMAC)) && \
defined(CONFIG_SAMA5_PIOE_IRQ)
xcpt_t sam_phyirq(int intf, xcpt_t irqhandler);
#endif
configs/sama5d3-xplained/nsh/defconfig
+1 -1
View File
@@ -169,7 +169,7 @@ CONFIG_SAMA5_HSMC=y
# CONFIG_SAMA5_UHPHS is not set
# CONFIG_SAMA5_UDPHS is not set
# CONFIG_SAMA5_GMAC is not set
# CONFIG_SAMA5_EMAC is not set
# CONFIG_SAMA5_EMAC0 is not set
# CONFIG_SAMA5_LCDC is not set
# CONFIG_SAMA5_ISI is not set
# CONFIG_SAMA5_CAN0 is not set
configs/sama5d3-xplained/src/Makefile
+1 -1
View File
@@ -84,7 +84,7 @@ CSRCS += sam_usb.c
endif
endif
ifeq ($(CONFIG_SAMA5_EMAC),y)
ifeq ($(CONFIG_SAMA5_EMAC0),y)
CSRCS += sam_ethernet.c
else
ifeq ($(CONFIG_SAMA5_GMAC),y)
configs/sama5d3-xplained/src/sam_ethernet.c
+2 -2
View File
@@ -55,7 +55,7 @@
************************************************************************************/
#ifdef CONFIG_SAMA5_PIOE_IRQ
#ifdef CONFIG_SAMA5_EMAC
#ifdef CONFIG_SAMA5_EMAC0
static xcpt g_emac_handler;
#endif
#ifdef CONFIG_SAMA5_GMAC
@@ -138,7 +138,7 @@ xcpt_t sam_phyirq(int intf, xcpt_t irqhandler)
xcpt_t oldhandler;
int irq;
#ifdef CONFIG_SAMA5_EMAC
#ifdef CONFIG_SAMA5_EMAC0
if (intf == EMAC_INTF)
{
handler = &g_emac_handler;
configs/sama5d3-xplained/src/sama5d3-xplained.h
+1 -1
View File
@@ -255,7 +255,7 @@
/* Networking */
#if !defined(CONFIG_NET) || (!defined(CONFIG_SAMA5_EMAC) && !defined(CONFIG_SAMA5_GMAC))
#if !defined(CONFIG_NET) || (!defined(CONFIG_SAMA5_EMAC0) && !defined(CONFIG_SAMA5_GMAC))
# undef HAVE_NETWORK
#endif
configs/sama5d3x-ek/README.txt
+16 -16
View File
@@ -895,25 +895,25 @@ Networking
-----------------------------
System Type
CONFIG_ARCH_CHIP_ATSAMA5D31=y : SAMA5D31 or SAMAD35 support EMAC
CONFIG_ARCH_CHIP_ATSAMA5D35=y : (others do not)
CONFIG_ARCH_CHIP_ATSAMA5D31=y : SAMA5D31 or SAMAD35 support EMAC
CONFIG_ARCH_CHIP_ATSAMA5D35=y : (others do not)
System Type -> SAMA5 Peripheral Support
CONFIG_SAMA5_EMAC=y : Enable the EMAC peripheral
CONFIG_SAMA5_EMAC0=y : Enable the EMAC peripheral
System Type -> EMAC device driver options
CONFIG_SAMA5_EMAC_NRXBUFFERS=16 : Set aside some RS and TX buffers
CONFIG_SAMA5_EMAC_NTXBUFFERS=4
CONFIG_SAMA5_EMAC_PHYADDR=1 : KSZ8021/31 PHY is at address 1
CONFIG_SAMA5_EMAC_AUTONEG=y : Use autonegotiation
CONFIG_SAMA5_EMAC_RMII=y : Either MII or RMII interface should work
CONFIG_SAMA5_EMAC_PHYSR=30 : Address of PHY status register on KSZ8021/31
CONFIG_SAMA5_EMAC_PHYSR_ALTCONFIG=y : Needed for KSZ8021/31
CONFIG_SAMA5_EMAC_PHYSR_ALTMODE=0x7 : " " " " " "
CONFIG_SAMA5_EMAC_PHYSR_10HD=0x1 : " " " " " "
CONFIG_SAMA5_EMAC_PHYSR_100HD=0x2 : " " " " " "
CONFIG_SAMA5_EMAC_PHYSR_10FD=0x5 : " " " " " "
CONFIG_SAMA5_EMAC_PHYSR_100FD=0x6 : " " " " " "
CONFIG_SAMA5_EMAC0_NRXBUFFERS=16 : Set aside some RS and TX buffers
CONFIG_SAMA5_EMAC0_NTXBUFFERS=4
CONFIG_SAMA5_EMAC0_PHYADDR=1 : KSZ8021/31 PHY is at address 1
CONFIG_SAMA5_EMAC0_AUTONEG=y : Use autonegotiation
CONFIG_SAMA5_EMAC0_RMII=y : Either MII or RMII interface should work
CONFIG_SAMA5_EMAC0_PHYSR=30 : Address of PHY status register on KSZ8021/31
CONFIG_SAMA5_EMAC0_PHYSR_ALTCONFIG=y : Needed for KSZ8021/31
CONFIG_SAMA5_EMAC0_PHYSR_ALTMODE=0x7 : " " " " " "
CONFIG_SAMA5_EMAC0_PHYSR_10HD=0x1 : " " " " " "
CONFIG_SAMA5_EMAC0_PHYSR_100HD=0x2 : " " " " " "
CONFIG_SAMA5_EMAC0_PHYSR_10FD=0x5 : " " " " " "
CONFIG_SAMA5_EMAC0_PHYSR_100FD=0x6 : " " " " " "
PHY selection. Later in the configuration steps, you will need to select
the KSZ8021/31 PHY for EMAC (See below)
@@ -2822,7 +2822,7 @@ SAMA5D3x-EK Configuration Options
CONFIG_SAMA5_UHPHS - USB Host High Speed
CONFIG_SAMA5_UDPHS - USB Device High Speed
CONFIG_SAMA5_GMAC - Gigabit Ethernet MAC
CONFIG_SAMA5_EMAC - Ethernet MAC
CONFIG_SAMA5_EMAC0 - Ethernet MAC 0
CONFIG_SAMA5_LCDC - LCD Controller
CONFIG_SAMA5_ISI - Image Sensor Interface
CONFIG_SAMA5_SSC0 - Synchronous Serial Controller 0
configs/sama5d3x-ek/include/board.h
+1 -1
View File
@@ -376,7 +376,7 @@ void sam_boardinitialize(void);
*
************************************************************************************/
#if defined(CONFIG_NET) && (defined(CONFIG_SAMA5_EMAC) || defined(CONFIG_SAMA5_GMAC)) && \
#if defined(CONFIG_NET) && (defined(CONFIG_SAMA5_EMAC0) || defined(CONFIG_SAMA5_GMAC)) && \
defined(CONFIG_SAMA5_PIOE_IRQ)
xcpt_t sam_phyirq(int intf, xcpt_t irqhandler);
#endif
configs/sama5d3x-ek/src/Makefile
+1 -1
View File
@@ -98,7 +98,7 @@ CSRCS += sam_usb.c
endif
endif
ifeq ($(CONFIG_SAMA5_EMAC),y)
ifeq ($(CONFIG_SAMA5_EMAC0),y)
CSRCS += sam_ethernet.c
else
ifeq ($(CONFIG_SAMA5_GMAC),y)
configs/sama5d3x-ek/src/sam_ethernet.c
+2 -2
View File
@@ -55,7 +55,7 @@
************************************************************************************/
#ifdef CONFIG_SAMA5_PIOE_IRQ
#ifdef CONFIG_SAMA5_EMAC
#ifdef CONFIG_SAMA5_EMAC0
static xcpt g_emac_handler;
#endif
#ifdef CONFIG_SAMA5_GMAC
@@ -138,7 +138,7 @@ xcpt_t sam_phyirq(int intf, xcpt_t irqhandler)
xcpt_t oldhandler;
int irq;
#ifdef CONFIG_SAMA5_EMAC
#ifdef CONFIG_SAMA5_EMAC0
if (intf == EMAC_INTF)
{
handler = &g_emac_handler;
configs/sama5d3x-ek/src/sama5d3x-ek.h
+1 -1
View File
@@ -314,7 +314,7 @@
/* Networking */
#if !defined(CONFIG_NET) || (!defined(CONFIG_SAMA5_EMAC) && !defined(CONFIG_SAMA5_GMAC))
#if !defined(CONFIG_NET) || (!defined(CONFIG_SAMA5_EMAC0) && !defined(CONFIG_SAMA5_GMAC))
# undef HAVE_NETWORK
#endif