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synced 2026-06-04 23:03:27 +08:00
Add support for STM32F107 OTG FS (doesn't work) and update USB support for Viewtools STM32F107~
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@@ -164,7 +164,7 @@
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# define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
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# define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
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#ifndef CONFIG_STM32_VALUELINE
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# define RCC_CFGR_USBPRE (1 << 22) /* Bit 22: USB prescaler */
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# define RCC_CFGR_USBPRE (1 << 22) /* Bit 22: USB/OTG FS prescaler */
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#endif
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#define RCC_CFGR_MCO_SHIFT (24) /* Bits 27-24: Microcontroller Clock Output */
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#define RCC_CFGR_MCO_MASK (15 << RCC_CFGR_MCO_SHIFT)
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@@ -272,6 +272,7 @@
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# define RCC_AHBENR_SDIOEN (1 << 10) /* Bit 10: SDIO clock enable */
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#endif
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#ifdef CONFIG_STM32_CONNECTIVITYLINE
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# define RCC_AHBENR_OTGFSEN (1 << 12) /* Bit 12: USB OTG FS clock enable */
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# define RCC_AHBENR_ETHMACEN (1 << 14) /* Bit 14: Ethernet MAC clock enable */
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# define RCC_AHBENR_ETHMACTXEN (1 << 15) /* Bit 15: Ethernet MAC TX clock enable */
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# define RCC_AHBENR_ETHMACRXEN (1 << 16) /* Bit 16: Ethernet MAC RX clock enable */
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@@ -148,10 +148,18 @@ static inline void rcc_enableahb(void)
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regval |= RCC_AHBENR_SDIOEN;
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#endif
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#if defined(CONFIG_STM32_ETHMAC) && defined(CONFIG_STM32_CONNECTIVITYLINE)
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#ifdef CONFIG_STM32_CONNECTIVITYLINE
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#ifdef CONFIG_STM32_OTGFS
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/* USB OTG FS clock enable */
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regval |= RCC_AHBENR_OTGFSEN;
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#endif
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#ifdef CONFIG_STM32_ETHMAC
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/* Ethernet clock enable */
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regval |= (RCC_AHBENR_ETHMACEN | RCC_AHBENR_ETHMACTXEN | RCC_AHBENR_ETHMACRXEN);
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#endif
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#endif
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putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */
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@@ -169,10 +177,13 @@ static inline void rcc_enableapb1(void)
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{
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uint32_t regval;
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#ifdef CONFIG_STM32_USB
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/* USB clock divider. This bit must be valid before enabling the USB
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* clock in the RCC_APB1ENR register. This bit can’t be reset if the USB
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* clock is enabled.
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#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_OTGFS)
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/* USB clock divider for USB FD device or USB OTG FS (OTGFS naming for this
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* bit is different, but it is the same bit.
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*
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* This bit must be valid before enabling the either the USB clock in the
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* RCC_APB1ENR register ro the OTG FS clock in the AHBENR reigser. This
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* bit can’t be reset if the USB clock is enabled.
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*/
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regval = getreg32(STM32_RCC_CFGR);
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