diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
index 5a6247faf44..8672f1fc712 100644
--- a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
@@ -75,18 +75,11 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-#define STM32_ADC1_OFFSET           0x0000
-#define STM32_ADC2_OFFSET           0x0100
-#define STM32_ADC3_OFFSET           0x0000
-#define STM32_ADC4_OFFSET           0x0100
 #define STM32_ADCCMN_OFFSET         0x0300
 
-#define STM32_ADC1_BASE             (STM32_ADC1_OFFSET+STM32_ADC12_BASE)   /* ADC1 Master ADC */
-#define STM32_ADC2_BASE             (STM32_ADC2_OFFSET+STM32_ADC12_BASE)   /* ADC2 Slave ADC */
-#define STM32_ADC3_BASE             (STM32_ADC3_OFFSET+STM32_ADC34_BASE)   /* ADC3 Master ADC */
-#define STM32_ADC4_BASE             (STM32_ADC4_OFFSET+STM32_ADC34_BASE)   /* ADC4 Slave ADC */
-#define STM32_ADC12CMN_BASE         (STM32_ADCCMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */
-#define STM32_ADC34CMN_BASE         (STM32_ADCCMN_OFFSET+STM32_ADC34_BASE) /* ADC3, ADC4 common */
+/* ADC1, ADC2 common - ADC2 not present on STM32 M0/M0+ devices */
+
+#define STM32_ADC12CMN_BASE         (STM32_ADCCMN_OFFSET+STM32_ADC1_BASE)
 
 /* Register Offsets *********************************************************/
 
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h
index ac00667b291..a5083157b9e 100644
--- a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h
@@ -99,7 +99,7 @@
 #define STM32_USART6_BASE    0x40011400     /* 0x40011400-0x400117ff USART6 */
 #define STM32_USART7_BASE    0x40011800     /* 0x40011800-0x40011bff USART7 */
 #define STM32_USART8_BASE    0x40011c00     /* 0x40011c00-0x40011fff USART8 */
-#define STM32_ADC12_BASE     0x40012400     /* 0x40012400-0x400127ff ADC 12 */
+#define STM32_ADC1_BASE      0x40012400     /* 0x40012400-0x400127ff ADC1 */
 #define STM32_TIM1_BASE      0x40012c00     /* 0x40012c00-0x40012fff TIM1 */
 #define STM32_SPI1_BASE      0x40013000     /* 0x40013000-0x400133ff SPI1 */
 #define STM32_USART1_BASE    0x40013800     /* 0x40013800-0x40013bff USART1 */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
index 919d747529b..2b2e5ccc7e1 100644
--- a/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
@@ -103,7 +103,7 @@
 #define STM32_USART6_BASE    0x40011400     /* 0x40011400-0x400117ff USART6 */
 #define STM32_USART7_BASE    0x40011800     /* 0x40011800-0x40011bff USART7 */
 #define STM32_USART8_BASE    0x40011c00     /* 0x40011c00-0x40011fff USART8 */
-#define STM32_ADC12_BASE     0x40012400     /* 0x40012400-0x400127ff ADC 12 */
+#define STM32_ADC1_BASE      0x40012400     /* 0x40012400-0x400127ff ADC1 */
 #define STM32_TIM1_BASE      0x40012c00     /* 0x40012c00-0x40012fff TIM1 */
 #define STM32_SPI1_BASE      0x40013000     /* 0x40013000-0x400133ff SPI1 */
 #define STM32_USART1_BASE    0x40013800     /* 0x40013800-0x40013bff USART1 */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
index 5d19a734ce3..487b44d8429 100644
--- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
@@ -86,7 +86,7 @@
 
 #define STM32_SYSCFG_BASE    0x40010000     /* 0x40010000-0x400103ff SYSCFG */
                                             /* EXTI ??? */
-#define STM32_ADC1_BASE      0x40012400     /* 0x40012400-0x400127ff ADC 1 */
+#define STM32_ADC1_BASE      0x40012400     /* 0x40012400-0x400127ff ADC1 */
 #define STM32_TIM1_BASE      0x40012c00     /* 0x40012c00-0x40012fff TIM1 */
 #define STM32_SPI1_BASE      0x40013000     /* 0x40013000-0x400133ff SPI1 */
 #define STM32_USART1_BASE    0x40013800     /* 0x40013800-0x40013bff USART1 */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h
index 200e997c163..d66e9ab990f 100644
--- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h
@@ -88,7 +88,7 @@
 #define STM32_TIM21_BASE     0x40010800     /* 0x40010800-0x40010bff TIM21 */
 #define STM32_TIM22_BASE     0x40014000     /* 0x40014000-0x400117ff TIM22 */
 #define STM32_FIREWALL_BASE  0x4001c000     /* 0x4001c000-0x400113ff Firewall */
-#define STM32_ADC12_BASE     0x40012400     /* 0x40012400-0x400127ff ADC12 */
+#define STM32_ADC1_BASE      0x40012400     /* 0x40012400-0x400127ff ADC1 */
 #define STM32_SPI1_BASE      0x40013000     /* 0x40013000-0x400133ff SPI1 */
 #define STM32_USART1_BASE    0x40013800     /* 0x40013800-0x40013bff USART1 */
 #define STM32_DBGMCU_BASE    0x40015800     /* 0x40015800-0x40015bff DBGMCU */