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Added functionality for Audio support with the STM32F746 Discoboard

Browse Source 
In particular additions to wm8994.h and filled functionality into
wm8994.c.

Resolved a few more remarks from review.
This commit is contained in:
okayserh
2022-04-30 11:10:12 +02:00
committed by Alan Carvalho de Assis
parent 5977279f0e
commit 476770e9fd
6 changed files with 1801 additions and 624 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/stm32f7/stm32_sai.c
+28 -29
View File
@@ -63,6 +63,7 @@
#include "stm32_dma.h" #include "stm32_dma.h"
#include "stm32_gpio.h" #include "stm32_gpio.h"
#include "stm32_sai.h" #include "stm32_sai.h"
#include "stm32_pwr.h"
#ifdef CONFIG_STM32F7_SAI #ifdef CONFIG_STM32F7_SAI
@@ -146,41 +147,19 @@
# define SAI_RXDMA16_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \ # define SAI_RXDMA16_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \
DMA_SCR_PSIZE_16BITS | DMA_SCR_MSIZE_16BITS | \ DMA_SCR_PSIZE_16BITS | DMA_SCR_MSIZE_16BITS | \
DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4) DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4)
# define SAI_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \ # define SAI_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \
DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \
DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4) DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4)
# define SAI_TXDMA8_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_M2P | DMA_SCR_MINC | \
# define SAI_TXDMA8_CONFIG (DMA_SCR_DIR_M2P | DMA_SCR_MINC | \
DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \
DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4) DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4)
# define SAI_TXDMA16_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_M2P | DMA_SCR_MINC | \ # define SAI_TXDMA16_CONFIG (DMA_SCR_DIR_M2P | DMA_SCR_MINC | \
DMA_SCR_PSIZE_16BITS | DMA_SCR_MSIZE_16BITS | \
DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4)
# define SAI_TXDMA32_CONFIG (DMA_SCR_DIR_M2P | DMA_SCR_MINC | \
DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \
DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4) DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4)
# define SAI_TXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_M2P | DMA_SCR_MINC | \
DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \
DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4)
#endif
#ifdef DMAMAP_SAI1
/* SAI DMA Channel/Stream selection. There
* are multiple DMA stream options that must be dis-ambiguated in the board.h
* file.
*/
# define SAI1_DMACHAN DMAMAP_SAI1
#endif
#ifdef DMAMAP_SAI2
/* SAI DMA Channel/Stream selection. There
* are multiple DMA stream options that must be dis-ambiguated in the board.h
* file.
*/
# define SAI2_DMACHAN DMAMAP_SAI2
#endif #endif
/**************************************************************************** /****************************************************************************
@@ -204,6 +183,10 @@ struct sai_buffer_s
struct stm32f7_sai_s struct stm32f7_sai_s
{ {
struct i2s_dev_s dev; /* Externally visible I2S interface */ struct i2s_dev_s dev; /* Externally visible I2S interface */
/* Callback for changes in sample rate */
stm32_sai_sampleratecb_t sampleratecb;
uintptr_t base; /* SAI block register base address */ uintptr_t base; /* SAI block register base address */
sem_t exclsem; /* Assures mutually exclusive access to SAI */ sem_t exclsem; /* Assures mutually exclusive access to SAI */
uint32_t frequency; /* SAI clock frequency */ uint32_t frequency; /* SAI clock frequency */
@@ -1151,6 +1134,17 @@ static uint32_t sai_samplerate(struct i2s_dev_s *dev, uint32_t rate)
DEBUGASSERT(priv && rate > 0); DEBUGASSERT(priv && rate > 0);
/* Call callback to change system clock (needed for STM32F746 Disco) */
if (priv->sampleratecb != NULL)
{
priv->frequency = priv->sampleratecb(dev, rate);
}
else
{
i2sinfo("No Sample Rate CB set!\n");
}
/* Save the new sample rate and update the divider */ /* Save the new sample rate and update the divider */
priv->samplerate = rate; priv->samplerate = rate;
@@ -1638,7 +1632,8 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv)
* *
****************************************************************************/ ****************************************************************************/
struct i2s_dev_s *stm32_sai_initialize(int intf) struct i2s_dev_s *stm32_sai_initialize(int intf,
stm32_sai_sampleratecb_t sampleratecb)
{ {
struct stm32f7_sai_s *priv; struct stm32f7_sai_s *priv;
irqstate_t flags; irqstate_t flags;
@@ -1652,6 +1647,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf)
{ {
i2sinfo("SAI1 Block A Selected\n"); i2sinfo("SAI1 Block A Selected\n");
priv = &g_sai1a_priv; priv = &g_sai1a_priv;
priv->sampleratecb = sampleratecb;
stm32_configgpio(GPIO_SAI1_SD_A); stm32_configgpio(GPIO_SAI1_SD_A);
# ifndef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B # ifndef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B
@@ -1668,6 +1664,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf)
{ {
i2sinfo("SAI1 Block B Selected\n"); i2sinfo("SAI1 Block B Selected\n");
priv = &g_sai1b_priv; priv = &g_sai1b_priv;
priv->sampleratecb = sampleratecb;
stm32_configgpio(GPIO_SAI1_SD_B); stm32_configgpio(GPIO_SAI1_SD_B);
# ifndef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A # ifndef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A
@@ -1684,6 +1681,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf)
{ {
i2sinfo("SAI2 Block A Selected\n"); i2sinfo("SAI2 Block A Selected\n");
priv = &g_sai2a_priv; priv = &g_sai2a_priv;
priv->sampleratecb = sampleratecb;
stm32_configgpio(GPIO_SAI2_SD_A); stm32_configgpio(GPIO_SAI2_SD_A);
# ifndef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B # ifndef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B
@@ -1700,6 +1698,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf)
{ {
i2sinfo("SAI2 Block B Selected\n"); i2sinfo("SAI2 Block B Selected\n");
priv = &g_sai2b_priv; priv = &g_sai2b_priv;
priv->sampleratecb = sampleratecb;
stm32_configgpio(GPIO_SAI2_SD_B); stm32_configgpio(GPIO_SAI2_SD_B);
# ifndef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A # ifndef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A
arch/arm/src/stm32f7/stm32_sai.h
+5 -1
View File
@@ -69,6 +69,9 @@ extern "C"
#define EXTERN extern #define EXTERN extern
#endif #endif
typedef uint32_t (*stm32_sai_sampleratecb_t)(struct i2s_dev_s *dev,
uint32_t rate);
/**************************************************************************** /****************************************************************************
* Name: stm32_sai_initialize * Name: stm32_sai_initialize
* *
@@ -83,7 +86,8 @@ extern "C"
* *
****************************************************************************/ ****************************************************************************/
struct i2s_dev_s *stm32_sai_initialize(int intf); struct i2s_dev_s *stm32_sai_initialize(int intf,
stm32_sai_sampleratecb_t sampleratecb);
#undef EXTERN #undef EXTERN
#ifdef __cplusplus #ifdef __cplusplus
boards/arm/stm32f7/stm32f746g-disco/include/board.h
+2 -2
View File
@@ -158,8 +158,8 @@
#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1) #define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(0) #define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(0)
#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(1) #define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(1)
#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0) #define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(1)
#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0) #define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(1)
#define STM32_RCC_DCKCFGR1_TIMPRESRC 0 #define STM32_RCC_DCKCFGR1_TIMPRESRC 0
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0 #define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0 #define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
boards/arm/stm32f7/stm32f746g-disco/src/stm32_wm8994.c
+104 -5
View File
@@ -33,13 +33,18 @@
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include <nuttx/i2c/i2c_master.h> #include <nuttx/i2c/i2c_master.h>
#include <nuttx/audio/i2s.h> #include <nuttx/audio/i2s.h>
#include <nuttx/audio/pcm.h>
#include <nuttx/audio/wm8994.h> #include <nuttx/audio/wm8994.h>
#include <arch/board/board.h> #include <arch/board/board.h>
#include "chip.h"
#include "stm32f746g-disco.h" #include "stm32f746g-disco.h"
#include "stm32_i2c.h" #include "stm32_i2c.h"
#include "stm32_sai.h" #include "stm32_sai.h"
#include "stm32_pwr.h"
#include "stm32_rcc.h"
#define HAVE_WM8994 #define HAVE_WM8994
#define WM8994_I2C_ADDRESS (0x34 >> 1) #define WM8994_I2C_ADDRESS (0x34 >> 1)
@@ -112,6 +117,88 @@ static struct stm32_mwinfo_s g_wm8994 =
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
static uint32_t stm32_wm8994_sampleratecb(struct i2s_dev_s *dev,
uint32_t rate)
{
uint32_t frequency = 0;
uint32_t regval = 0;
uint32_t mask_divq = 0;
uint32_t mask_i2s = 0;
/* Table 210 in "STM32F75xxx and STM32F74xxx advanced Arm(r)-based 32-bit
* MCUs - Reference manual" suggests the use of specific sai_x_ker_ck
* frequencies for common audio sample frequencies:
* For 44.1, 22.05, 11.025 KHz, 44.1 kHz * 256 = 11289600 Hz
* For 192, 96, 48, 32, 16, 8 KHz, 192 kHz * 256 = 49152000 Hz
*
* The below configurations use 429000000 / 19 / 2 = 1128473.x
* as approximation for the first group of sample frequencies and
* 344000000 / 1 / 7 = 49142857.x as approximation for the second
* group of sample frequencies
*/
if ((rate == 44100) || (rate == 22050) || (rate == 11025))
{
/* Division factor has 1 offset! (i.e. 0 = /1, 1 = /2, etc. */
mask_divq = RCC_DCKCFGR1_PLLI2SDIVQ(18);
mask_i2s = RCC_PLLI2SCFGR_PLLI2SN(429) |
RCC_PLLI2SCFGR_PLLI2SQ(2);
frequency = 11289473;
}
else
{
/* Division factor has 1 offset! (i.e. 0 = /1, 1 = /2, etc. */
mask_divq = RCC_DCKCFGR1_PLLI2SDIVQ(0);
mask_i2s = RCC_PLLI2SCFGR_PLLI2SN(344) |
RCC_PLLI2SCFGR_PLLI2SQ(7);
frequency = 49142857;
}
/* Check if i2s PLL is already in correct configuration */
if ((getreg32(STM32_RCC_DCKCFGR1) &
(RCC_DCKCFGR1_PLLI2SDIVQ_MASK)) != mask_divq)
{
/* Disable the PLLI2S */
regval = getreg32(STM32_RCC_CR);
regval &= ~(RCC_CR_PLLI2SON);
putreg32 (regval, STM32_RCC_CR);
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SON))
{
}
/* Set PLLI2S Configuration */
regval = getreg32(STM32_RCC_DCKCFGR1);
regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK);
regval |= mask_divq;
putreg32(regval, STM32_RCC_DCKCFGR1);
regval = getreg32(STM32_RCC_PLLI2SCFGR);
regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK
| RCC_PLLI2SCFGR_PLLI2SQ_MASK);
regval |= mask_i2s;
putreg32(regval, STM32_RCC_PLLI2SCFGR);
/* Enable the PLLI2S */
regval = getreg32(STM32_RCC_CR);
regval |= (RCC_CR_PLLI2SON);
putreg32 (regval, STM32_RCC_CR);
while (!(getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY))
{
}
}
audinfo("i2s PLL configured for samplerate %lu\n", rate);
return frequency;
}
/**************************************************************************** /****************************************************************************
* Name: stm32_wm8994_initialize * Name: stm32_wm8994_initialize
* *
@@ -132,6 +219,7 @@ static struct stm32_mwinfo_s g_wm8994 =
int stm32_wm8994_initialize(int minor) int stm32_wm8994_initialize(int minor)
{ {
struct audio_lowerhalf_s *wm8994; struct audio_lowerhalf_s *wm8994;
struct audio_lowerhalf_s *pcm;
struct i2c_master_s *i2c; struct i2c_master_s *i2c;
struct i2s_dev_s *i2s; struct i2s_dev_s *i2s;
static bool initialized = false; static bool initialized = false;
@@ -163,7 +251,7 @@ int stm32_wm8994_initialize(int minor)
/* Get an instance of the I2S interface for the CODEC data streams */ /* Get an instance of the I2S interface for the CODEC data streams */
i2s = stm32_sai_initialize(WM8994_SAI_BUS); i2s = stm32_sai_initialize(WM8994_SAI_BUS, stm32_wm8994_sampleratecb);
if (!i2s) if (!i2s)
{ {
auderr("stm32_sai_initialize failed\n"); auderr("stm32_sai_initialize failed\n");
@@ -183,21 +271,32 @@ int stm32_wm8994_initialize(int minor)
goto error; goto error;
} }
/* No we can embed the WM8994/I2C/I2S conglomerate into a PCM decoder
* instance so that we will have a PCM front end for the the WM8994
* driver.
*/
pcm = pcm_decode_initialize(wm8994);
if (pcm == NULL)
{
auderr("ERROR: Failed create the PCM decoder\n");
ret = -ENODEV;
goto error;
}
/* Create a device name */ /* Create a device name */
snprintf(devname, 12, "pcm%d", minor); snprintf(devname, 12, "pcm%d", minor);
#if 0
/* Finally, we can register the ADAU1961/I2C/I2S audio device. */ /* Finally, we can register the ADAU1961/I2C/I2S audio device. */
ret = audio_register(devname, wm8994); ret = audio_register(devname, pcm);
if (ret < 0) if (ret < 0)
{ {
auderr("failed to register /dev/%s device: %d\n", devname, ret); auderr("failed to register /dev/%s device: %d\n", devname, ret);
goto error; goto error;
} }
#endif
/* Now we are initialized */ /* Now we are initialized */
initialized = true; initialized = true;
drivers/audio/wm8994.c
+908 -77
View File
File diff suppressed because it is too large Load Diff
drivers/audio/wm8994.h
+275 -31
View File
@@ -276,7 +276,7 @@
#define WM8994_AIF2_EQ_BAND_4A 0x58D /* AIF2 EQ Band 4 A */ #define WM8994_AIF2_EQ_BAND_4A 0x58D /* AIF2 EQ Band 4 A */
#define WM8994_AIF2_EQ_BAND_4B 0x58E /* AIF2 EQ Band 4 B */ #define WM8994_AIF2_EQ_BAND_4B 0x58E /* AIF2 EQ Band 4 B */
#define WM8994_AIF2_EQ_BAND_4C 0x58F /* AIF2 EQ Band 4 C */ #define WM8994_AIF2_EQ_BAND_4C 0x58F /* AIF2 EQ Band 4 C */
#define WM8994_AIF2_EQ_BAND_4PG 0x490 /* AIF2 EQ Band 4 PG */ #define WM8994_AIF2_EQ_BAND_4PG 0x590 /* AIF2 EQ Band 4 PG */
#define WM8994_AIF2_EQ_BAND_5A 0x591 /* AIF2 EQ Band 5 A */ #define WM8994_AIF2_EQ_BAND_5A 0x591 /* AIF2 EQ Band 5 A */
#define WM8994_AIF2_EQ_BAND_5B 0x592 /* AIF2 EQ Band 5 B */ #define WM8994_AIF2_EQ_BAND_5B 0x592 /* AIF2 EQ Band 5 B */
#define WM8994_AIF2_EQ_BAND_5PG 0x593 /* AIF2 EQ Band 5 PG */ #define WM8994_AIF2_EQ_BAND_5PG 0x593 /* AIF2 EQ Band 5 PG */
@@ -363,10 +363,10 @@
#define WM8994_BIAS_ENA (1 << 0) /* Bit 0: Enables the Normal bias current generator (for all analogue functions */ #define WM8994_BIAS_ENA (1 << 0) /* Bit 0: Enables the Normal bias current generator (for all analogue functions */
#define WM8994_BIAS_ENA_DISABLE (0) /* Disabled */ #define WM8994_BIAS_ENA_DISABLE (0) /* Disabled */
#define WM8994_BIAS_ENA_ENABLE WM8994_BIAS_ENA /* Enabled */ #define WM8994_BIAS_ENA_ENABLE WM8994_BIAS_ENA /* Enabled */
#define WM8994_VMID_SEL_SHITF (1) /* Bits 1-2: VMID Divider Enable and Select */ #define WM8994_VMID_SEL_SHIFT (1) /* Bits 1-2: VMID Divider Enable and Select */
#define WM8994_VMID_SEL_DISABLE (0 << WM8994_VMID_SEL_SHIFT) /* VMID disabled (for OFF mode) */ #define WM8994_VMID_SEL_DISABLE (0 << WM8994_VMID_SEL_SHIFT) /* VMID disabled (for OFF mode) */
#define WM8994_VMID_SEL_2x40K (1 << WM8994_VMID_SEL_SHIFT) /* 2*40k divider (for normal operation */ #define WM8994_VMID_SEL_2X40K (1 << WM8994_VMID_SEL_SHIFT) /* 2*40k divider (for normal operation */
#define WM8994_VMID_SEL_2x240K (2 << WM8994_VMID_SEL_SHIFT) /* 2*240k divider (for low power standby*/ #define WM8994_VMID_SEL_2X240K (2 << WM8994_VMID_SEL_SHIFT) /* 2*240k divider (for low power standby*/
/* Bit 3: Reserved */ /* Bit 3: Reserved */
#define WM8994_MICB1_ENA (1 << 4) /* Bit 4; Microphone Bias 1 Enable */ #define WM8994_MICB1_ENA (1 << 4) /* Bit 4; Microphone Bias 1 Enable */
@@ -636,15 +636,16 @@
#define WM8994_HPOUT1L_VOL_MIN (0 << WM8994_HPOUT1L_VOL_SHIFT) /* -57dB */ #define WM8994_HPOUT1L_VOL_MIN (0 << WM8994_HPOUT1L_VOL_SHIFT) /* -57dB */
#define WM8994_HPOUT1L_VOL_DEFAULT (0 << WM8994_HPOUT1L_VOL_SHIFT) /* -57dB to +6dB in 1 dB steps*/ #define WM8994_HPOUT1L_VOL_DEFAULT (0 << WM8994_HPOUT1L_VOL_SHIFT) /* -57dB to +6dB in 1 dB steps*/
#define WM8994_HPOUT1L_VOL_MAX (0x3F << WM8994_HPOUT1L_VOL_SHIFT) /* +6dB */ #define WM8994_HPOUT1L_VOL_MAX (0x3F << WM8994_HPOUT1L_VOL_SHIFT) /* +6dB */
# define WM8994_HPOUT1L_VOL(n) ((uint16_t)(n) << WM8994_HPOUT1L_VOL_SHIFT) /* Set volume to defined value */
#define WM8994_HPOUT1L_MUTE_N_SHIFT (6) /* Bit 6: HPOUT1LVOL (Left Headphone Output PGA) Mute */ #define WM8994_HPOUT1L_MUTE_N_SHIFT (6) /* Bit 6: HPOUT1LVOL (Left Headphone Output PGA) Mute */
#define WM8994_HPOUT1L_MUTE_N_YES (0) /* Mute */ #define WM8994_HPOUT1L_MUTE_N_YES (0) /* Mute */
#define WM8994_HPOUT1L_MUTE_N_NO (1 << WM8994_HPOUT1L_MUTE_N_SHIFT) /* Un-Mute */ #define WM8994_HPOUT1L_MUTE_N_NO (1 << WM8994_HPOUT1L_MUTE_N_SHIFT) /* Un-Mute */
#define WM8994_HPOUT1L_ZC_SHIFT (7) /* Bit 7: HPOUT1LVOL (Left Headphone Output PGA) Zero Cross */ #define WM8994_HPOUT1L_ZC_SHIFT (7) /* Bit 7: HPOUT1LVOL (Left Headphone Output PGA) Zero Cross */
#define WM8994_HPOUT1L_ZC_DIABLED (0) /* Zero cross disabled */ #define WM8994_HPOUT1L_ZC_DIABLED (0) /* Zero cross disabled */
#define WM8994_HPOUT1L_ZC_ENABLED (WM8994_HPOUT1L_ZC_SHIFT) /* Zero cross enabled */ #define WM8994_HPOUT1L_ZC_ENABLED (1 << WM8994_HPOUT1L_ZC_SHIFT) /* Zero cross enabled */
#define WM8994_HPOUT1_VU_SHIFT (8) /* Bit 8: Headphone Output PGA Volume Update */ #define WM8994_HPOUT1_VU_SHIFT (8) /* Bit 8: Headphone Output PGA Volume Update */
#define WM8994_HPOUT1_VU_DISABLE (0) #define WM8994_HPOUT1_VU_DISABLE (0)
#define WM8994_HPOUT1_VU_ENABLED (WM8994_HPOUT1L_VU_SHIFT) /* Writing a 1 to this bit will update HPOUT1LVOL and #define WM8994_HPOUT1_VU_ENABLED (1 << WM8994_HPOUT1_VU_SHIFT) /* Writing a 1 to this bit will update HPOUT1LVOL and
* HPOUT1RVOL volumes simultaneously */ * HPOUT1RVOL volumes simultaneously */
/* R29 (0x1D) - Right Output Volume /* R29 (0x1D) - Right Output Volume
@@ -654,16 +655,17 @@
#define WM8994_HPOUT1R_VOL_MIN (0 << WM8994_HPOUT1R_VOL_SHIFT) /* -57dB */ #define WM8994_HPOUT1R_VOL_MIN (0 << WM8994_HPOUT1R_VOL_SHIFT) /* -57dB */
#define WM8994_HPOUT1R_VOL_DEFAULT (0 << WM8994_HPOUT1R_VOL_SHIFT) /* -57dB to +6dB in 1 dB steps*/ #define WM8994_HPOUT1R_VOL_DEFAULT (0 << WM8994_HPOUT1R_VOL_SHIFT) /* -57dB to +6dB in 1 dB steps*/
#define WM8994_HPOUT1R_VOL_MAX (0x3F << WM8994_HPOUT1R_VOL_SHIFT) /* +6dB */ #define WM8994_HPOUT1R_VOL_MAX (0x3F << WM8994_HPOUT1R_VOL_SHIFT) /* +6dB */
# define WM8994_HPOUT1R_VOL(n) ((uint16_t)(n) << WM8994_HPOUT1R_VOL_SHIFT) /* Set volume to defined value */
#define WM8994_HPOUT1R_MUTE_N_SHIFT (6) /* Bit 6: HPOUT1RVOL (Left Headphone Output PGA) Mute */ #define WM8994_HPOUT1R_MUTE_N_SHIFT (6) /* Bit 6: HPOUT1RVOL (Left Headphone Output PGA) Mute */
#define WM8994_HPOUT1R_MUTE_N_YES (0) /* Mute */ #define WM8994_HPOUT1R_MUTE_N_YES (0) /* Mute */
#define WM8994_HPOUT1R_MUTE_N_NO (1 << WM8994_HPOUT1R_MUTE_N_SHIFT) /* Un-Mute */ #define WM8994_HPOUT1R_MUTE_N_NO (1 << WM8994_HPOUT1R_MUTE_N_SHIFT) /* Un-Mute */
#define WM8994_HPOUT1R_ZC_SHIFT (7) /* Bit 7: HPOUT1RVOL (Left Headphone Output PGA) Zero Cross */ #define WM8994_HPOUT1R_ZC_SHIFT (7) /* Bit 7: HPOUT1RVOL (Left Headphone Output PGA) Zero Cross */
#define WM8994_HPOUT1R_ZC_DIABLED (0) /* Zero cross disabled */ #define WM8994_HPOUT1R_ZC_DIABLED (0) /* Zero cross disabled */
#define WM8994_HPOUT1R_ZC_ENABLED (WM8994_HPOUT1R_ZC_SHIFT) /* Zero cross enabled */ #define WM8994_HPOUT1R_ZC_ENABLED (1 << WM8994_HPOUT1R_ZC_SHIFT) /* Zero cross enabled */
#if 0 #if 0
#define WM8994_HPOUT1_VU_SHIFT (1 << 8) /* Bit 8: Headphone Output PGA Volume Update */ #define WM8994_HPOUT1_VU_SHIFT (1 << 8) /* Bit 8: Headphone Output PGA Volume Update */
#define WM8994_HPOUT1_VU_DISABLE (0) #define WM8994_HPOUT1_VU_DISABLE (0)
#define WM8994_HPOUT1_VU_ENABLED (WM8994_HPOUT1L_VU_SHIFT) /* Writing a 1 to this bit will update HPOUT1LVOL and #define WM8994_HPOUT1_VU_ENABLED (1 << WM8994_HPOUT1L_VU_SHIFT) /* Writing a 1 to this bit will update HPOUT1LVOL and
* HPOUT1RVOL volumes simultaneously */ * HPOUT1RVOL volumes simultaneously */
#endif #endif
@@ -752,6 +754,34 @@
/* R46 (0x2E) - Output Mixer (2) /* R46 (0x2E) - Output Mixer (2)
*/ */
#define WM8994_DAC1R_TO_MIXOUTR (1 << 0) /* Bit 0: Right DAC1 to MIXOUTR Mute */
#define WM8994_DAC1R_TO_MIXOUTR_MUTE (0) /* Mute */
#define WM8994_DAC1R_TO_MIXOUTR_UNMUTE (WM8994_DAC1R_TO_MIXOUTR) /* Un-mute */
#define WM8994_IN2RP_TO_MIXOUTR (1 << 1) /* Bit 1: IN2RP to MIXOUTR Mute */
#define WM8994_IN2RP_TO_MIXOUTR_MUTE (0) /* Mute */
#define WM8994_IN2RP_TO_MIXOUTR_UNMUTE (WM8994_IN2RP_TO_MIXOUTR) /* Un-mute */
#define WM8994_IN1R_TO_MIXOUTR (1 << 2) /* Bit 2: IN1R PGA Output to MIXOUTR Mute */
#define WM8994_IN1R_TO_MIXOUTR_MUTE (0) /* Mute */
#define WM8994_IN1R_TO_MIXOUTR_UNMUTE (WM8994_IN1R_TO_MIXOUTR_MUTE) /* Un-mute */
#define WM8994_IN1L_TO_MIXOUTR (1 << 3) /* Bit 3: IN1L PGA Output to MIXOUTR Mute */
#define WM8994_IN1L_TO_MIXOUTR_MUTE (0) /* Mute */
#define WM8994_IN1L_TO_MIXOUTR_UNMUTE (WM8994_IN1L_TO_MIXOUTR_MUTE) /* Un-mute */
#define WM8994_IN2RN_TO_MIXOUTR (1 << 4) /* Bit 4: IN2RN to MIXOUTR Mute */
#define WM8994_IN2RN_TO_MIXOUTR_MUTE (0) /* Mute */
#define WM8994_IN2RN_TO_MIXOUTR_UNMUTE (WM8994_IN2RN_TO_MIXOUTR) /* Un-mute */
#define WM8994_IN2LN_TO_MIXOUTR (1 << 5) /* Bit 5: IN2LN to MIXOUTR Mute */
#define WM8994_IN2LN_TO_MIXOUTR_MUTE (0) /* Mute */
#define WM8994_IN2LN_TO_MIXOUTR_UNMUTE (WM8994_IN2LN_TO_MIXOUTR) /* Un-mute */
#define WM8994_MIXINR_TO_MIXOUTR (1 << 6) /* Bit 6: MIXINR Output(Left ADC bypass) to MIXOUTR Mute */
#define WM8994_MIXINR_TO_MIXOUTR_MUTE (0) /* mute */
#define WM8994_MIXINR_TO_MIXOUTR_UNMUTE (WM8994_MIXINR_TO_MIXOUTR) /* Un-mute */
#define WM8994_MIXINL_TO_MIXOUTR (1 << 7) /* Bit 7: MIXINL Output(Left ADC bypass) to MIXOUTR Mute */
#define WM8994_MIXINL_TO_MIXOUTR_MUTE (0) /* mute */
#define WM8994_MIXINL_TO_MIXOUTR_UNMUTE (WM8994_MIXINL_TO_MIXOUTR) /* Un-mute */
#define WM8994_DAC1R_TO_HPOUT1R (1 << 8) /* Bit 8: HPOUT1RVOL(Left Headphone Output PGA) Input Select */
#define WM8994_DAC1R_TO_HPOUT1R_MIXOUTL (0) /* MIXOUTR */
#define WM8994_DAC1R_TO_HPOUT1R_DAC1L (WM8994_DAC1R_TO_HPOUT1R) /* DAC1R */
/* R47 (0x2F) - Output Mixer (3) /* R47 (0x2F) - Output Mixer (3)
*/ */
@@ -775,6 +805,36 @@
/* R54 (0x36) - Speaker Mixer /* R54 (0x36) - Speaker Mixer
*/ */
#define WM8994_DAC2L_TO_SPKMIXL (1 << 9) /* Bit 9: Left DAC2 to SPKMXL Mute */
#define WM8994_DAC2L_TO_SPKMIXL_MUTE (0) /* Mute */
#define WM8994_DAC2L_TO_SPKMIXL_UNMUTE (WM8994_DAC2L_TO_SPKMIXL) /* Un-mute */
#define WM8994_DAC2R_TO_SPKMIXR (1 << 8) /* Bit 8: Right DAC2 to SPKMXL Mute */
#define WM8994_DAC2R_TO_SPKMIXL_MUTE (0) /* Mute */
#define WM8994_DAC2R_TO_SPKMIXL_UNMUTE (WM8994_DAC2R_TO_SPKMIXL) /* Un-mute */
#define WM8994_MIXINL_TO_SPKMIXL (1 << 7) /* Bit 7: MIXINL (Left ADC bypass) to SPKMIXL Mute */
#define WM8994_MIXINL_TO_SPKMIXL_MUTE (0) /* Mute */
#define WM8994_MIXINL_TO_SPKMIXL_UNMUTE (WM8994_MIXINL_TO_SPKMIXL) /* Un-mute */
#define WM8994_MIXINR_TO_SPKMIXR (1 << 6) /* Bit 6: MIXINR (Right ADC bypass) to SPKMIXR Mute */
#define WM8994_MIXINR_TO_SPKMIXR_MUTE (0) /* Mute */
#define WM8994_MIXINR_TO_SPKMIXR_UNMUTE (WM8994_MIXINR_TO_SPKMIXR) /* Un-mute */
#define WM8994_IN1LP_TO_SPKMIXL (1 << 5) /* Bit 5: IN1LP to SPKMIXL Mute */
#define WM8994_IN1LP_TO_SPKMIXL_MUTE (0) /* Mute */
#define WM8994_IN1LP_TO_SPKMIXL_UNMUTE (WM8994_IN1LP_TO_SPKMIXL) /* Un-mute */
#define WM8994_IN1RP_TO_SPKMIXR (1 << 4) /* Bit 4: IN1RP to SPKMIXR Mute */
#define WM8994_IN1RP_TO_SPKMIXR_MUTE (0) /* Mute */
#define WM8994_IN1RP_TO_SPKMIXR_UNMUTE (WM8994_IN1RP_TO_SPKMIXR) /* Un-mute */
#define WM8994_MIXOUTL_TO_SPKMIXL (1 << 3) /* Bit 3: MIXOUTL to SPKMIXL Mute */
#define WM8994_MIXOUTL_TO_SPKMIXL_MUTE (0) /* Mute */
#define WM8994_MIXOUTL_TO_SPKMIXL_UNMUTE (WM8994_MIXOUTL_TO_SPKMIXL) /* Un-mute */
#define WM8994_MIXOUTR_TO_SPKMIXR (1 << 2) /* Bit 2: MIXOUTR to SPKMIXR Mute */
#define WM8994_MIXOUTR_TO_SPKMIXR_MUTE (0) /* Mute */
#define WM8994_MIXOUTR_TO_SPKMIXR_UNMUTE (WM8994_MIXOUTR_TO_SPKMIXR) /* Un-mute */
#define WM8994_DAC1L_TO_SPKMIXL (1 << 1) /* Bit 1: DAC1L to SPKMIXL Mute */
#define WM8994_DAC1L_TO_SPKMIXL_MUTE (0) /* Mute */
#define WM8994_DAC1L_TO_SPKMIXL_UNMUTE (WM8994_DAC1L_TO_SPKMIXL) /* Un-mute */
#define WM8994_DAC1R_TO_SPKMIXR (1 << 0) /* Bit 0: DAC1R to SPKMIXR Mute */
#define WM8994_DAC1R_TO_SPKMIXR_MUTE (0) /* Mute */
#define WM8994_DAC1R_TO_SPKMIXR_UNMUTE (WM8994_DAC1R_TO_SPKMIXR) /* Un-mute */
/* R55 (0x37) - Additional Control /* R55 (0x37) - Additional Control
*/ */
@@ -829,15 +889,81 @@
/* R76 (0x4C) - Charge Pump (1) /* R76 (0x4C) - Charge Pump (1)
*/ */
#define WM8994_CP_ENA (1 << 15) /* Bit 15: Enable charge-pump digits */
#define WM8994_CP_ENA_DISABLE (0) /* Diable */
#define WM8994_CP_ENA_ENABLE (WM8994_CP_ENA) /* Enable */
/* R77 (0x4D) - Charge Pump (2) /* R77 (0x4D) - Charge Pump (2)
*/ */
#define WM8994_CP_DISCH (1 << 15) /* Bit 15: Charge Pump Discharge Select */
#define WM8994_CP_DISCH_FLOAT (0) /* Charge Pump outputs floating when disabled */
#define WM8994_CP_DISCH_DISCHARGE (WM8994_CP_DISCH) /* Charge Pump outputs discharged when disabled */
/* R81 (0x51) - Class W (1) /* R81 (0x51) - Class W (1)
*/ */
#define WM8994_CP_DYN_SRC_SEL_SHIFT 8 /* Bits 8-9: Selects the digitial audio source for
* envelope tracking */
#define WM8994_CP_DYN_SRC_SEL_MASK (3 << WM8994_CP_DYN_SRC_SEL_SHIFT)
#define WM8994_CP_DYN_SRC_SEL_AIF1_TS0 (0 << WM8994_CP_DYN_SRC_SEL_SHIFT) /* AIF1, DAC Timeslot 0 */
#define WM8994_CP_DYN_SRC_SEL_AIF1_TS1 (1 << WM8994_CP_DYN_SRC_SEL_SHIFT) /* AIF1, DAC Timeslot 1 */
#define WM8994_CP_DYN_SRC_SEL_AIF2_DATA (2 << WM8994_CP_DYN_SRC_SEL_SHIFT) /* AIF2, DAC data */
#define WM8994_CP_DYN_PWR (1 << 0) /* Bit 0: Enable dynamic charge pump power control */
#define WM8994_CP_DYN_PWR_CG (0) /* Charge pump controlled by volume register (Class G) */
#define WM8994_CP_DYN_PWR_CW (WM8994_CP_DYN_PWR) /* Charge pump controlled by real-time audio lev. (Class W) */
/* R84 (0x54) - DC Servo (1) /* R84 (0x54) - DC Servo (1)
*/ */
#define WM8994_DCS_TRIG_SINGLE_1 (1 << 13) /* Bit 13: Writing 1 to this bit selects a single DC offset
* correction for HPOUT1R. In readback, a value of 1
* indicates that the DC Servo single correction is
* in progress
*/
#define WM8994_DCS_TRIG_SINGLE_0 (1 << 12) /* Bit 12: Writing 1 to this bit selects a single DC offset
* correction for HPOUT1L. In readback, a value of 1
* indicates that the DC Servo single correction is
* in progress
*/
#define WM8994_DCS_TRIG_SERIES_1 (1 << 9) /* Bit 9: Writing 1 to this bit selects a series of DC offset
* corrections for HPOUT1R. In readback, a value of 1
* indicates that the DC Servo DAC write correction is
* in progress
*/
#define WM8994_DCS_TRIG_SERIES_0 (1 << 8) /* Bit 8: Writing 1 to this bit selects a series of DC offset
* corrections for HPOUT1L. In readback, a value of 1
* indicates that the DC Servo DAC write correction is
* in progress
*/
#define WM8994_DCS_TRIG_STARTUP_1 (1 << 5) /* Bit 5: Writing 1 to this bit selects Start-Up DC
* Servo mode for HPOUT1R. In readback, a value of 1
* indicates that the DC Servo Start-Up correction is
* in progress
*/
#define WM8994_DCS_TRIG_STARTUP_0 (1 << 4) /* Bit 4: Writing 1 to this bit selects Start-Up DC
* Servo mode for HPOUT1L. In readback, a value of 1
* indicates that the DC Servo Start-Up correction is
* in progress
*/
#define WM8994_DCS_TRIG_DAC_WR_1 (1 << 3) /* Bit 3: Writing 1 to this bit selects DAC Write
* DC Servo mode for HPOUT1R. In readback, a value of 1
* indicates that the DC Servo DAC Write correction is
* in progress
*/
#define WM8994_DCS_TRIG_DAC_WR_0 (1 << 2) /* Bit 2: Writing 1 to this bit selects DAC Write
* DC Servo mode for HPOUT1L. In readback, a value of 1
* indicates that the DC Servo DAC Write correction is
* in progress
*/
#define WM8994_DCS_ENA_CHAN_1 (1 << 1) /* Bit 1: DC Servo enable for HPOUT1R */
#define WM8994_DCS_ENA_CHAN_1_DISABLE (0) /* Diable */
#define WM8994_DCS_ENA_CHAN_1_ENABLE (WM8994_DCS_ENA_CHAN_1) /* Enable */
#define WM8994_DCS_ENA_CHAN_0 (1 << 0) /* Bit 0: DC Servo enable for HPOUT1L */
#define WM8994_DCS_ENA_CHAN_0_DISABLE (0) /* Diable */
#define WM8994_DCS_ENA_CHAN_0_ENABLE (WM8994_DCS_ENA_CHAN_1) /* Enable */
/* R85 (0x55) - DC Servo (2) /* R85 (0x55) - DC Servo (2)
*/ */
@@ -850,6 +976,25 @@
/* R96 (0x60) - Analogue HP (1) /* R96 (0x60) - Analogue HP (1)
*/ */
#define WM8994_HPOUT1L_RMV_SHORT (1 << 7) /* Bit 7: Removes HPOUT1L short */
#define WM8994_HPOUT1L_RMV_SHORT_DISABLE (0) /* HPOUT1L short diabled */
#define WM8994_HPOUT1L_RMV_SHORT_ENABLE (WM8994_HPOUT1L_RMV_SHORT) /* HPOUT1L short enabled */
#define WM8994_HPOUT1L_OUTP (1 << 6) /* Bit 6: Enables HPOUT1L output stage */
#define WM8994_HPOUT1L_OUTP_DISABLE (0) /* Diable */
#define WM8994_HPOUT1L_OUTP_ENABLE (WM8994_HPOUT1L_OUTP) /* Enable */
#define WM8994_HPOUT1L_DLY (1 << 5) /* Bit 5: Enables HPOUT1L intermediate stage */
#define WM8994_HPOUT1L_DLY_DISABLE (0) /* Diable */
#define WM8994_HPOUT1L_DLY_ENABLE (WM8994_HPOUT1L_DLY) /* Enable */
#define WM8994_HPOUT1R_RMV_SHORT (1 << 3) /* Bit 3: Removes HPOUT1R short */
#define WM8994_HPOUT1R_RMV_SHORT_DISABLE (0) /* HPOUT1R short diabled */
#define WM8994_HPOUT1R_RMV_SHORT_ENABLE (WM8994_HPOUT1R_RMV_SHORT) /* HPOUT1R short enabled */
#define WM8994_HPOUT1R_OUTP (1 << 2) /* Bit 2: Enables HPOUT1R output stage */
#define WM8994_HPOUT1R_OUTP_DISABLE (0) /* Diable */
#define WM8994_HPOUT1R_OUTP_ENABLE (WM8994_HPOUT1R_OUTP) /* Enable */
#define WM8994_HPOUT1R_DLY (1 << 1) /* Bit 1: Enables HPOUT1R intermediate stage */
#define WM8994_HPOUT1R_DLY_DISABLE (0) /* Diable */
#define WM8994_HPOUT1R_DLY_ENABLE (WM8994_HPOUT1R_DLY) /* Enable */
/* R208 (0xD0) - Mic Detect 1 /* R208 (0xD0) - Mic Detect 1
*/ */
@@ -868,9 +1013,21 @@
/* R272 (0x110) - Write Sequencer Ctrl (1) /* R272 (0x110) - Write Sequencer Ctrl (1)
*/ */
#define WM8994_WSEQ_ENA (1 << 15) /* Bit 15: Write Sequencer Enable */
#define WM8994_WSEQ_ENA_DISABLE (0) /* Diable */
#define WM8994_WSEQ_ENA_ENABLE (WM8994_WSEQ_ENA) /* Enable */
#define WM8994_WSEQ_ABORT (1 << 9) /* Bit 9: Writing 1 to this bit aborts the current seq. */
#define WM8994_WSEQ_START (1 << 8) /* Bit 8: Writing 1 to this bit starts the seq. */
#define WM8994_WSEQ_START_INDEX_SHIFT (0) /* Bits 0-6: Sequence start index */
#define WM8994_WSEQ_START_INDEX_MASK (0x7F << WM8994_WSEQ_START_INDEX_SHIFT)
/* R273 (0x111) - Write Sequencer Ctrl (2) /* R273 (0x111) - Write Sequencer Ctrl (2)
*/ */
#define WM8994_WSEQ_BUSY (1 << 8) /* Bit 8: Sequencer busy flag (read only) */
#define WM8994_WSEQ_CURRENT_INDEX_SHIFT (0) /* Bits 0-6: Sequence current index */
#define WM8994_WSEQ_CURRENT_INDEX_MASK (0x7F << W8994_WSEQ_CURRENT_INDEX_SHIFT)
/* R512 (0x200) - AIF1 Clocking (1) /* R512 (0x200) - AIF1 Clocking (1)
*/ */
@@ -929,18 +1086,18 @@
#define WM8994_AIF1CLK_RATE_8 (8 << WM8994_AIF1CLK_RATE_SHIFT) /* 1408 */ #define WM8994_AIF1CLK_RATE_8 (8 << WM8994_AIF1CLK_RATE_SHIFT) /* 1408 */
#define WM8994_AIF1CLK_RATE_9 (9 << WM8994_AIF1CLK_RATE_SHIFT) /* 1536 */ #define WM8994_AIF1CLK_RATE_9 (9 << WM8994_AIF1CLK_RATE_SHIFT) /* 1536 */
#define WM8994_AIF1_SR_SHIFT (4) /* Bits 4-7: Selects the AIF1 Sample Rate (fs) */ #define WM8994_AIF1_SR_SHIFT (4) /* Bits 4-7: Selects the AIF1 Sample Rate (fs) */
#define WM8994_AIF1_SR_MASK (0xf << WM8994_AIF1CLK_RATE_SHIFT) #define WM8994_AIF1_SR_MASK (0xf << WM8994_AIF1_SR_SHIFT)
#define WM8994_AIF1_SR_8K (0 << WM8994_AIF1CLK_RATE_SHIFT) /* 8kHz */ #define WM8994_AIF1_SR_8K (0 << WM8994_AIF1_SR_SHIFT) /* 8kHz */
#define WM8994_AIF1_SR_11K (1 << WM8994_AIF1CLK_RATE_SHIFT) /* 11.025kHz */ #define WM8994_AIF1_SR_11K (1 << WM8994_AIF1_SR_SHIFT) /* 11.025kHz */
#define WM8994_AIF1_SR_12K (2 << WM8994_AIF1CLK_RATE_SHIFT) /* 12kHz */ #define WM8994_AIF1_SR_12K (2 << WM8994_AIF1_SR_SHIFT) /* 12kHz */
#define WM8994_AIF1_SR_16K (3 << WM8994_AIF1CLK_RATE_SHIFT) /* 16kHz */ #define WM8994_AIF1_SR_16K (3 << WM8994_AIF1_SR_SHIFT) /* 16kHz */
#define WM8994_AIF1_SR_22K (4 << WM8994_AIF1CLK_RATE_SHIFT) /* 22.05kHz */ #define WM8994_AIF1_SR_22K (4 << WM8994_AIF1_SR_SHIFT) /* 22.05kHz */
#define WM8994_AIF1_SR_24K (5 << WM8994_AIF1CLK_RATE_SHIFT) /* 24kHz */ #define WM8994_AIF1_SR_24K (5 << WM8994_AIF1_SR_SHIFT) /* 24kHz */
#define WM8994_AIF1_SR_32K (6 << WM8994_AIF1CLK_RATE_SHIFT) /* 32kHz */ #define WM8994_AIF1_SR_32K (6 << WM8994_AIF1_SR_SHIFT) /* 32kHz */
#define WM8994_AIF1_SR_44K (7 << WM8994_AIF1CLK_RATE_SHIFT) /* 44.1kHz */ #define WM8994_AIF1_SR_44K (7 << WM8994_AIF1_SR_SHIFT) /* 44.1kHz */
#define WM8994_AIF1_SR_48K (8 << WM8994_AIF1CLK_RATE_SHIFT) /* 48kHz */ #define WM8994_AIF1_SR_48K (8 << WM8994_AIF1_SR_SHIFT) /* 48kHz */
#define WM8994_AIF1_SR_88K (9 << WM8994_AIF1CLK_RATE_SHIFT) /* 88.2kHz */ #define WM8994_AIF1_SR_88K (9 << WM8994_AIF1_SR_SHIFT) /* 88.2kHz */
#define WM8994_AIF1_SR_96K (10 << WM8994_AIF1CLK_RATE_SHIFT) /* 96kHz */ #define WM8994_AIF1_SR_96K (10 << WM8994_AIF1_SR_SHIFT) /* 96kHz */
/* Bits 8-15: Reserved */ /* Bits 8-15: Reserved */
/* R529 (0x211) - AIF2 Rate /* R529 (0x211) - AIF2 Rate
@@ -1097,9 +1254,16 @@
/* R1026 (0x402) - AIF1 DAC1 Left Volume /* R1026 (0x402) - AIF1 DAC1 Left Volume
*/ */
#define WM8994_AIF1DAC1_VU (1 << 8) /* Bit 8: AIF1DAC1 input path (AIF1, TS 0) Vol Update */
#define WM8994_AIF1DAC1L_VOL_SHIFT (0) /* Bits 0-7: AIF1DAC1 (Left) input path, Digital Vol. */
#define WM8994_AIF1DAC1L_VOL_MASK (0xFF << WM8994_AIF1DAC1L_VOL_SHIFT)
/* R1027 (0x403) - AIF1 DAC1 Right Volume /* R1027 (0x403) - AIF1 DAC1 Right Volume
*/ */
#define WM8994_AIF1DAC1R_VOL_SHIFT (0) /* Bits 0-7: AIF1DAC1 (Right) input path, Digital Vol. */
#define WM8994_AIF1DAC1R_VOL_MASK (0xFF << WM8994_AIF1DAC1R_VOL_SHIFT)
/* R1028 (0x404) - AIF1 ADC2 Left Volume /* R1028 (0x404) - AIF1 ADC2 Left Volume
*/ */
@@ -1109,36 +1273,82 @@
/* R1030 (0x406) - AIF1 DAC2 Left Volume /* R1030 (0x406) - AIF1 DAC2 Left Volume
*/ */
#define WM8994_AIF1DAC2_VU (1 << 8) /* Bit 8: AIF1DAC2 input path (AIF1, TS 1) Vol Update */
#define WM8994_AIF1DAC2L_VOL_SHIFT (0) /* Bits 0-7: AIF1DAC2 (Left) input path, Digital Vol. */
#define WM8994_AIF1DAC2L_VOL_MASK (0xFF << WM8994_AIF1DAC2L_VOL_SHIFT)
/* R1031 (0x407) - AIF1 DAC2 Right Volume /* R1031 (0x407) - AIF1 DAC2 Right Volume
*/ */
#define WM8994_AIF1DAC2R_VOL_SHIFT (0) /* Bits 0-7: AIF1DAC2 (Right) input path, Digital Vol. */
#define WM8994_AIF1DAC2R_VOL_MASK (0xFF << WM8994_AIF1DAC2R_VOL_SHIFT)
/* R1040 (0x410) - AIF1 ADC1 Filters /* R1040 (0x410) - AIF1 ADC1 Filters
*/ */
/* R1041 (0x411) - AIF1 ADC2 Filters /* R1041 (0x411) - AIF1 ADC2 Filters
*/ */
#define WM8994_AIF1ADC2_HPF_CUT_MASK 0x6000 /* AIF1ADC2_HPF_CUT - [14:13] */ #define WM8994_AIF1ADC2_HPF_CUT_SHIFT (13) /* Bits 13-14: AIF1ADC2 output path (AIF1, TS 1), HPF CO */
#define WM8994_AIF1ADC2_HPF_CUT_SHIFT 13 /* AIF1ADC2_HPF_CUT - [14:13] */ #define WM8994_AIF1ADC2_HPF_CUT_MASK (3 << WM8994_AIF1ADC2_HPF_CUT_SHIFT)
#define WM8994_AIF1ADC2_HPF_CUT_WIDTH 2 /* AIF1ADC2_HPF_CUT - [14:13] */ #define WM8994_AIF1ADC2_HPF_CUT_HIFI (0 << WM8994_AIF1ADC2_HPF_CUT_SHIFT) /* Hi-fi mode (fc = 4 Hz at fs = 48kHz) */
#define WM8994_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */ #define WM8994_AIF1ADC2_HPF_CUT_VOICE1 (1 << WM8994_AIF1ADC2_HPF_CUT_SHIFT) /* Voice mode 1 (fc = 127 Hz at fs = 8kHz) */
#define WM8994_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */ #define WM8994_AIF1ADC2_HPF_CUT_VOICE2 (2 << WM8994_AIF1ADC2_HPF_CUT_SHIFT) /* Voice mode 2 (fc = 130 Hz at fs = 8kHz) */
#define WM8994_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */ #define WM8994_AIF1ADC2_HPF_CUT_VOICE3 (3 << WM8994_AIF1ADC2_HPF_CUT_SHIFT) /* Voice mode 3 (fc = 267 Hz at fs = 8kHz) */
#define WM8994_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */ #define WM8994_AIF1ADC2L_HPF (1 << 12) /* Bit 12: AIF1ADC2 (Left) output path (AIF1, TS 1) Dig. HPF */
#define WM8994_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */ #define WM8994_AIF1ADC2L_HPF_DISABLE (0) /* Disable */
#define WM8994_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */ #define WM8994_AIF1ADC2L_HPF_ENABLE (WM8994_AIF1ADC2L_HPF) /* Enable */
#define WM8994_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */ #define WM8994_AIF1ADC2R_HPF (1 << 11) /* Bit 11: AIF1ADC2 (Right) output path (AIF1, TS 1) Dig. HPF */
#define WM8994_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */ #define WM8994_AIF1ADC2R_HPF_DISABLE (0) /* Disable */
#define WM8994_AIF1ADC2R_HPF_ENABLE (WM8994_AIF1ADC2R_HPF) /* Enable */
/* R1056 (0x420) - AIF1 DAC1 Filters (1) /* R1056 (0x420) - AIF1 DAC1 Filters (1)
*/ */
#define WM8994_AIF1DAC1_MUTE (1 << 9) /* Bit 9: AIF1DAC1 input path (AIF1, TS 0) Soft Mute Control */
#define WM8994_AIF1DAC1_MUTE_UNMUTE (0) /* Un-mute */
#define WM8994_AIF1DAC1_MUTE_MUTE (WM8994_AIF1DAC1_MUTE) /* Mute */
#define WM8994_AIF1DAC1_MONO (1 << 7) /* Bit 7: AIF1DAC1 input path (AIF1, TS 0) Mono Mix Control */
#define WM8994_AIF1DAC1_MONO_DISABLE (0) /* Disabled */
#define WM8994_AIF1DAC1_MONO_ENABLE (WM8994_AIF1DAC1_MONO) /* Enabled */
#define WM8994_AIF1DAC1_MUTERATE (1 << 5) /* Bit 5: AIF1DAC1 input path (AIF1, TS 0) Soft Mute Ramp Rate */
#define WM8994_AIF1DAC1_MUTERATE_FAST (0) /* Fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48kHz */
#define WM8994_AIF1DAC1_MUTERATE_SLOW (WM8994_AIF1DAC1_MUTERATE) /* Slow ramp (fs/32, maximum ramp time is 171ms at fs=48kHz */
#define WM8994_AIF1DAC1_UNMUTE_RAMP (1 << 4) /* Bit 4: AIF1DAC1 input path (AIF1, TS 0) Unmute Ramp select */
#define WM8994_AIF1DAC1_UNMUTE_RAMP_IMMEDIATE (0) /* Volume change immediately to AIF1DAC1L_VOL */
#define WM8994_AIF1DAC1_UNMUTE_RAMP_GRADUAL (WM8994_AIF1DAC1_UNMUTE_RAMP) /* Volume change gradually to AIF1DAC1R_VOL */
#define WM8994_AIF1DAC1_DEEMP_SHIFT (1) /* Bit 1-2: AIF1DAC1 input path (AIF1, TS 0), De-Emphasis */
#define WM8994_AIF1DAC1_DEEMP_MASK (3 << WM8994_AIF1DAC1_DEEMP_SHIFT)
#define WM8994_AIF1DAC1_DEEMP_NO (0 << WM8994_AIF1DAC1_DEEMP_SHIFT) /* No de-emphasis */
#define WM8994_AIF1DAC1_DEEMP_32KHZ (1 << WM8994_AIF1DAC1_DEEMP_SHIFT) /* 32kHz sample rate */
#define WM8994_AIF1DAC1_DEEMP_44KHZ (2 << WM8994_AIF1DAC1_DEEMP_SHIFT) /* 44.1kHz sample rate */
#define WM8994_AIF1DAC1_DEEMP_48KHZ (3 << WM8994_AIF1DAC1_DEEMP_SHIFT) /* 48kHz sample rate*/
/* R1057 (0x421) - AIF1 DAC1 Filters (2) /* R1057 (0x421) - AIF1 DAC1 Filters (2)
*/ */
/* R1058 (0x422) - AIF1 DAC2 Filters (1) /* R1058 (0x422) - AIF1 DAC2 Filters (1)
*/ */
#define WM8994_AIF1DAC2_MUTE (1 << 9) /* Bit 9: AIF1DAC2 input path (AIF1, TS 1) Soft Mute Control */
#define WM8994_AIF1DAC2_MUTE_UNMUTE (0) /* Un-mute */
#define WM8994_AIF1DAC2_MUTE_MUTE (WM8994_AIF1DAC2_MUTE) /* Mute */
#define WM8994_AIF1DAC2_MONO (1 << 7) /* Bit 7: AIF1DAC2 input path (AIF1, TS 1) Mono Mix Control */
#define WM8994_AIF1DAC2_MONO_DISABLE (0) /* Disabled */
#define WM8994_AIF1DAC2_MONO_ENABLE (WM8994_AIF1DAC2_MONO) /* Enabled */
#define WM8994_AIF1DAC2_MUTERATE (1 << 5) /* Bit 5: AIF1DAC2 input path (AIF1, TS 1) Soft Mute Ramp Rate */
#define WM8994_AIF1DAC2_MUTERATE_FAST (0) /* Fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48kHz */
#define WM8994_AIF1DAC2_MUTERATE_SLOW (WM8994_AIF1DAC2_MUTERATE) /* Slow ramp (fs/32, maximum ramp time is 171ms at fs=48kHz */
#define WM8994_AIF1DAC2_UNMUTE_RAMP (1 << 4) /* Bit 4: AIF1DAC2 input path (AIF1, TS 1) Unmute Ramp select */
#define WM8994_AIF1DAC2_UNMUTE_RAMP_IMMEDIATE (0) /* Volume change immediately to AIF1DAC1L_VOL */
#define WM8994_AIF1DAC2_UNMUTE_RAMP_GRADUAL (WM8994_AIF1DAC2_UNMUTE_RAMP) /* Volume change gradually to AIF1DAC1R_VOL */
#define WM8994_AIF1DAC2_DEEMP_SHIFT (1) /* Bit 1-2: AIF1DAC2 input path (AIF1, TS 1), De-Emphasis */
#define WM8994_AIF1DAC2_DEEMP_MASK (3 << WM8994_AIF1DAC2_DEEMP_SHIFT)
#define WM8994_AIF1DAC2_DEEMP_NO (0 << WM8994_AIF1DAC2_DEEMP_SHIFT) /* No de-emphasis */
#define WM8994_AIF1DAC2_DEEMP_32KHZ (1 << WM8994_AIF1DAC2_DEEMP_SHIFT) /* 32kHz sample rate */
#define WM8994_AIF1DAC2_DEEMP_44KHZ (2 << WM8994_AIF1DAC2_DEEMP_SHIFT) /* 44.1kHz sample rate */
#define WM8994_AIF1DAC2_DEEMP_48KHZ (3 << WM8994_AIF1DAC2_DEEMP_SHIFT) /* 48kHz sample rate*/
/* R1059 (0x423) - AIF1 DAC2 Filters (2) /* R1059 (0x423) - AIF1 DAC2 Filters (2)
*/ */
@@ -1425,6 +1635,11 @@
/* R1539 (0x603) - DAC2 Mixer Volumes /* R1539 (0x603) - DAC2 Mixer Volumes
*/ */
#define WM8994_ADCR_DAC2_VOL_SHIFT (5) /* Bits 5-8: Sidetone STR to DAC2L and DAC2R Volume */
#define WM8994_ADCR_DAC2_VOL_MASK (0xF << WM8994_ADCR_DAC2_VOL_SHIFT) /* 0000 = -36 DB, 1100 = 0dB */
#define WM8994_ADCL_DAC2_VOL_SHIFT (0) /* Bits 0-3: Sidetone STL to DAC2L and DAC2R Volume */
#define WM8994_ADCL_DAC2_VOL_MASK (0xF << WM8994_ADCL_DAC2_VOL_SHIFT /* 0000 = -36 DB, 1100 = 0dB */
/* R1540 (0x604) - DAC2 Left Mixer Routing /* R1540 (0x604) - DAC2 Left Mixer Routing
*/ */
@@ -1462,15 +1677,41 @@
/* R1552 (0x610) - DAC1 Left Volume /* R1552 (0x610) - DAC1 Left Volume
*/ */
#define WM8994_DAC1L_MUTE (1 << 9) /* Bit 9: DAC1L Soft Mute Control */
#define WM8994_DAC1L_MUTE_UNMUTE (0) /* DAC Un-mute */
#define WM8994_DAC1L_MUTE_MUTE (WM8994_DAC1L_MUTE) /* DAC Mute */
#define WM8994_DAC1_VU (1 << 8) /* Bit 8: DAC1L and DAC1R Volume Update */
#define WM8994_DAC1L_VOL_SHIFT (0) /* Bits 0-7: DAC1L Digital Volume */
#define WM8994_DAC1L_VOL_MASK (0xFF << WM8994_DAC1L_VOL_SHIFT)
/* R1553 (0x611) - DAC1 Right Volume /* R1553 (0x611) - DAC1 Right Volume
*/ */
#define WM8994_DAC1R_MUTE (1 << 9) /* Bit 9: DAC1R Soft Mute Control */
#define WM8994_DAC1R_MUTE_UNMUTE (0) /* DAC Un-mute */
#define WM8994_DAC1R_MUTE_MUTE (WM8994_DAC1L_MUTE) /* DAC Mute */
#define WM8994_DAC1R_VOL_SHIFT (0) /* Bits 0-7: DAC1R Digital Volume */
#define WM8994_DAC1R_VOL_MASK (0xFF << WM8994_DAC1R_VOL_SHIFT)
/* R1554 (0x612) - DAC2 Left Volume /* R1554 (0x612) - DAC2 Left Volume
*/ */
#define WM8994_DAC2L_MUTE (1 << 9) /* Bit 9: DAC2L Soft Mute Control */
#define WM8994_DAC2L_MUTE_UNMUTE (0) /* DAC Un-mute */
#define WM8994_DAC2L_MUTE_MUTE (WM8994_DAC2L_MUTE) /* DAC Mute */
#define WM8994_DAC2_VU (1 << 8) /* Bit 8: DAC2L and DAC2R Volume Update */
#define WM8994_DAC2L_VOL_SHIFT (0) /* Bits 0-7: DAC2L Digital Volume */
#define WM8994_DAC2L_VOL_MASK (0xFF << WM8994_DAC2L_VOL_SHIFT)
/* R1555 (0x613) - DAC2 Right Volume /* R1555 (0x613) - DAC2 Right Volume
*/ */
#define WM8994_DAC2R_MUTE (1 << 9) /* Bit 9: DAC2R Soft Mute Control */
#define WM8994_DAC2R_MUTE_UNMUTE (0) /* DAC Un-mute */
#define WM8994_DAC2R_MUTE_MUTE (WM8994_DAC2R_MUTE) /* DAC Mute */
#define WM8994_DAC2R_VOL_SHIFT (0) /* Bits 0-7: DAC2R Digital Volume */
#define WM8994_DAC2R_VOL_MASK (0xFF << WM8994_DAC2R_VOL_SHIFT)
/* R1556 (0x614) - DAC Softmute /* R1556 (0x614) - DAC Softmute
*/ */
@@ -1539,6 +1780,9 @@
#define WM8994_BCLK_MAXDIV 30 #define WM8994_BCLK_MAXDIV 30
#define WM8994_NFLLRATIO 30 #define WM8994_NFLLRATIO 30
#define WM8994_FRAMELEN8 16 /* Bits per frame for 8-bit data */
#define WM8994_FRAMELEN16 32 /* Bits per frame for 16-bit data */
/* Commonly defined and redefined macros */ /* Commonly defined and redefined macros */
#ifndef MIN #ifndef MIN