diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a37e03aa694..37b632f9aeb 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -91,6 +91,14 @@ config ARCH_CHIP_IMX8 ---help--- NXP i.MX8 (ARMv8a) applications processors +config ARCH_CHIP_IMX9 + bool "NXP i.MX9 Platform (ARMv8.2a)" + select ARCH_HAVE_ADDRENV + select ARCH_HAVE_IRQTRIGGER + select ARCH_NEED_ADDRENV_MAPPING + ---help--- + NXP i.MX9 (ARMv8.2a) applications processors + config ARCH_CHIP_ARM64_CUSTOM bool "Custom ARM64 chip" select ARCH_CHIP_CUSTOM @@ -181,6 +189,18 @@ config ARCH_CORTEX_A53 select ARCH_HAVE_TESTSET select ARM_HAVE_NEON +config ARCH_CORTEX_A55 + bool + default n + select ARCH_ARMV8A + select ARCH_HAVE_TRUSTZONE + select ARCH_DCACHE + select ARCH_ICACHE + select ARCH_HAVE_MMU + select ARCH_HAVE_FPU + select ARCH_HAVE_TESTSET + select ARM_HAVE_NEON + config ARCH_CORTEX_A57 bool default n @@ -229,6 +249,7 @@ config ARCH_CHIP default "goldfish" if ARCH_CHIP_GOLDFISH default "fvp-v8r" if ARCH_CHIP_FVP_ARMV8R default "imx8" if ARCH_CHIP_IMX8 + default "imx9" if ARCH_CHIP_IMX9 config ARM_HAVE_NEON bool @@ -311,6 +332,10 @@ if ARCH_CHIP_IMX8 source "arch/arm64/src/imx8/Kconfig" endif +if ARCH_CHIP_IMX9 +source "arch/arm64/src/imx9/Kconfig" +endif + if ARCH_CHIP_GOLDFISH source "arch/arm64/src/goldfish/Kconfig" endif diff --git a/arch/arm64/include/imx9/chip.h b/arch/arm64/include/imx9/chip.h new file mode 100644 index 00000000000..b5b46f8ce10 --- /dev/null +++ b/arch/arm64/include/imx9/chip.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/arm64/include/imx9/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_INCLUDE_IMX9_CHIP_H +#define __ARCH_ARM64_INCLUDE_IMX9_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of bytes in x kibibytes/mebibytes/gibibytes */ + +#define KB(x) ((x) << 10) +#define MB(x) (KB(x) << 10) +#define GB(x) (MB(UINT64_C(x)) << 10) + +#if defined(CONFIG_ARCH_CHIP_IMX93) + +#if CONFIG_ARM_GIC_VERSION == 3 || CONFIG_ARM_GIC_VERSION == 4 + +#define CONFIG_GICD_BASE 0x48000000 +#define CONFIG_GICR_BASE 0x48040000 +#define CONFIG_GICR_OFFSET 0x20000 + +#else + +#error CONFIG_ARM_GIC_VERSION should be 2, 3 or 4 + +#endif /* CONFIG_ARM_GIC_VERSION */ + +#define CONFIG_RAMBANK1_ADDR 0x80000000 +#define CONFIG_RAMBANK1_SIZE MB(128) + +#define CONFIG_DEVICEIO_BASEADDR 0x40000000 +#define CONFIG_DEVICEIO_SIZE MB(512) + +#define MPID_TO_CLUSTER_ID(mpid) ((mpid) & ~0xff) + +#endif + +/**************************************************************************** + * Assembly Macros + ****************************************************************************/ + +#ifdef __ASSEMBLY__ + +.macro get_cpu_id xreg0 + mrs \xreg0, mpidr_el1 + ubfx \xreg0, \xreg0, #0, #8 +.endm + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM64_INCLUDE_IMX9_CHIP_H */ diff --git a/arch/arm64/include/imx9/imx93_irq.h b/arch/arm64/include/imx9/imx93_irq.h new file mode 100644 index 00000000000..cc3e24d7078 --- /dev/null +++ b/arch/arm64/include/imx9/imx93_irq.h @@ -0,0 +1,298 @@ +/**************************************************************************** + * arch/arm64/include/imx9/imx93_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_INCLUDE_IMX9_IMX93_IRQ_H +#define __ARCH_ARM64_INCLUDE_IMX9_IMX93_IRQ_H + +#define IMX9_IRQ_RESERVED32 (IMX9_IRQ_EXT + 0) /* Exception condition notification while boot */ +#define IMX9_IRQ_RESERVED33 (IMX9_IRQ_EXT + 1) /* DAP interrupt */ +#define IMX9_IRQ_RESERVED34 (IMX9_IRQ_EXT + 2) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED35 (IMX9_IRQ_EXT + 3) /* CTI trigger outputs from CM33 platform */ +#define IMX9_IRQ_RESERVED36 (IMX9_IRQ_EXT + 4) /* CTI trigger outputs from CA55 platform */ +#define IMX9_IRQ_RESERVED37 (IMX9_IRQ_EXT + 5) /* Performance Unit Interrupts from CA55 platform */ +#define IMX9_IRQ_RESERVED38 (IMX9_IRQ_EXT + 6) /* ECC error from CA55 platform cache */ +#define IMX9_IRQ_RESERVED39 (IMX9_IRQ_EXT + 7) /* 1-bit or 2-bit ECC or Parity error from CA55 platform cache */ +#define IMX9_IRQ_CAN1 (IMX9_IRQ_EXT + 8) /* CAN1 interrupt */ +#define IMX9_IRQ_CAN1_ERROR (IMX9_IRQ_EXT + 9) /* CAN1 error interrupt */ +#define IMX9_IRQ_GPIO1_0_15 (IMX9_IRQ_EXT + 10) /* General Purpose Input/Output 1 interrupt 0 */ +#define IMX9_IRQ_GPIO1_16_31 (IMX9_IRQ_EXT + 11) /* General Purpose Input/Output 1 interrupt 1 */ +#define IMX9_IRQ_I3C1 (IMX9_IRQ_EXT + 12) /* Improved Inter-Integrated Circuit 1 interrupt */ +#define IMX9_IRQ_LPI2C1 (IMX9_IRQ_EXT + 13) /* Low Power Inter-Integrated Circuit module 1 */ +#define IMX9_IRQ_LPI2C2 (IMX9_IRQ_EXT + 14) /* Low Power Inter-Integrated Circuit module 2 */ +#define IMX9_IRQ_LPIT1 (IMX9_IRQ_EXT + 15) /* Low Power Periodic Interrupt Timer 1 */ +#define IMX9_IRQ_LPSPI1 (IMX9_IRQ_EXT + 16) /* Low Power Serial Peripheral Interface 1 */ +#define IMX9_IRQ_LPSPI2 (IMX9_IRQ_EXT + 17) /* Low Power Serial Peripheral Interface 2 */ +#define IMX9_IRQ_LPTMR1 (IMX9_IRQ_EXT + 18) /* Low Power Timer 1 */ +#define IMX9_IRQ_LPUART1 (IMX9_IRQ_EXT + 19) /* Low Power UART 1 */ +#define IMX9_IRQ_LPUART2 (IMX9_IRQ_EXT + 20) /* Low Power UART 2 */ +#define IMX9_IRQ_MU1_A (IMX9_IRQ_EXT + 21) /* Messaging Unit 1 - Side A (to communicate with M7 core) */ +#define IMX9_IRQ_MU1_B (IMX9_IRQ_EXT + 22) /* Messaging Unit 1 - Side B (to communicate with M33 core) */ +#define IMX9_IRQ_MU2_A (IMX9_IRQ_EXT + 23) /* Messaging Unit 2 - Side A (to communicate with M7 core) */ +#define IMX9_IRQ_MU2_B (IMX9_IRQ_EXT + 24) /* Messaging Unit 2 - Side B (to communicate with A55 core) */ +#define IMX9_IRQ_RESERVED57 (IMX9_IRQ_EXT + 25) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED58 (IMX9_IRQ_EXT + 26) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED59 (IMX9_IRQ_EXT + 27) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED60 (IMX9_IRQ_EXT + 28) /* Edgelock Trust MUA RX full interrupt */ +#define IMX9_IRQ_RESERVED61 (IMX9_IRQ_EXT + 29) /* Edgelock Trust MUA TX empty interrupt */ +#define IMX9_IRQ_RESERVED62 (IMX9_IRQ_EXT + 30) /* Edgelock Apps Core MUA RX full interrupt */ +#define IMX9_IRQ_RESERVED63 (IMX9_IRQ_EXT + 31) /* Edgelock Apps Core MUA TX empty interrupt */ +#define IMX9_IRQ_RESERVED64 (IMX9_IRQ_EXT + 32) /* Edgelock Realtime Core MUA RX full interrupt */ +#define IMX9_IRQ_RESERVED65 (IMX9_IRQ_EXT + 33) /* Edgelock Realtime Core MUA TX empty interrupt */ +#define IMX9_IRQ_RESERVED66 (IMX9_IRQ_EXT + 34) /* Edgelock secure interrupt */ +#define IMX9_IRQ_RESERVED67 (IMX9_IRQ_EXT + 35) /* Edgelock non-secure interrupt */ +#define IMX9_IRQ_TPM1 (IMX9_IRQ_EXT + 36) /* Timer PWM module 1 */ +#define IMX9_IRQ_TPM2 (IMX9_IRQ_EXT + 37) /* Timer PWM module 2 */ +#define IMX9_IRQ_WDOG1 (IMX9_IRQ_EXT + 38) /* Watchdog 1 Interrupt */ +#define IMX9_IRQ_WDOG2 (IMX9_IRQ_EXT + 39) /* Watchdog 2 Interrupt */ +#define IMX9_IRQ_TRDC (IMX9_IRQ_EXT + 40) /* AONMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED73 (IMX9_IRQ_EXT + 41) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED74 (IMX9_IRQ_EXT + 42) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED75 (IMX9_IRQ_EXT + 43) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED76 (IMX9_IRQ_EXT + 44) /* Reserved interrupt */ +#define IMX9_IRQ_SAI1 (IMX9_IRQ_EXT + 45) /* Serial Audio Interface 1 */ +#define IMX9_IRQ_RESERVED78 (IMX9_IRQ_EXT + 46) /* M33 PS Tag/Data Parity Error */ +#define IMX9_IRQ_RESERVED79 (IMX9_IRQ_EXT + 47) /* M33 TCM ECC interrupt */ +#define IMX9_IRQ_RESERVED80 (IMX9_IRQ_EXT + 48) /* M33 TCM Error interrupt */ +#define IMX9_IRQ_RESERVED81 (IMX9_IRQ_EXT + 49) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED82 (IMX9_IRQ_EXT + 50) /* Reserved interrupt */ +#define IMX9_IRQ_CAN2 (IMX9_IRQ_EXT + 51) /* CAN2 interrupt */ +#define IMX9_IRQ_CAN2_ERROR (IMX9_IRQ_EXT + 52) /* CAN2 error interrupt */ +#define IMX9_IRQ_FLEXIO1 (IMX9_IRQ_EXT + 53) /* Flexible IO 1 interrupt */ +#define IMX9_IRQ_FLEXIO2 (IMX9_IRQ_EXT + 54) /* Flexible IO 2 interrupt */ +#define IMX9_IRQ_FLEXSPI1 (IMX9_IRQ_EXT + 55) /* FlexSPI controller interface interrupt 1 */ +#define IMX9_IRQ_RESERVED88 (IMX9_IRQ_EXT + 56) /* Reserved interrupt */ +#define IMX9_IRQ_GPIO2_0_15 (IMX9_IRQ_EXT + 57) /* General Purpose Input/Output 2 interrupt 0 */ +#define IMX9_IRQ_GPIO2_16_31 (IMX9_IRQ_EXT + 58) /* General Purpose Input/Output 2 interrupt 1 */ +#define IMX9_IRQ_GPIO3_0_15 (IMX9_IRQ_EXT + 59) /* General Purpose Input/Output 3 interrupt 0 */ +#define IMX9_IRQ_GPIO3_16_31 (IMX9_IRQ_EXT + 60) /* General Purpose Input/Output 3 interrupt 1 */ +#define IMX9_IRQ_I3C2 (IMX9_IRQ_EXT + 61) /* Improved Inter-Integrated Circuit 2 interrupt */ +#define IMX9_IRQ_LPI2C3 (IMX9_IRQ_EXT + 62) /* Low Power Inter-Integrated Circuit module 3 */ +#define IMX9_IRQ_LPI2C4 (IMX9_IRQ_EXT + 63) /* Low Power Inter-Integrated Circuit module 4 */ +#define IMX9_IRQ_LPIT2 (IMX9_IRQ_EXT + 64) /* Low Power Periodic Interrupt Timer 2 */ +#define IMX9_IRQ_LPSPI3 (IMX9_IRQ_EXT + 65) /* Low Power Serial Peripheral Interface 3 */ +#define IMX9_IRQ_LPSPI4 (IMX9_IRQ_EXT + 66) /* Low Power Serial Peripheral Interface 4 */ +#define IMX9_IRQ_LPTMR2 (IMX9_IRQ_EXT + 67) /* Low Power Timer 2 */ +#define IMX9_IRQ_LPUART3 (IMX9_IRQ_EXT + 68) /* Low Power UART 3 */ +#define IMX9_IRQ_LPUART4 (IMX9_IRQ_EXT + 69) /* Low Power UART 4 */ +#define IMX9_IRQ_LPUART5 (IMX9_IRQ_EXT + 70) /* Low Power UART 5 */ +#define IMX9_IRQ_LPUART6 (IMX9_IRQ_EXT + 71) /* Low Power UART 6 */ +#define IMX9_IRQ_RESERVED104 (IMX9_IRQ_EXT + 72) /* MTR Master error interrupt */ +#define IMX9_IRQ_RESERVED105 (IMX9_IRQ_EXT + 73) /* BBNSM Non-Secure interrupt */ +#define IMX9_IRQ_RESERVED106 (IMX9_IRQ_EXT + 74) /* System Counter compare interrupt */ +#define IMX9_IRQ_TPM3 (IMX9_IRQ_EXT + 75) /* Timer PWM module 3 */ +#define IMX9_IRQ_TPM4 (IMX9_IRQ_EXT + 76) /* Timer PWM module 4 */ +#define IMX9_IRQ_TPM5 (IMX9_IRQ_EXT + 77) /* Timer PWM module 5 */ +#define IMX9_IRQ_TPM6 (IMX9_IRQ_EXT + 78) /* Timer PWM module 6 */ +#define IMX9_IRQ_WDOG3 (IMX9_IRQ_EXT + 79) /* Watchdog 3 Interrupt */ +#define IMX9_IRQ_WDOG4 (IMX9_IRQ_EXT + 80) /* Watchdog 4 Interrupt */ +#define IMX9_IRQ_WDOG5 (IMX9_IRQ_EXT + 81) /* Watchdog 5 Interrupt */ +#define IMX9_IRQ_RESERVED114 (IMX9_IRQ_EXT + 82) /* WAKEUPMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_TEMPMON (IMX9_IRQ_EXT + 83) /* TempSensor interrupt */ +#define IMX9_IRQ_RESERVED116 (IMX9_IRQ_EXT + 84) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED117 (IMX9_IRQ_EXT + 85) /* Reserved interrupt */ +#define IMX9_IRQ_USDHC1 (IMX9_IRQ_EXT + 86) /* ultra Secure Digital Host Controller interrupt 1 */ +#define IMX9_IRQ_USDHC2 (IMX9_IRQ_EXT + 87) /* ultra Secure Digital Host Controller interrupt 2 */ +#define IMX9_IRQ_RESERVED120 (IMX9_IRQ_EXT + 88) /* MEGAMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED121 (IMX9_IRQ_EXT + 89) /* NIC_WRAPPER TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED122 (IMX9_IRQ_EXT + 90) /* DRAM controller Performance Monitor Interrupt */ +#define IMX9_IRQ_RESERVED123 (IMX9_IRQ_EXT + 91) /* DRAM controller Critical Interrupt */ +#define IMX9_IRQ_RESERVED124 (IMX9_IRQ_EXT + 92) /* DRAM Phy Critical Interrupt */ +#define IMX9_IRQ_RESERVED125 (IMX9_IRQ_EXT + 93) /* Reserved interrupt */ +#define IMX9_IRQ_DMA3_ERROR (IMX9_IRQ_EXT + 94) /* eDMA1 error interrupt */ +#define IMX9_IRQ_DMA3_0 (IMX9_IRQ_EXT + 95) /* eDMA1 channel 0 interrupt */ +#define IMX9_IRQ_DMA3_1 (IMX9_IRQ_EXT + 96) /* eDMA1 channel 1 interrupt */ +#define IMX9_IRQ_DMA3_2 (IMX9_IRQ_EXT + 97) /* eDMA1 channel 2 interrupt */ +#define IMX9_IRQ_DMA3_3 (IMX9_IRQ_EXT + 98) /* eDMA1 channel 3 interrupt */ +#define IMX9_IRQ_DMA3_4 (IMX9_IRQ_EXT + 99) /* eDMA1 channel 4 interrupt */ +#define IMX9_IRQ_DMA3_5 (IMX9_IRQ_EXT + 100) /* eDMA1 channel 5 interrupt */ +#define IMX9_IRQ_DMA3_6 (IMX9_IRQ_EXT + 101) /* eDMA1 channel 6 interrupt */ +#define IMX9_IRQ_DMA3_7 (IMX9_IRQ_EXT + 102) /* eDMA1 channel 7 interrupt */ +#define IMX9_IRQ_DMA3_8 (IMX9_IRQ_EXT + 103) /* eDMA1 channel 8 interrupt */ +#define IMX9_IRQ_DMA3_9 (IMX9_IRQ_EXT + 104) /* eDMA1 channel 9 interrupt */ +#define IMX9_IRQ_DMA3_10 (IMX9_IRQ_EXT + 105) /* eDMA1 channel 10 interrupt */ +#define IMX9_IRQ_DMA3_11 (IMX9_IRQ_EXT + 106) /* eDMA1 channel 11 interrupt */ +#define IMX9_IRQ_DMA3_12 (IMX9_IRQ_EXT + 107) /* eDMA1 channel 12 interrupt */ +#define IMX9_IRQ_DMA3_13 (IMX9_IRQ_EXT + 108) /* eDMA1 channel 13 interrupt */ +#define IMX9_IRQ_DMA3_14 (IMX9_IRQ_EXT + 109) /* eDMA1 channel 14 interrupt */ +#define IMX9_IRQ_DMA3_15 (IMX9_IRQ_EXT + 110) /* eDMA1 channel 15 interrupt */ +#define IMX9_IRQ_DMA3_16 (IMX9_IRQ_EXT + 111) /* eDMA1 channel 16 interrupt */ +#define IMX9_IRQ_DMA3_17 (IMX9_IRQ_EXT + 112) /* eDMA1 channel 17 interrupt */ +#define IMX9_IRQ_DMA3_18 (IMX9_IRQ_EXT + 113) /* eDMA1 channel 18 interrupt */ +#define IMX9_IRQ_DMA3_19 (IMX9_IRQ_EXT + 114) /* eDMA1 channel 19 interrupt */ +#define IMX9_IRQ_DMA3_20 (IMX9_IRQ_EXT + 115) /* eDMA1 channel 20 interrupt */ +#define IMX9_IRQ_DMA3_21 (IMX9_IRQ_EXT + 116) /* eDMA1 channel 21 interrupt */ +#define IMX9_IRQ_DMA3_22 (IMX9_IRQ_EXT + 117) /* eDMA1 channel 22 interrupt */ +#define IMX9_IRQ_DMA3_23 (IMX9_IRQ_EXT + 118) /* eDMA1 channel 23 interrupt */ +#define IMX9_IRQ_DMA3_24 (IMX9_IRQ_EXT + 119) /* eDMA1 channel 24 interrupt */ +#define IMX9_IRQ_DMA3_25 (IMX9_IRQ_EXT + 120) /* eDMA1 channel 25 interrupt */ +#define IMX9_IRQ_DMA3_26 (IMX9_IRQ_EXT + 121) /* eDMA1 channel 26 interrupt */ +#define IMX9_IRQ_DMA3_27 (IMX9_IRQ_EXT + 122) /* eDMA1 channel 27 interrupt */ +#define IMX9_IRQ_DMA3_28 (IMX9_IRQ_EXT + 123) /* eDMA1 channel 28 interrupt */ +#define IMX9_IRQ_DMA3_29 (IMX9_IRQ_EXT + 124) /* eDMA1 channel 29 interrupt */ +#define IMX9_IRQ_DMA3_30 (IMX9_IRQ_EXT + 125) /* eDMA1 channel 30 interrupt */ +#define IMX9_IRQ_RESERVED158 (IMX9_IRQ_EXT + 126) /* Reserved interrupt */ +#define IMX9_IRQ_DMA4_ERROR (IMX9_IRQ_EXT + 127) /* eDMA2 error interrupt */ +#define IMX9_IRQ_DMA4_0_1 (IMX9_IRQ_EXT + 128) /* eDMA2 channel 0/1 interrupt */ +#define IMX9_IRQ_DMA4_2_3 (IMX9_IRQ_EXT + 129) /* eDMA2 channel 2/3 interrupt */ +#define IMX9_IRQ_DMA4_4_5 (IMX9_IRQ_EXT + 130) /* eDMA2 channel 4/5 interrupt */ +#define IMX9_IRQ_DMA4_6_7 (IMX9_IRQ_EXT + 131) /* eDMA2 channel 6/7 interrupt */ +#define IMX9_IRQ_DMA4_8_9 (IMX9_IRQ_EXT + 132) /* eDMA2 channel 8/9 interrupt */ +#define IMX9_IRQ_DMA4_10_11 (IMX9_IRQ_EXT + 133) /* eDMA2 channel 10/11 interrupt */ +#define IMX9_IRQ_DMA4_12_13 (IMX9_IRQ_EXT + 134) /* eDMA2 channel 12/13 interrupt */ +#define IMX9_IRQ_DMA4_14_15 (IMX9_IRQ_EXT + 135) /* eDMA2 channel 14/15 interrupt */ +#define IMX9_IRQ_DMA4_16_17 (IMX9_IRQ_EXT + 136) /* eDMA2 channel 16/17 interrupt */ +#define IMX9_IRQ_DMA4_18_19 (IMX9_IRQ_EXT + 137) /* eDMA2 channel 18/19 interrupt */ +#define IMX9_IRQ_DMA4_20_21 (IMX9_IRQ_EXT + 138) /* eDMA2 channel 20/21 interrupt */ +#define IMX9_IRQ_DMA4_22_23 (IMX9_IRQ_EXT + 139) /* eDMA2 channel 22/23 interrupt */ +#define IMX9_IRQ_DMA4_24_25 (IMX9_IRQ_EXT + 140) /* eDMA2 channel 24/25 interrupt */ +#define IMX9_IRQ_DMA4_26_27 (IMX9_IRQ_EXT + 141) /* eDMA2 channel 26/27 interrupt */ +#define IMX9_IRQ_DMA4_28_29 (IMX9_IRQ_EXT + 142) /* eDMA2 channel 28/29 interrupt */ +#define IMX9_IRQ_DMA4_30_31 (IMX9_IRQ_EXT + 143) /* eDMA2 channel 30/31 interrupt */ +#define IMX9_IRQ_DMA4_32_33 (IMX9_IRQ_EXT + 144) /* eDMA2 channel 32/33 interrupt */ +#define IMX9_IRQ_DMA4_34_35 (IMX9_IRQ_EXT + 145) /* eDMA2 channel 34/35 interrupt */ +#define IMX9_IRQ_DMA4_36_37 (IMX9_IRQ_EXT + 146) /* eDMA2 channel 36/37 interrupt */ +#define IMX9_IRQ_DMA4_38_39 (IMX9_IRQ_EXT + 147) /* eDMA2 channel 38/39 interrupt */ +#define IMX9_IRQ_DMA4_40_41 (IMX9_IRQ_EXT + 148) /* eDMA2 channel 40/41 interrupt */ +#define IMX9_IRQ_DMA4_42_43 (IMX9_IRQ_EXT + 149) /* eDMA2 channel 42/43 interrupt */ +#define IMX9_IRQ_DMA4_44_45 (IMX9_IRQ_EXT + 150) /* eDMA2 channel 44/45 interrupt */ +#define IMX9_IRQ_DMA4_46_47 (IMX9_IRQ_EXT + 151) /* eDMA2 channel 46/47 interrupt */ +#define IMX9_IRQ_DMA4_48_49 (IMX9_IRQ_EXT + 152) /* eDMA2 channel 48/49 interrupt */ +#define IMX9_IRQ_DMA4_50_51 (IMX9_IRQ_EXT + 153) /* eDMA2 channel 50/51 interrupt */ +#define IMX9_IRQ_DMA4_52_53 (IMX9_IRQ_EXT + 154) /* eDMA2 channel 52/53 interrupt */ +#define IMX9_IRQ_DMA4_54_55 (IMX9_IRQ_EXT + 155) /* eDMA2 channel 54/55 interrupt */ +#define IMX9_IRQ_DMA4_56_57 (IMX9_IRQ_EXT + 156) /* eDMA2 channel 56/57 interrupt */ +#define IMX9_IRQ_DMA4_58_59 (IMX9_IRQ_EXT + 157) /* eDMA2 channel 58/59 interrupt */ +#define IMX9_IRQ_DMA4_60_61 (IMX9_IRQ_EXT + 158) /* eDMA2 channel 60/61 interrupt */ +#define IMX9_IRQ_DMA4_62_63 (IMX9_IRQ_EXT + 159) /* eDMA2 channel 62/63 interrupt */ +#define IMX9_IRQ_RESERVED192 (IMX9_IRQ_EXT + 160) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED193 (IMX9_IRQ_EXT + 161) /* Edgelock Group 1 reset source */ +#define IMX9_IRQ_RESERVED194 (IMX9_IRQ_EXT + 162) /* Edgelock Group 2 reset source */ +#define IMX9_IRQ_RESERVED195 (IMX9_IRQ_EXT + 163) /* Edgelock Group 2 reset source */ +#define IMX9_IRQ_RESERVED196 (IMX9_IRQ_EXT + 164) /* JTAGSW DAP MDM-AP SRC reset source */ +#define IMX9_IRQ_RESERVED197 (IMX9_IRQ_EXT + 165) /* JTAGC SRC reset source */ +#define IMX9_IRQ_RESERVED198 (IMX9_IRQ_EXT + 166) /* CM33 SYSREQRST SRC reset source */ +#define IMX9_IRQ_RESERVED199 (IMX9_IRQ_EXT + 167) /* CM33 LOCKUP SRC reset source */ +#define IMX9_IRQ_RESERVED200 (IMX9_IRQ_EXT + 168) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED201 (IMX9_IRQ_EXT + 169) /* Reserved interrupt */ +#define IMX9_IRQ_SAI2 (IMX9_IRQ_EXT + 170) /* Serial Audio Interface 2 */ +#define IMX9_IRQ_SAI3 (IMX9_IRQ_EXT + 171) /* Serial Audio Interface 3 */ +#define IMX9_IRQ_ISI (IMX9_IRQ_EXT + 172) /* ISI interrupt */ +#define IMX9_IRQ_RESERVED205 (IMX9_IRQ_EXT + 173) /* PXP interrupt 0 */ +#define IMX9_IRQ_RESERVED206 (IMX9_IRQ_EXT + 174) /* PXP interrupt 1 */ +#define IMX9_IRQ_CSI (IMX9_IRQ_EXT + 175) /* CSI interrupt */ +#define IMX9_IRQ_RESERVED208 (IMX9_IRQ_EXT + 176) /* LCDIF Sync Interrupt */ +#define IMX9_IRQ_DSI (IMX9_IRQ_EXT + 177) /* MIPI DSI Interrupt Request */ +#define IMX9_IRQ_RESERVED210 (IMX9_IRQ_EXT + 178) /* Machine learning processor interrupt */ +#define IMX9_IRQ_ENET_MAC0_RX_TX_D ONE1 (IMX9_IRQ_EXT + 179) /* MAC 0 Receive/ Trasmit Frame/ Buffer Done */ +#define IMX9_IRQ_ENET_MAC0_RX_TX_D ONE2 (IMX9_IRQ_EXT + 180) /* MAC 0 Receive/ Trasmit Frame/ Buffer Done */ +#define IMX9_IRQ_ENET (IMX9_IRQ_EXT + 181) /* MAC 0 IRQ */ +#define IMX9_IRQ_ENET_1588 (IMX9_IRQ_EXT + 182) /* MAC 0 1588 Timer Interrupt - synchronous */ +#define IMX9_IRQ_ENET_QOS_PMT (IMX9_IRQ_EXT + 183) /* ENET QOS PMT interrupt */ +#define IMX9_IRQ_ENET_QOS (IMX9_IRQ_EXT + 184) /* ENET QOS interrupt */ +#define IMX9_IRQ_RESERVED217 (IMX9_IRQ_EXT + 185) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED218 (IMX9_IRQ_EXT + 186) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED219 (IMX9_IRQ_EXT + 187) /* USB-1 Wake-up Interrupt */ +#define IMX9_IRQ_RESERVED220 (IMX9_IRQ_EXT + 188) /* USB-2 Wake-up Interrupt */ +#define IMX9_IRQ_GPIO4_0_15 (IMX9_IRQ_EXT + 189) /* General Purpose Input/Output 4 interrupt 0 */ +#define IMX9_IRQ_GPIO4_16_31 (IMX9_IRQ_EXT + 190) /* General Purpose Input/Output 4 interrupt 1 */ +#define IMX9_IRQ_LPSPI5 (IMX9_IRQ_EXT + 191) /* Low Power Serial Peripheral Interface 5 */ +#define IMX9_IRQ_LPSPI6 (IMX9_IRQ_EXT + 192) /* Low Power Serial Peripheral Interface 6 */ +#define IMX9_IRQ_LPSPI7 (IMX9_IRQ_EXT + 193) /* Low Power Serial Peripheral Interface 7 */ +#define IMX9_IRQ_LPSPI8 (IMX9_IRQ_EXT + 194) /* Low Power Serial Peripheral Interface 8 */ +#define IMX9_IRQ_LPI2C5 (IMX9_IRQ_EXT + 195) /* Low Power Inter-Integrated Circuit module 5 */ +#define IMX9_IRQ_LPI2C6 (IMX9_IRQ_EXT + 196) /* Low Power Inter-Integrated Circuit module 6 */ +#define IMX9_IRQ_LPI2C7 (IMX9_IRQ_EXT + 197) /* Low Power Inter-Integrated Circuit module 7 */ +#define IMX9_IRQ_LPI2C8 (IMX9_IRQ_EXT + 198) /* Low Power Inter-Integrated Circuit module 8 */ +#define IMX9_IRQ_PDM_HWVAD_ERROR (IMX9_IRQ_EXT + 199) /* PDM interrupt */ +#define IMX9_IRQ_PDM_HWVAD_EVENT (IMX9_IRQ_EXT + 200) /* PDM interrupt */ +#define IMX9_IRQ_PDM_ERROR (IMX9_IRQ_EXT + 201) /* PDM interrupt */ +#define IMX9_IRQ_PDM_EVENT (IMX9_IRQ_EXT + 202) /* PDM interrupt */ +#define IMX9_IRQ_RESERVED235 (IMX9_IRQ_EXT + 203) /* AUDIO XCVR interrupt */ +#define IMX9_IRQ_RESERVED236 (IMX9_IRQ_EXT + 204) /* AUDIO XCVR interrupt */ +#define IMX9_IRQ_USDHC3 (IMX9_IRQ_EXT + 205) /* ultra Secure Digital Host Controller interrupt 3 */ +#define IMX9_IRQ_RESERVED238 (IMX9_IRQ_EXT + 206) /* OCRAM MECC interrupt */ +#define IMX9_IRQ_RESERVED239 (IMX9_IRQ_EXT + 207) /* OCRAM MECC interrupt */ +#define IMX9_IRQ_RESERVED240 (IMX9_IRQ_EXT + 208) /* HSIOMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED241 (IMX9_IRQ_EXT + 209) /* MEDIAMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_LPUART7 (IMX9_IRQ_EXT + 210) /* Low Power UART 7 */ +#define IMX9_IRQ_LPUART8 (IMX9_IRQ_EXT + 211) /* Low Power UART 8 */ +#define IMX9_IRQ_RESERVED244 (IMX9_IRQ_EXT + 212) /* CM33 MCM interrupt */ +#define IMX9_IRQ_RESERVED245 (IMX9_IRQ_EXT + 213) /* SFA interrupt */ +#define IMX9_IRQ_RESERVED246 (IMX9_IRQ_EXT + 214) /* GIC600 INTERRUPT */ +#define IMX9_IRQ_RESERVED247 (IMX9_IRQ_EXT + 215) /* GIC600 INTERRUPT */ +#define IMX9_IRQ_RESERVED248 (IMX9_IRQ_EXT + 216) /* GIC600 INTERRUPT */ +#define IMX9_IRQ_RESERVED249 (IMX9_IRQ_EXT + 217) /* ADC interrupt */ +#define IMX9_IRQ_RESERVED250 (IMX9_IRQ_EXT + 218) /* ADC interrupt */ +#define IMX9_IRQ_RESERVED251 (IMX9_IRQ_EXT + 219) /* ADC interrupt */ +#define IMX9_IRQ_RESERVED252 (IMX9_IRQ_EXT + 220) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED253 (IMX9_IRQ_EXT + 221) /* I3C1 wakeup irq after double sync */ +#define IMX9_IRQ_RESERVED254 (IMX9_IRQ_EXT + 222) /* I3C2 wakeup irq after double sync */ +#define IMX9_IRQ_RESERVED255 (IMX9_IRQ_EXT + 223) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED256 (IMX9_IRQ_EXT + 224) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED257 (IMX9_IRQ_EXT + 225) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED258 (IMX9_IRQ_EXT + 226) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED259 (IMX9_IRQ_EXT + 227) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED260 (IMX9_IRQ_EXT + 228) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED261 (IMX9_IRQ_EXT + 229) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED262 (IMX9_IRQ_EXT + 230) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED263 (IMX9_IRQ_EXT + 231) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED264 (IMX9_IRQ_EXT + 232) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED265 (IMX9_IRQ_EXT + 233) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED266 (IMX9_IRQ_EXT + 234) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED267 (IMX9_IRQ_EXT + 235) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED268 (IMX9_IRQ_EXT + 236) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED269 (IMX9_IRQ_EXT + 237) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED270 (IMX9_IRQ_EXT + 238) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED271 (IMX9_IRQ_EXT + 239) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED272 (IMX9_IRQ_EXT + 240) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED273 (IMX9_IRQ_EXT + 241) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED274 (IMX9_IRQ_EXT + 242) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED275 (IMX9_IRQ_EXT + 243) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED276 (IMX9_IRQ_EXT + 244) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED277 (IMX9_IRQ_EXT + 245) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED278 (IMX9_IRQ_EXT + 246) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED279 (IMX9_IRQ_EXT + 247) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED280 (IMX9_IRQ_EXT + 248) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED281 (IMX9_IRQ_EXT + 249) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED282 (IMX9_IRQ_EXT + 250) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED283 (IMX9_IRQ_EXT + 251) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED284 (IMX9_IRQ_EXT + 252) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED285 (IMX9_IRQ_EXT + 253) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED286 (IMX9_IRQ_EXT + 254) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED287 (IMX9_IRQ_EXT + 255) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED288 (IMX9_IRQ_EXT + 256) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED289 (IMX9_IRQ_EXT + 257) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED290 (IMX9_IRQ_EXT + 258) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED291 (IMX9_IRQ_EXT + 259) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED292 (IMX9_IRQ_EXT + 260) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED293 (IMX9_IRQ_EXT + 261) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED294 (IMX9_IRQ_EXT + 262) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED295 (IMX9_IRQ_EXT + 263) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED296 (IMX9_IRQ_EXT + 264) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED297 (IMX9_IRQ_EXT + 265) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED298 (IMX9_IRQ_EXT + 266) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED299 (IMX9_IRQ_EXT + 267) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED300 (IMX9_IRQ_EXT + 268) /* ADC Asynchronous Interrupt */ + +/* Total amount of entries in system vector table */ + +#define NR_IRQS (301) + +#endif /* __ARCH_ARM64_INCLUDE_IMX9_IMX93_IRQ_H */ diff --git a/arch/arm64/include/imx9/irq.h b/arch/arm64/include/imx9/irq.h new file mode 100644 index 00000000000..5e96f56a795 --- /dev/null +++ b/arch/arm64/include/imx9/irq.h @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/arm64/include/imx9/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM64_INCLUDE_IMX9_IRQ_H +#define __ARCH_ARM64_INCLUDE_IMX9_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include +#else +# error "Unrecognized i.MX9 architecture" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX9_IRQ_SOFTWARE0 (0) /* Cortex-A55 Software Generated Interrupt 0 */ +#define IMX9_IRQ_SOFTWARE1 (1) /* Cortex-A55 Software Generated Interrupt 1 */ +#define IMX9_IRQ_SOFTWARE2 (2) /* Cortex-A55 Software Generated Interrupt 2 */ +#define IMX9_IRQ_SOFTWARE3 (3) /* Cortex-A55 Software Generated Interrupt 3 */ +#define IMX9_IRQ_SOFTWARE4 (4) /* Cortex-A55 Software Generated Interrupt 4 */ +#define IMX9_IRQ_SOFTWARE5 (5) /* Cortex-A55 Software Generated Interrupt 5 */ +#define IMX9_IRQ_SOFTWARE6 (6) /* Cortex-A55 Software Generated Interrupt 6 */ +#define IMX9_IRQ_SOFTWARE7 (7) /* Cortex-A55 Software Generated Interrupt 7 */ +#define IMX9_IRQ_SOFTWARE8 (8) /* Cortex-A55 Software Generated Interrupt 8 */ +#define IMX9_IRQ_SOFTWARE9 (9) /* Cortex-A55 Software Generated Interrupt 9 */ +#define IMX9_IRQ_SOFTWARE10 (10) /* Cortex-A55 Software Generated Interrupt 10 */ +#define IMX9_IRQ_SOFTWARE11 (11) /* Cortex-A55 Software Generated Interrupt 11 */ +#define IMX9_IRQ_SOFTWARE12 (12) /* Cortex-A55 Software Generated Interrupt 12 */ +#define IMX9_IRQ_SOFTWARE13 (13) /* Cortex-A55 Software Generated Interrupt 13 */ +#define IMX9_IRQ_SOFTWARE14 (14) /* Cortex-A55 Software Generated Interrupt 14 */ +#define IMX9_IRQ_SOFTWARE15 (15) /* Cortex-A55 Software Generated Interrupt 15 */ +#define IMX9_IRQ_VIRTUALMAINTENANCE (25) /* Cortex-A55 Virtual Maintenance Interrupt */ +#define IMX9_IRQ_HYPERVISORTIMER (26) /* Cortex-A55 Hypervisor Timer Interrupt */ +#define IMX9_IRQ_VIRTUALTIMER (27) /* Cortex-A55 Virtual Timer Interrupt */ +#define IMX9_IRQ_LEGACYFASTINT (28) /* Cortex-A55 Legacy nFIQ signal Interrupt */ +#define IMX9_IRQ_SECUREPHYTIMER (29) /* Cortex-A55 Secure Physical Timer Interrupt */ +#define IMX9_IRQ_NONSECUREPHYTIMER (30) /* Cortex-A55 Non-secure Physical Timer Interrupt */ +#define IMX9_IRQ_LEGACYIRQ (31) /* Cortex-A55 Legacy nIRQ Interrupt */ + +#define IMX9_IRQ_EXT (32) /* Vector number of the first ext int */ + +#endif /* __ARCH_ARM64_INCLUDE_IMX9_IRQ_H */ diff --git a/arch/arm64/src/imx9/Kconfig b/arch/arm64/src/imx9/Kconfig new file mode 100644 index 00000000000..e0b72de272a --- /dev/null +++ b/arch/arm64/src/imx9/Kconfig @@ -0,0 +1,31 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_IMX9 + +menu "i.MX9 Chip Selection" + +choice + prompt "i.MX9 Core Configuration" + default ARCH_CHIP_IMX93 + +config ARCH_CHIP_IMX93 + bool "i.MX9 Application Processor" + select ARCH_HAVE_MULTICPU + select ARMV8A_HAVE_GICv3 + select ARCH_CORTEX_A55 + +endchoice # i.MX9 Chip Selection + +endmenu # "i.MX9 Chip Selection" + +menu "i.MX9 Peripheral Selection" +config IMX9_UART1 + bool "UART1" + default n + select UART1_SERIALDRIVER +endmenu # iMX Peripheral Selection + +endif # ARCH_CHIP_IMX9 diff --git a/arch/arm64/src/imx9/Make.defs b/arch/arm64/src/imx9/Make.defs new file mode 100644 index 00000000000..0f9a4821c63 --- /dev/null +++ b/arch/arm64/src/imx9/Make.defs @@ -0,0 +1,32 @@ +############################################################################ +# arch/arm64/src/imx9/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include common/Make.defs + +# i.MX9-specific C source files + +CHIP_CSRCS = imx9_boot.c + +ifeq ($(CONFIG_ARCH_CHIP_IMX93),y) + CHIP_CSRCS += imx9_lpuart.c + ifeq ($(CONFIG_ARCH_EARLY_PRINT),y) + CHIP_ASRCS = imx93_lowputc.S + endif +endif diff --git a/arch/arm64/src/imx9/chip.h b/arch/arm64/src/imx9/chip.h new file mode 100644 index 00000000000..691f795ed8f --- /dev/null +++ b/arch/arm64/src/imx9/chip.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/arm64/src/imx9/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_CHIP_H +#define __ARCH_ARM64_SRC_IMX9_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Macro Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM64_SRC_IMX9_CHIP_H */ diff --git a/arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h b/arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h new file mode 100644 index 00000000000..f3fcbded4e0 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h @@ -0,0 +1,174 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_MEMORYMAP_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX9_GIC_DISTRIBUTOR_BASE (0x48000000UL) +#define IMX9_GIC_REDISTRIBUTOR_BASE (0x48040000UL) +#define IMX9_ANA_OSC_BASE (0x44480000UL) +#define IMX9_AXBS_BASE (0x44510000UL) +#define IMX9_BBNSM_BASE (0x44440000UL) +#define IMX9_BLK_CTRL_BBSMMIX1_BASE (0x44410000UL) +#define IMX9_BLK_CTRL_MLMIX_BASE (0x4A810000UL) +#define IMX9_BLK_CTRL_NIC_WRAPPER1_BASE (0x49000000UL) +#define IMX9_BLK_CTRL_NS_AONMIX1_BASE (0x44210000UL) +#define IMX9_BLK_CTRL_S_AONMIX2_BASE (0x444F0000UL) +#define IMX9_BLK_CTRL_WAKEUPMIX1_BASE (0x42420000UL) +#define IMX9_CAN1_BASE (0x443A0000UL) +#define IMX9_CAN2_BASE (0x425B0000UL) +#define IMX9_CCM_CTRL_BASE (0x44450000UL) +#define IMX9_CM33_MCM_BASE (0x44420000UL) +#define IMX9_DDR_CTRL_BASE (0x4E300000UL) +#define IMX9_BLK_CTRL_DDRMIX_BASE (0x4E010000UL) +#define IMX9_DMA3_BASE (0x44000000UL) +#define IMX9_DMA4_BASE (0x42000000UL) +#define IMX9_PMRO_BASE (0x44484000UL) +#define IMX9_ENET_BASE (0x42890000UL) +#define IMX9_ENET_QOS_BASE (0x428A0000UL) +#define IMX9_FLEXIO1_BASE (0x425C0000UL) +#define IMX9_FLEXIO2_BASE (0x425D0000UL) +#define IMX9_FLEXSPI_BASE (0x425E0000UL) +#define IMX9_FLEXSPI_ARDF_BASE (0x47420000UL) +#define IMX9_FLEXSPI_ATDF_BASE (0x47430000UL) +#define IMX9_GPC_CTRL_CM33_BASE (0x44470000UL) +#define IMX9_GPC_CTRL_CA55_0_BASE (0x44470800UL) +#define IMX9_GPC_CTRL_CA55_1_BASE (0x44471000UL) +#define IMX9_GPC_CTRL_CA55_CLUSTER_BASE (0x44471800UL) +#define IMX9_SAI1_BASE (0x443B0000UL) +#define IMX9_SAI2_BASE (0x42650000UL) +#define IMX9_SAI3_BASE (0x42660000UL) +#define IMX9_I3C1_BASE (0x44330000UL) +#define IMX9_I3C2_BASE (0x42520000UL) +#define IMX9_IOMUXC1_BASE (0x443C0000UL) +#define IMX9_ISI_BASE (0x4AE40000UL) +#define IMX9_LCDIF_BASE (0x4AE30000UL) +#define IMX9_LPI2C1_BASE (0x44340000UL) +#define IMX9_LPI2C2_BASE (0x44350000UL) +#define IMX9_LPI2C3_BASE (0x42530000UL) +#define IMX9_LPI2C4_BASE (0x42540000UL) +#define IMX9_LPI2C5_BASE (0x426B0000UL) +#define IMX9_LPI2C6_BASE (0x426C0000UL) +#define IMX9_LPI2C7_BASE (0x426D0000UL) +#define IMX9_LPI2C8_BASE (0x426E0000UL) +#define IMX9_LPIT1_BASE (0x442F0000UL) +#define IMX9_LPIT2_BASE (0x424C0000UL) +#define IMX9_LPSPI1_BASE (0x44360000UL) +#define IMX9_LPSPI2_BASE (0x44370000UL) +#define IMX9_LPSPI3_BASE (0x42550000UL) +#define IMX9_LPSPI4_BASE (0x42560000UL) +#define IMX9_LPSPI5_BASE (0x426F0000UL) +#define IMX9_LPSPI6_BASE (0x42700000UL) +#define IMX9_LPSPI7_BASE (0x42710000UL) +#define IMX9_LPSPI8_BASE (0x42720000UL) +#define IMX9_LPTMR1_BASE (0x44300000UL) +#define IMX9_LPTMR2_BASE (0x424D0000UL) +#define IMX9_LPUART1_BASE (0x44380000UL) +#define IMX9_LPUART2_BASE (0x44390000UL) +#define IMX9_LPUART3_BASE (0x42570000UL) +#define IMX9_LPUART4_BASE (0x42580000UL) +#define IMX9_LPUART5_BASE (0x42590000UL) +#define IMX9_LPUART6_BASE (0x425A0000UL) +#define IMX9_LPUART7_BASE (0x42690000UL) +#define IMX9_LPUART8_BASE (0x426A0000UL) +#define IMX9_M33_CACHE_MCM_BASE (0x44401000UL) +#define IMX9_BLK_CTRL_MEDIAMIX_BASE (0x4AC10000UL) +#define IMX9_MIPI_CSI_CSR_BASE (0x4AE00000UL) +#define IMX9_MIPI_DSI_BASE (0x4AE10000UL) +#define IMX9_MU1__MUB_BASE (0x44230000UL) +#define IMX9_MU2__MUB_BASE (0x42440000UL) +#define IMX9_NPU_BASE (0x4A900000UL) +#define IMX9_OCOTP_BASE (0x47518000UL) +#define IMX9_OCRAM_MECC1_BASE (0x490A0000UL) +#define IMX9_FLEXSPI_OTFAD1_BASE (0x425E0C00UL) +#define IMX9_PDM_BASE (0x44520000UL) +#define IMX9_ARMPLL_BASE (0x44481000UL) +#define IMX9_AUDIOPLL_BASE (0x44481200UL) +#define IMX9_DRAMPLL_BASE (0x44481300UL) +#define IMX9_SYSPLL_BASE (0x44481100UL) +#define IMX9_VIDEOPLL_BASE (0x44481400UL) +#define IMX9_PXP_BASE (0x4AE20000UL) +#define IMX9_GPIO1_BASE (0x47400000UL) +#define IMX9_GPIO2_BASE (0x43810000UL) +#define IMX9_GPIO3_BASE (0x43820000UL) +#define IMX9_GPIO4_BASE (0x43830000UL) +#define IMX9_ROMCP1_BASE (0x44430000UL) +#define IMX9_ROMCP2_BASE (0x42640000UL) +#define IMX9_ADC1_BASE (0x44530000UL) +#define IMX9_SEMA42_1_BASE (0x44260000UL) +#define IMX9_SEMA42_2_BASE (0x42450000UL) +#define IMX9_SFA_BASE (0x44483000UL) +#define IMX9_SPDIF_BASE (0x42680000UL) +#define IMX9_SRC_SENTINEL_SLICE_BASE (0x44460400UL) +#define IMX9_SRC_AON_SLICE_BASE (0x44460800UL) +#define IMX9_SRC_WKUP_SLICE_BASE (0x44460C00UL) +#define IMX9_SRC_DDR_SLICE_BASE (0x44461000UL) +#define IMX9_SRC_DPHY_SLICE_BASE (0x44461400UL) +#define IMX9_SRC_ML_SLICE_BASE (0x44461800UL) +#define IMX9_SRC_NIC_SLICE_BASE (0x44461C00UL) +#define IMX9_SRC_HSIO_SLICE_BASE (0x44462000UL) +#define IMX9_SRC_MEDIA_SLICE_BASE (0x44462400UL) +#define IMX9_SRC_M33P_SLICE_BASE (0x44462800UL) +#define IMX9_SRC_A55C0_SLICE_BASE (0x44462C00UL) +#define IMX9_SRC_A55C1_SLICE_BASE (0x44463000UL) +#define IMX9_SRC_A55P_SLICE_BASE (0x44463400UL) +#define IMX9_M33_PCF1_BASE (0x443E0000UL) +#define IMX9_M33_PSF1_BASE (0x443F0000UL) +#define IMX9_SYS_CTR_COMPARE_BASE (0x442A0000UL) +#define IMX9_SYS_CTR_CONTROL_BASE (0x44290000UL) +#define IMX9_SYS_CTR_READ_BASE (0x442B0000UL) +#define IMX9_TMU_BASE (0x44482000UL) +#define IMX9_TPM1_BASE (0x44310000UL) +#define IMX9_TPM2_BASE (0x44320000UL) +#define IMX9_TPM3_BASE (0x424E0000UL) +#define IMX9_TPM4_BASE (0x424F0000UL) +#define IMX9_TPM5_BASE (0x42500000UL) +#define IMX9_TPM6_BASE (0x42510000UL) +#define IMX9_TRDC1_BASE (0x44270000UL) +#define IMX9_TRDC2_BASE (0x42460000UL) +#define IMX9_TRGMUX_BASE (0x44531000UL) +#define IMX9_TSTMR1__TSTMRA_BASE (0x442C0000UL) +#define IMX9_TSTMR2__TSTMRA_BASE (0x42480000UL) +#define IMX9_USB__USB_OTG1_BASE (0x4C100000UL) +#define IMX9_USB__USB_OTG2_BASE (0x4C200000UL) +#define IMX9_USB__USBNC_OTG1_BASE (0x4C100200UL) +#define IMX9_USB__USBNC_OTG2_BASE (0x4C200200UL) +#define IMX9_USDHC1_BASE (0x42850000UL) +#define IMX9_USDHC2_BASE (0x42860000UL) +#define IMX9_USDHC3_BASE (0x428B0000UL) +#define IMX9_WDOG1_BASE (0x442D0000UL) +#define IMX9_WDOG2_BASE (0x442E0000UL) +#define IMX9_WDOG3_BASE (0x42490000UL) +#define IMX9_WDOG4_BASE (0x424A0000UL) +#define IMX9_WDOG5_BASE (0x424B0000UL) +#define IMX9_LPCAC_PC_BASE (0x44400000UL) +#define IMX9_LPCAC_PS_BASE (0x44400800UL) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_MEMORYMAP_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_lpuart.h b/arch/arm64/src/imx9/hardware/imx9_lpuart.h new file mode 100644 index 00000000000..3925c51bc60 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_lpuart.h @@ -0,0 +1,158 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_lpuart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPUART_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPUART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* 32-bit register definition */ + +#define UARTVERID 0x0000 /* Version ID Register */ +#define UARTPARAM 0x0004 /* Parameter Register */ +#define UARTGLOBAL 0x0008 /* LPUART Global Register */ +#define UARTPINCFG 0x000c /* LPUART Pin Configuration Register */ +#define UARTBAUD 0x0010 /* LPUART Baud Rate Register */ +#define UARTSTAT 0x0014 /* LPUART Status Register */ +#define UARTCTRL 0x0018 /* LPUART Control Register */ +#define UARTDATA 0x001c /* LPUART Data Register */ +#define UARTMATCH 0x0020 /* LPUART Match Address Register */ +#define UARTMODIR 0x0024 /* LPUART Modem IrDA Register */ +#define UARTFIFO 0x0028 /* LPUART FIFO Register */ +#define UARTWATER 0x002c /* LPUART Watermark Register */ + +#define UARTBAUD_MAEN1 0x80000000 +#define UARTBAUD_MAEN2 0x40000000 +#define UARTBAUD_M10 0x20000000 +#define UARTBAUD_TDMAE 0x00800000 +#define UARTBAUD_RDMAE 0x00200000 +#define UARTBAUD_RIDMAE 0x00100000 +#define UARTBAUD_MATCFG 0x00400000 +#define UARTBAUD_BOTHEDGE 0x00020000 +#define UARTBAUD_RESYNCDIS 0x00010000 +#define UARTBAUD_LBKDIE 0x00008000 +#define UARTBAUD_RXEDGIE 0x00004000 +#define UARTBAUD_SBNS 0x00002000 +#define UARTBAUD_SBR 0x00000000 +#define UARTBAUD_SBR_MASK 0x1fff +#define UARTBAUD_OSR_MASK 0x1f +#define UARTBAUD_OSR_SHIFT 24 + +#define UARTSTAT_LBKDIF 0x80000000 +#define UARTSTAT_RXEDGIF 0x40000000 +#define UARTSTAT_MSBF 0x20000000 +#define UARTSTAT_RXINV 0x10000000 +#define UARTSTAT_RWUID 0x08000000 +#define UARTSTAT_BRK13 0x04000000 +#define UARTSTAT_LBKDE 0x02000000 +#define UARTSTAT_RAF 0x01000000 +#define UARTSTAT_TDRE 0x00800000 +#define UARTSTAT_TC 0x00400000 +#define UARTSTAT_RDRF 0x00200000 +#define UARTSTAT_IDLE 0x00100000 +#define UARTSTAT_OR 0x00080000 +#define UARTSTAT_NF 0x00040000 +#define UARTSTAT_FE 0x00020000 +#define UARTSTAT_PE 0x00010000 +#define UARTSTAT_MA1F 0x00008000 +#define UARTSTAT_M21F 0x00004000 + +#define UARTCTRL_R8T9 0x80000000 +#define UARTCTRL_R9T8 0x40000000 +#define UARTCTRL_TXDIR 0x20000000 +#define UARTCTRL_TXINV 0x10000000 +#define UARTCTRL_ORIE 0x08000000 +#define UARTCTRL_NEIE 0x04000000 +#define UARTCTRL_FEIE 0x02000000 +#define UARTCTRL_PEIE 0x01000000 +#define UARTCTRL_TIE 0x00800000 +#define UARTCTRL_TCIE 0x00400000 +#define UARTCTRL_RIE 0x00200000 +#define UARTCTRL_ILIE 0x00100000 +#define UARTCTRL_TE 0x00080000 +#define UARTCTRL_RE 0x00040000 +#define UARTCTRL_RWU 0x00020000 +#define UARTCTRL_SBK 0x00010000 +#define UARTCTRL_MA1IE 0x00008000 +#define UARTCTRL_MA2IE 0x00004000 +#define UARTCTRL_IDLECFG_OFF 0x8 +#define UARTCTRL_LOOPS 0x00000080 +#define UARTCTRL_DOZEEN 0x00000040 +#define UARTCTRL_RSRC 0x00000020 +#define UARTCTRL_M 0x00000010 +#define UARTCTRL_WAKE 0x00000008 +#define UARTCTRL_ILT 0x00000004 +#define UARTCTRL_PE 0x00000002 +#define UARTCTRL_PT 0x00000001 + +#define UARTDATA_NOISY 0x00008000 +#define UARTDATA_PARITYE 0x00004000 +#define UARTDATA_FRETSC 0x00002000 +#define UARTDATA_RXEMPT 0x00001000 +#define UARTDATA_IDLINE 0x00000800 +#define UARTDATA_MASK 0x3ff + +#define UARTMODIR_IREN 0x00020000 +#define UARTMODIR_RTSWATER_S 0x8 +#define UARTMODIR_TXCTSSRC 0x00000020 +#define UARTMODIR_TXCTSC 0x00000010 +#define UARTMODIR_RXRTSE 0x00000008 +#define UARTMODIR_TXRTSPOL 0x00000004 +#define UARTMODIR_TXRTSE 0x00000002 +#define UARTMODIR_TXCTSE 0x00000001 + +#define UARTFIFO_TXEMPT 0x00800000 +#define UARTFIFO_RXEMPT 0x00400000 +#define UARTFIFO_TXOF 0x00020000 +#define UARTFIFO_RXUF 0x00010000 +#define UARTFIFO_TXFLUSH 0x00008000 +#define UARTFIFO_RXFLUSH 0x00004000 +#define UARTFIFO_RXIDEN_MASK 0x7 +#define UARTFIFO_RXIDEN_OFF 10 +#define UARTFIFO_TXOFE 0x00000200 +#define UARTFIFO_RXUFE 0x00000100 +#define UARTFIFO_TXFE 0x00000080 +#define UARTFIFO_FIFOSIZE_MASK 0x7 +#define UARTFIFO_TXSIZE_OFF 4 +#define UARTFIFO_RXFE 0x00000008 +#define UARTFIFO_RXSIZE_OFF 0 +#define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) + +#define UARTWATER_COUNT_MASK 0xff +#define UARTWATER_TXCNT_OFF 8 +#define UARTWATER_RXCNT_OFF 24 +#define UARTWATER_WATER_MASK 0xff +#define UARTWATER_TXWATER_OFF 0 +#define UARTWATER_RXWATER_OFF 16 + +#define UARTGLOBAL_RST 0x2 + +#define UARTFIFO_RXIDEN_RDRF 0x3 +#define UARTCTRL_IDLECFG 0x7 + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPUART_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_memorymap.h b/arch/arm64/src/imx9/hardware/imx9_memorymap.h new file mode 100644 index 00000000000..cf682d25a21 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_memorymap.h @@ -0,0 +1,36 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include "hardware/imx93/imx93_memorymap.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H */ diff --git a/arch/arm64/src/imx9/imx93_lowputc.S b/arch/arm64/src/imx9/imx93_lowputc.S new file mode 100644 index 00000000000..f3311810e05 --- /dev/null +++ b/arch/arm64/src/imx9/imx93_lowputc.S @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx93_lowputs.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + **************************************************************************** + * + * DESCRIPTION + * Wrapper for early printk + * + ***************************************************************************/ + +#include + +#include "arm64_macro.inc" + +#include "hardware/imx9_lpuart.h" +#include "hardware/imx93/imx93_memorymap.h" + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .file "imx93_lowputc.S" + +/**************************************************************************** + * Assembly Macros + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* PL011 UART initialization */ + +GTEXT(arm64_earlyprintinit) +SECTION_FUNC(text, arm64_earlyprintinit) + /* TODO: Assumes u-boot has set us up, assumption is fine for now */ + ret + +/* i.MX93 wait LPUART to be ready to transmit + * rb: register which contains the UART base address + * rc: scratch register + */ +.macro early_uart_ready rb, rc +1: + ldr \rc, [\rb, #UARTSTAT] /* <- Flag register */ + tst \rc, #UARTSTAT_TDRE /* Check FIFO EMPTY bit */ + beq 1b /* Wait for the UART to be ready */ +.endm + +/* i.MX93 LPUART transmit character + * rb: register which contains the UART base address + * rt: register which contains the character to transmit */ +.macro early_uart_transmit rb, rt + str \rt, [\rb, #UARTDATA] /* -> Data Register */ +.endm + +/* + * Print a character on the UART - this function is called by C + * w0: character to print + */ +GTEXT(arm64_lowputc) +SECTION_FUNC(text, arm64_lowputc) + ldr x15, =IMX9_LPUART1_BASE + early_uart_ready x15, w2 + early_uart_transmit x15, w0 + ret diff --git a/arch/arm64/src/imx9/imx9_boot.c b/arch/arm64/src/imx9/imx9_boot.c new file mode 100644 index 00000000000..16f19de2c6b --- /dev/null +++ b/arch/arm64/src/imx9/imx9_boot.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#ifdef CONFIG_PAGING +# include +#endif + +#include +#include "arm64_arch.h" +#include "arm64_internal.h" +#include "arm64_mmu.h" +#include "imx9_boot.h" +#include "imx9_serial.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct arm_mmu_region g_mmu_regions[] = +{ + MMU_REGION_FLAT_ENTRY("DEVICE_REGION", + CONFIG_DEVICEIO_BASEADDR, CONFIG_DEVICEIO_SIZE, + MT_DEVICE_NGNRNE | MT_RW | MT_SECURE), + + MMU_REGION_FLAT_ENTRY("DRAM0_S0", + CONFIG_RAMBANK1_ADDR, CONFIG_RAMBANK1_SIZE, + MT_NORMAL | MT_RW | MT_SECURE), +}; + +const struct arm_mmu_config g_mmu_config = +{ + .num_regions = nitems(g_mmu_regions), + .mmu_regions = g_mmu_regions, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm64_el_init + * + * Description: + * The function called from arm64_head.S at very early stage for these + * platform, it's use to: + * - Handling special hardware initialize routine which is need to + * run at high ELs + * - Initialize system software such as hypervisor or security firmware + * which is need to run at high ELs + * + ****************************************************************************/ + +void arm64_el_init(void) +{ +} + +/**************************************************************************** + * Name: arm64_chip_boot + * + * Description: + * Complete boot operations started in arm64_head.S + * + ****************************************************************************/ + +void arm64_chip_boot(void) +{ + /* MAP IO and DRAM, enable MMU. */ + + arm64_mmu_init(true); + + /* Perform board-specific device initialization. This would include + * configuration of board specific resources such as GPIOs, LEDs, etc. + */ + + imx9_board_initialize(); + +#ifdef USE_EARLYSERIALINIT + /* Perform early serial initialization if we are going to use the serial + * driver. + */ + + arm64_earlyserialinit(); +#endif +} diff --git a/arch/arm64/src/imx9/imx9_boot.h b/arch/arm64/src/imx9/imx9_boot.h new file mode 100644 index 00000000000..cfd10b7e1b2 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_boot.h @@ -0,0 +1,79 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_boot.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_BOOT_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_BOOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: imx9_board_initialize + * + * Description: + * All i.MX9 architectures must provide the following entry point. This + * entry point is called in the initialization phase -- after + * imx_memory_initialize and after all memory has been configured and + * mapped but before any devices have been initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_board_initialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_BOOT_H */ diff --git a/arch/arm64/src/imx9/imx9_lpuart.c b/arch/arm64/src/imx9/imx9_lpuart.c new file mode 100644 index 00000000000..2fa4307f4c2 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_lpuart.c @@ -0,0 +1,950 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_lpuart.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "arm64_arch.h" +#include "arm64_internal.h" +#include "arm64_gic.h" + +#include "imx9_serial.h" +#include "imx9_boot.h" + +#include "hardware/imx9_lpuart.h" +#include "hardware/imx9_memorymap.h" + +#ifdef USE_SERIALDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Which UART with be tty0/console and which tty1-4? The console will + * always be ttyS0. If there is no console then will use the lowest + * numbered UART. + */ + +/* First pick the console and ttys0. This could be any of UART1-5 */ + +#if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +#endif + +/* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ +#define DMA_RX_TIMEOUT (10) +#define UART_AUTOSUSPEND_TIMEOUT 3000 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imx9_uart_port_s +{ + unsigned long iobase; + unsigned int baud; /* Configured baud */ + unsigned int irq_num; + unsigned int txfifo_size; + unsigned int rxfifo_size; + int is_console; +}; + +static inline uint32_t imx9_read(struct imx9_uart_port_s *port, uint32_t off) +{ + return getreg32(port->iobase + off); +} + +static inline void imx9_write(struct imx9_uart_port_s *port, uint32_t val, + uint32_t off) +{ + putreg32(val, port->iobase + off); +} + +static int imx9_lpuart_stop_tx(struct imx9_uart_port_s *sport) +{ + unsigned long temp; + + temp = imx9_read(sport, UARTCTRL); + temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); + imx9_write(sport, temp, UARTCTRL); + + return 0; +} + +static int imx9_lpuart_stop_rx(struct imx9_uart_port_s *sport) +{ + unsigned long temp; + + temp = imx9_read(sport, UARTCTRL); + imx9_write(sport, temp & ~UARTCTRL_RE, UARTCTRL); + + return 0; +} + +static int imx9_lpuart_start_tx(struct imx9_uart_port_s *sport) +{ + unsigned long temp; + + temp = imx9_read(sport, UARTCTRL); + imx9_write(sport, temp | UARTCTRL_TIE, UARTCTRL); + + return 0; +} + +static int imx9_lpuart_start_rx(struct imx9_uart_port_s *sport) +{ + unsigned long temp; + + temp = imx9_read(sport, UARTCTRL); + imx9_write(sport, temp | UARTCTRL_RE, UARTCTRL); + + return 0; +} + +/**************************************************************************** + * Name: imx9_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void imx9_rxint(struct uart_dev_s *dev, bool enable) +{ + struct imx9_uart_port_s *sport = (struct imx9_uart_port_s *)dev->priv; + + if (enable) + { + imx9_lpuart_start_rx(sport); + } + else + { + imx9_lpuart_stop_rx(sport); + } +} + +/**************************************************************************** + * Name: imx9_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void imx9_txint(struct uart_dev_s *dev, bool enable) +{ + struct imx9_uart_port_s *sport = (struct imx9_uart_port_s *)dev->priv; + + if (enable) + { + imx9_lpuart_start_tx(sport); + } + else + { + imx9_lpuart_stop_tx(sport); + } +} + +/**************************************************************************** + * Name: imx9_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void imx9_send(struct uart_dev_s *dev, int ch) +{ + struct imx9_uart_port_s *sport = (struct imx9_uart_port_s *)dev->priv; + + imx9_write(sport, ch, UARTDATA); +} + +/**************************************************************************** + * Name: imx9_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int imx9_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct imx9_uart_port_s *sport = (struct imx9_uart_port_s *)dev->priv; + unsigned int rx; + unsigned int sr; + + /* to clear the FE, OR, NF, FE, PE flags, + * read STAT then read DATA reg + */ + + sr = imx9_read(sport, UARTSTAT); + rx = imx9_read(sport, UARTDATA); + + *status = sr; + + return rx; +} + +/**************************************************************************** + * Name: imx9_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool imx9_rxavailable(struct uart_dev_s *dev) +{ + struct imx9_uart_port_s *sport = (struct imx9_uart_port_s *)dev->priv; + unsigned long sfifo = imx9_read(sport, UARTFIFO); + + if (sfifo & UARTFIFO_RXEMPT) + { + return false; + } + else + { + return true; + } +} + +/**************************************************************************** + * Name: imx9_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ****************************************************************************/ + +static bool imx9_txready(struct uart_dev_s *dev) +{ + struct imx9_uart_port_s *sport = (struct imx9_uart_port_s *)dev->priv; + unsigned long txcnt; + + /* When TXFULL is set, there is no space in the Tx FIFO */ + + txcnt = imx9_read(sport, UARTWATER); + txcnt = txcnt >> UARTWATER_TXCNT_OFF; + txcnt &= UARTWATER_COUNT_MASK; + + if (txcnt < sport->txfifo_size) + { + return true; + } + else + { + return false; + } +} + +/**************************************************************************** + * Name: imx9_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ****************************************************************************/ + +static bool imx9_txempty(struct uart_dev_s *dev) +{ + struct imx9_uart_port_s *sport = (struct imx9_uart_port_s *)dev->priv; + unsigned long stat = imx9_read(sport, UARTSTAT); + unsigned long sfifo = imx9_read(sport, UARTFIFO); + + if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) + { + return true; + } + else + { + return false; + } +} + +/**************************************************************************** + * Name: imx9_irq_handler (and front-ends) + * + * Description: + * This is the common UART interrupt handler. It should cal + * uart_transmitchars or uart_receivechar to perform the appropriate data + * transfers. + * + ****************************************************************************/ + +static int imx9_uart_irq_handler(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct imx9_uart_port_s *sport; + unsigned long sts; + unsigned long rxcount; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + sport = (struct imx9_uart_port_s *)dev->priv; + + sts = imx9_read(sport, UARTSTAT); + rxcount = imx9_read(sport, UARTWATER); + rxcount = rxcount >> UARTWATER_RXCNT_OFF; + + if (sts & UARTSTAT_RDRF || rxcount > 0) + { + uart_recvchars(dev); + } + + if (sts & UARTSTAT_TDRE) + { + uart_xmitchars(dev); + } + + imx9_write(sport, sts, UARTSTAT); + return OK; +} + +static int imx9_lpuart_hw_reset(struct imx9_uart_port_s *sport) +{ + if (sport->is_console) + { + return 0; + } + + /* Toggle the reset signal to reset and release the peripheral */ + + putreg32(UARTGLOBAL_RST, sport->iobase + UARTGLOBAL); + putreg32(0, sport->iobase + UARTGLOBAL); + + return 0; +} + +static int imx9_setup(struct uart_dev_s *dev) +{ + irqstate_t i_flags; + int ret; + struct imx9_uart_port_s *sport = (struct imx9_uart_port_s *)dev->priv; + + i_flags = up_irq_save(); + + ret = imx9_lpuart_hw_reset(sport); + if (ret < 0) + { + serr("failed to reset hw: %d\n", ret); + } + + up_irq_restore(i_flags); + + return ret; +} + +/**************************************************************************** + * Name: imx9_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void imx9_shutdown(struct uart_dev_s *dev) +{ + struct imx9_uart_port_s *sport = (struct imx9_uart_port_s *)dev->priv; + unsigned long temp; + irqstate_t i_flags; + + i_flags = up_irq_save(); + + /* clear statue */ + + temp = imx9_read(sport, UARTSTAT); + imx9_write(sport, temp, UARTSTAT); + + /* disable Rx/Tx DMA */ + + temp = imx9_read(sport, UARTBAUD); + temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE | UARTBAUD_RIDMAE); + imx9_write(sport, temp, UARTBAUD); + + /* disable Rx/Tx and interrupts */ + + temp = imx9_read(sport, UARTCTRL); + temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_TIE | + UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_ILIE | + UARTCTRL_LOOPS); + imx9_write(sport, temp, UARTCTRL); + imx9_write(sport, 0, UARTMODIR); + + up_irq_restore(i_flags); +} + +static void imx9_setup_watermark(struct imx9_uart_port_s *sport) +{ + unsigned long val; + unsigned long ctrl; + unsigned long ctrl_saved; + unsigned long rxiden_cnt; + + ctrl = imx9_read(sport, UARTCTRL); + ctrl_saved = ctrl; + ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | + UARTCTRL_RIE | UARTCTRL_RE); + imx9_write(sport, ctrl, UARTCTRL); + + /* enable FIFO mode */ + + val = imx9_read(sport, UARTFIFO); + val |= UARTFIFO_TXFE | UARTFIFO_RXFE; + val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; + val &= ~(UARTFIFO_RXIDEN_MASK << UARTFIFO_RXIDEN_OFF); + rxiden_cnt = 0; + val |= ((rxiden_cnt & UARTFIFO_RXIDEN_MASK) << UARTFIFO_RXIDEN_OFF); + + imx9_write(sport, val, UARTFIFO); + + /* set the watermark + * rx_watermark = 1; + */ + + val = (1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); + imx9_write(sport, val, UARTWATER); + + /* Restore cr2 */ + + imx9_write(sport, ctrl_saved, UARTCTRL); +} + +static void imx9_setup_watermark_enable(struct imx9_uart_port_s *sport) +{ + uint32_t temp; + + imx9_setup_watermark(sport); + + temp = imx9_read(sport, UARTCTRL); + temp |= UARTCTRL_RE | UARTCTRL_TE; + temp |= UARTCTRL_IDLECFG << UARTCTRL_IDLECFG_OFF; + imx9_write(sport, temp, UARTCTRL); +} + +static void imx9_hw_disable(struct imx9_uart_port_s *sport) +{ + unsigned long temp; + + temp = imx9_read(sport, UARTCTRL); + temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE | + UARTCTRL_TIE | UARTCTRL_TE); + imx9_write(sport, temp, UARTCTRL); +} + +static void imx9_configure(struct imx9_uart_port_s *sport) +{ + unsigned long temp; + + temp = imx9_read(sport, UARTCTRL); + temp |= UARTCTRL_RIE | UARTCTRL_ILIE; + temp |= UARTCTRL_TIE; + imx9_write(sport, temp, UARTCTRL); +} + +static void imx9_hw_setup(struct imx9_uart_port_s *sport) +{ + irqstate_t i_flags; + + i_flags = up_irq_save(); + + imx9_hw_disable(sport); + + imx9_setup_watermark_enable(sport); + imx9_configure(sport); + up_enable_irq(sport->irq_num); + + up_irq_restore(i_flags); +} + +/**************************************************************************** + * Name: imx9_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int imx9_attach(struct uart_dev_s *dev) +{ + struct imx9_uart_port_s *sport = (struct imx9_uart_port_s *)dev->priv; + int ret; + unsigned long temp; + + /* determine FIFO size */ + + temp = imx9_read(sport, UARTFIFO); + + sport->txfifo_size = UARTFIFO_DEPTH( + (temp >> UARTFIFO_TXSIZE_OFF) & UARTFIFO_FIFOSIZE_MASK); + sport->rxfifo_size = UARTFIFO_DEPTH( + (temp >> UARTFIFO_RXSIZE_OFF) & UARTFIFO_FIFOSIZE_MASK); + + ret = irq_attach(sport->irq_num, imx9_uart_irq_handler, dev); + + if (ret == OK) + { + imx9_hw_setup(sport); + } + else + { + sinfo("error ret=%d\n", ret); + } + + return ret; +} + +/**************************************************************************** + * Name: imx_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void imx9_detach(struct uart_dev_s *dev) +{ + struct imx9_uart_port_s *sport = (struct imx9_uart_port_s *)dev->priv; + + up_disable_irq(sport->irq_num); + irq_detach(sport->irq_num); +} + +/**************************************************************************** + * Name: imx9_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * for current imx9 configure. + * + ****************************************************************************/ + +static int imx9_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || defined(CONFIG_SERIAL_TERMIOS) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + irqstate_t flags; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct imx_uart_s *user = (struct imx_uart_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct imx_uart_s)); + } + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + struct imx_uart_s *priv = (struct imx_uart_s *)dev->priv; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Return parity */ + + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + + /* Return stop bits */ + + termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0; + + /* Return flow control */ + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + termiosp->c_cflag |= ((priv->oflow) ? CCTS_OFLOW : 0); +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + termiosp->c_cflag |= ((priv->iflow) ? CRTS_IFLOW : 0); +#endif + + /* Return baud */ + + cfsetispeed(termiosp, priv->baud); + + /* Return number of bits */ + + switch (priv->bits) + { + case 5: + { + termiosp->c_cflag |= CS5; + break; + } + + case 6: + { + termiosp->c_cflag |= CS6; + break; + } + + case 7: + { + termiosp->c_cflag |= CS7; + break; + } + + default: + case 8: + { + termiosp->c_cflag |= CS8; + break; + } + +#if defined(CS9) + case 9: + { + termiosp->c_cflag |= CS9; + break; + } +#endif + } + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + struct imx_uart_s *priv = (struct imx_uart_s *)dev->priv; + uint32_t baud; + uint32_t ie; + uint8_t parity; + uint8_t nbits; + bool stop2; + + if ((!termiosp) +#ifdef CONFIG_SERIAL_OFLOWCONTROL + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) +#endif + ) + { + ret = -EINVAL; + break; + } + + /* Decode baud. */ + + ret = OK; + baud = cfgetispeed(termiosp); + + /* Decode number of bits */ + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + { + nbits = 5; + break; + } + + case CS6: + { + nbits = 6; + break; + } + + case CS7: + { + nbits = 7; + break; + } + + case CS8: + { + nbits = 8; + break; + } + +#if defined(CS9) + case CS9: + { + nbits = 9; + break; + } + +#endif + default: + { + ret = -EINVAL; + break; + } + } + + /* Decode parity */ + + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + /* Decode stop bits */ + + stop2 = (termiosp->c_cflag & CSTOPB) != 0; + + /* Verify that all settings are valid before committing */ + + if (ret == OK) + { + /* Commit */ + + priv->baud = baud; + priv->parity = parity; + priv->bits = nbits; + priv->stopbits2 = stop2; +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif + + /* effect the changes immediately - note that we do not + * implement TCSADRAIN / TCSAFLUSH + */ + + flags = spin_lock_irqsave(NULL); + imx9_disableuartint(priv, &ie); + ret = imx9_setup(dev); + + /* Restore the interrupt state */ + + imx_restoreuartint(priv, ie); + priv->ie = ie; + spin_unlock_irqrestore(NULL, flags); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + default: + { + ret = -ENOTTY; + break; + } + } + + return ret; +} + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Serial driver UART operations */ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = imx9_setup, + .shutdown = imx9_shutdown, + .attach = imx9_attach, + .detach = imx9_detach, + .ioctl = imx9_ioctl, + .receive = imx9_receive, + .rxint = imx9_rxint, + .rxavailable = imx9_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = imx9_send, + .txint = imx9_txint, + .txready = imx9_txready, + .txempty = imx9_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_IMX9_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; + +/* This describes the state of the IMX uart1 port. */ + +static struct imx9_uart_port_s g_uart1priv = +{ + .iobase = IMX9_LPUART1_BASE, + .baud = CONFIG_UART1_BAUD, + .irq_num = IMX9_IRQ_LPUART1, + .is_console = 1, +}; + +static struct uart_dev_s g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; + +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm64_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in + * debug so that the serial console will be available + * during bootup. This must be called before arm64_serialinit. + * + ****************************************************************************/ + +void arm64_earlyserialinit(void) +{ + /* NOTE: This function assumes that low level hardware configuration + * -- including all clocking and pin configuration -- was performed by the + * function imx9_lowsetup() earlier in the boot sequence. + */ + + /* Enable the console UART. The other UARTs will be initialized if and + * when they are first opened. + */ +#ifdef CONSOLE_DEV + CONSOLE_DEV.isconsole = true; + imx9_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug + * writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + arm64_lowputc('\r'); + } + + arm64_lowputc((uint8_t)ch); + return ch; +} + +/**************************************************************************** + * Name: arm64_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that imx_earlyserialinit was called previously. + * + ****************************************************************************/ + +void arm64_serialinit(void) +{ + int ret; + + ret = uart_register("/dev/console", &CONSOLE_DEV); + if (ret < 0) + { + sinfo("error at register dev/console, ret =%d\n", ret); + } + + ret = uart_register("/dev/ttyS0", &TTYS0_DEV); + if (ret < 0) + { + sinfo("error at register dev/ttyS0, ret =%d\n", ret); + } +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm64/src/imx9/imx9_serial.h b/arch/arm64/src/imx9/imx9_serial.h new file mode 100644 index 00000000000..854c6367aee --- /dev/null +++ b/arch/arm64/src/imx9/imx9_serial.h @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_serial.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_SERIAL_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_SERIAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "arm64_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before arm_serialinit. + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void imx9_earlyserialinit(void); +#endif + +/**************************************************************************** + * Name: uart_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before arm_serialinit. + * + ****************************************************************************/ + +#if defined(USE_EARLYSERIALINIT) && defined(IMX9_HAVE_UART) +void uart_earlyserialinit(void); +#endif + +/**************************************************************************** + * Name: uart_serialinit + * + * Description: + * Register the UART serial console and serial ports. This assumes that + * uart_earlyserialinit was called previously. + * + ****************************************************************************/ + +#ifdef IMX9_HAVE_UART +void uart_serialinit(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_IMX9_IMX_SERIAL_H */