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Update OpenOCD notes and scripts

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3088 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2010-11-07 16:21:12 +00:00
parent 1cc1905a3f
commit 451f83fab8
3 changed files with 212 additions and 30 deletions
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configs/olimex-lpc1766stk/tools/olimex.cfg
+49 -27
View File
@@ -1,3 +1,5 @@
# NXP LPC1766 Cortex-M3 with 256kB Flash and 32kB+32kB Local On-Chip SRAM,
#daemon configuration
telnet_port 4444
gdb_port 3333
@@ -8,7 +10,9 @@ ft2232_device_desc "Olimex OpenOCD JTAG A"
ft2232_layout "olimex-jtag"
ft2232_vid_pid 0x15BA 0x0003
# NXP LPC1766 Cortex-M3 with 256kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
# LPC17xx chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -16,12 +20,18 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME lpc1766
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
if { [info exists CCLK ] } {
set _CCLK $CCLK
} else {
set _ENDIAN little
set _CCLK 4000
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -29,33 +39,45 @@ if { [info exists CPUTAPID ] } {
}
#delays on reset lines
jtag_nsrst_delay 200
adapter_nsrst_delay 200
jtag_ntrst_delay 200
# LPC2000 & LPC1700 -> SRST causes TRST
reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
# LPC1766 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
# REVISIT is there any good reason to have this reset-init event handler??
# Normally they should set up (board-specific) clocking then probe the flash...
$_TARGETNAME configure -event reset-init {
# Force NVIC.VTOR to point to flash at 0 ...
# WHY? This is it's reset value; we run right after reset!!
mwb 0xE000ED08 0x00
}
# LPC1766 has 256kB of user-available FLASH (bootloader is located in separate dedicated region).
# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
# LPC1766 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
# LPC1766 has 256kB of flash memory, managed by ROM code (including a
# boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc1700 80000 calc_checksum
flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME \
lpc1700 $_CCLK calc_checksum
# 4MHz / 6 = 666kHz, so use 500
jtag_khz 100
# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
jtag_khz 10
$_TARGETNAME configure -event reset-init {
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
# and reside in flash instead).
#
# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
# Bit Symbol Value Description Reset
# value
# 0 MAP Memory map control. 0
# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
# 1 User mode. The on-chip Flash memory is mapped to address 0.
# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
#
# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1766&type=user
mww 0x400FC040 0x01
}
configs/olimex-lpc1766stk/tools/oocd.sh
+13 -3
View File
@@ -1,4 +1,7 @@
#!/bin/sh
#
# See configs/olimex-lpc1766stk/README.txt for information about
# this file.
TOPDIR=$1
USAGE="$0 <TOPDIR> [-d]"
@@ -8,10 +11,16 @@ if [ -z "${TOPDIR}" ]; then
exit 1
fi
OPENOCD_PATH="/cygdrive/c/OpenOCD/openocd-0.4.0/src"
# Assume that OpenOCD was installed and at /usr/local/bin. Uncomment
# the following to run directly from the build directory
#OPENOCD_PATH="/home/OpenOCD/openocd/src"
#TARGET_PATH="/home/OpenOCD/openocd/tcl"
OPENOCD_PATH="/usr/local/bin"
TARGET_PATH="/usr/local/share/openocd/scripts"
OPENOCD_EXE=openocd.exe
OPENOCD_CFG="${TOPDIR}/configs/olimex-lpc1766stk/tools/olimex.cfg"
OPENOCD_ARGS="-f `cygpath -w ${OPENOCD_CFG}`"
OPENOCD_ARGS="-f ${OPENOCD_CFG} -s ${TARGET_PATH}"
if [ "X$2" = "X-d" ]; then
OPENOCD_ARGS=$OPENOCD_ARGS" -d3"
@@ -32,7 +41,8 @@ if [ ! -f ${OPENOCD_CFG} ]; then
fi
echo "Starting OpenOCD"
${OPENOCD_PATH}/${OPENOCD_EXE} ${OPENOCD_ARGS} &
cd ${OPENOCD_PATH} || { echo "Failed to CD to ${OPENOCD_PATH}"; exit 1; }
${OPENOCD_EXE} ${OPENOCD_ARGS} &
echo "OpenOCD daemon started"
ps -ef | grep openocd
echo "In GDB: target remote localhost:3333"