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risc-v/mpfs: add CoreMMC support
This adds support for the CoreMMC v3.1 FPGA driver as described in Microchip Handbook HB0510. The driver doesn't support DMA. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This commit is contained in:
Eero Nurkkala
committed by
Xiang Xiao
Xiang Xiao
parent
f141a6480c
commit
4494e75e87
@@ -325,6 +325,25 @@ config MPFS_EMMCSD
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---help---
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---help---
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Selects the MPFS eMMCSD driver.
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Selects the MPFS eMMCSD driver.
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config MPFS_COREMMC
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bool "COREMMC"
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select ARCH_HAVE_SDIO
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select SDIO_BLOCKSETUP
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default n
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---help---
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Selects the MPFS CoreMMC driver.
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config MPFS_COREMMC_BASE
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hex "Base address for the CoreMMC instance"
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default 0x60030000
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depends on MPFS_COREMMC
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config MPFS_COREMMC_IRQNUM
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int "Number of F2H interrupt"
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default 5
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range 0 63
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depends on MPFS_COREMMC
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config MPFS_IHC_CLIENT
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config MPFS_IHC_CLIENT
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bool "IHC slave"
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bool "IHC slave"
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depends on RPTUN && !MPFS_BOOTLOADER
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depends on RPTUN && !MPFS_BOOTLOADER
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@@ -62,6 +62,10 @@ ifeq ($(CONFIG_MPFS_EMMCSD),y)
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CHIP_CSRCS += mpfs_emmcsd.c
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CHIP_CSRCS += mpfs_emmcsd.c
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endif
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endif
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ifeq ($(CONFIG_MPFS_COREMMC),y)
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CHIP_CSRCS += mpfs_coremmc.c
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endif
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ifeq ($(CONFIG_MPFS_ETHMAC),y)
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ifeq ($(CONFIG_MPFS_ETHMAC),y)
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CHIP_CSRCS += mpfs_ethernet.c
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CHIP_CSRCS += mpfs_ethernet.c
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endif
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endif
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@@ -0,0 +1,311 @@
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/****************************************************************************
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* arch/risc-v/src/mpfs/hardware/mpfs_coremmc.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_COREMMC_H
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#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_COREMMC_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define MPFS_COREMMC_SR_OFFSET 0x00
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#define MPFS_COREMMC_VR_OFFSET 0x01
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#define MPFS_COREMMC_MJVR_OFFSET 0x02
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#define MPFS_COREMMC_MIVR_OFFSET 0x03
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#define MPFS_COREMMC_CMDX_OFFSET 0x04
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#define MPFS_COREMMC_ARG1_OFFSET 0x08
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#define MPFS_COREMMC_ARG2_OFFSET 0x09
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#define MPFS_COREMMC_ARG3_OFFSET 0x0a
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#define MPFS_COREMMC_ARG4_OFFSET 0x0b
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#define MPFS_COREMMC_RR0_OFFSET 0x10
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#define MPFS_COREMMC_RR1_OFFSET 0x14
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#define MPFS_COREMMC_RR2_OFFSET 0x15
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#define MPFS_COREMMC_RR3_OFFSET 0x16
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#define MPFS_COREMMC_RR4_OFFSET 0x17
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#define MPFS_COREMMC_RR5_OFFSET 0x18
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#define MPFS_COREMMC_RR6_OFFSET 0x19
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#define MPFS_COREMMC_RR7_OFFSET 0x1a
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#define MPFS_COREMMC_RR8_OFFSET 0x1b
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#define MPFS_COREMMC_RR9_OFFSET 0x1c
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#define MPFS_COREMMC_RR10_OFFSET 0x1d
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#define MPFS_COREMMC_RR11_OFFSET 0x1e
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#define MPFS_COREMMC_RR12_OFFSET 0x1f
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#define MPFS_COREMMC_RR13_OFFSET 0x20
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#define MPFS_COREMMC_RR14_OFFSET 0x21
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#define MPFS_COREMMC_RR15_OFFSET 0x22
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#define MPFS_COREMMC_WDR_OFFSET 0x24
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#define MPFS_COREMMC_RDR_OFFSET 0x28
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#define MPFS_COREMMC_IMR_OFFSET 0x2c
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#define MPFS_COREMMC_SBIMR_OFFSET 0x2d
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#define MPFS_COREMMC_MBIMR_OFFSET 0x2e
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#define MPFS_COREMMC_ISR_OFFSET 0x30
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#define MPFS_COREMMC_SBISR_OFFSET 0x31
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#define MPFS_COREMMC_MBISR_OFFSET 0x32
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#define MPFS_COREMMC_ICR_OFFSET 0x34
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#define MPFS_COREMMC_SBICR_OFFSET 0x35
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#define MPFS_COREMMC_MBICR_OFFSET 0x36
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#define MPFS_COREMMC_CTRL_OFFSET 0x38
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#define MPFS_COREMMC_SBCSR_OFFSET 0x39
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#define MPFS_COREMMC_MBCSR_OFFSET 0x3a
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#define MPFS_COREMMC_RSPTO_OFFSET 0x3c
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#define MPFS_COREMMC_DATATO_OFFSET 0x40
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#define MPFS_COREMMC_BLR_OFFSET 0x44
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#define MPFS_COREMMC_DCTRL_OFFSET 0x48
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#define MPFS_COREMMC_CLKR_OFFSET 0x4c
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#define MPFS_COREMMC_BCR_OFFSET 0x50
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#define MPFS_COREMMC_MAX_OFFSET (MPFS_COREMMC_BCR_OFFSET + 0x4)
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/* Status register */
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#define MPFS_COREMMC_SR_RDRE (1 << 7) /* Response Data Ready */
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#define MPFS_COREMMC_SR_SWFF (1 << 6) /* Write FIFO Full */
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#define MPFS_COREMMC_SR_SRFF (1 << 5) /* Read FIFO Full */
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#define MPFS_COREMMC_SR_SWFE (1 << 4) /* Write FIFO Empty */
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#define MPFS_COREMMC_SR_SRFE (1 << 3) /* Read FIFO Empty */
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#define MPFS_COREMMC_SR_EBOD (1 << 2) /* Buffer Overflow */
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#define MPFS_COREMMC_SR_EBUD (1 << 1) /* Buffer Underrun */
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#define MPFS_COREMMC_SR_ECRD (1 << 0) /* CRC Error Detected */
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/* Version register */
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#define COREMMC_VR_FIFODEPTH (0x3 << 4)
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#define COREMMC_VR_FIFODEPTH_512 0x00
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#define COREMMC_VR_FIFODEPTH_4K 0x01
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#define COREMMC_VR_FIFODEPTH_16K 0x02
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#define COREMMC_VR_FIFODEPTH_32K 0x03
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/* Interrupt Mask Register */
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#define COREMMC_IMR_UER (1 << 7)
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#define COREMMC_IMR_SBI (1 << 6)
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#define COREMMC_IMR_TBI (1 << 5)
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#define COREMMC_IMR_TXI (1 << 4)
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#define COREMMC_IMR_RRI (1 << 3)
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#define COREMMC_IMR_CSI (1 << 2)
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#define COREMMC_IMR_BOI (1 << 1)
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#define COREMMC_IMR_BUI (1 << 0)
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#define COREMMC_IMR_ERROR (COREMMC_IMR_UER | COREMMC_IMR_SBI | \
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COREMMC_IMR_TBI | COREMMC_IMR_TXI | \
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COREMMC_IMR_TXI | COREMMC_IMR_BOI | \
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COREMMC_IMR_BUI)
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/* Single Block Interrupt Mask Register */
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#define COREMMC_SBIMR_WDATAINFIFOTO (1 << 7)
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#define COREMMC_SBIMR_WBUSYTO (1 << 6)
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#define COREMMC_SBIMR_WCRCSTAERR (1 << 5)
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#define COREMMC_SBIMR_RSTPERR (1 << 4)
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#define COREMMC_SBIMR_RSTTO (1 << 3)
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#define COREMMC_SBIMR_CRCERR (1 << 2)
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#define COREMMC_SBIMR_RDONE (1 << 1)
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#define COREMMC_SBIMR_WDONE (1 << 0)
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#define COREMMC_SBIMR_ERROR (COREMMC_SBIMR_WDATAINFIFOTO | \
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COREMMC_SBIMR_WBUSYTO | \
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COREMMC_SBIMR_WCRCSTAERR | \
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COREMMC_SBIMR_RSTPERR | \
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COREMMC_SBIMR_RSTTO | \
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COREMMC_SBIMR_CRCERR)
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/* Multiple Block Interrupt Mask Register */
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#define COREMMC_MBIMR_WDATAINFIFOTO (1 << 7)
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#define COREMMC_MBIMR_WBUSYTO (1 << 6)
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#define COREMMC_MBIMR_WCRCSTAERR (1 << 5)
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#define COREMMC_MBIMR_RSTPERR (1 << 4)
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#define COREMMC_MBIMR_RSTTO (1 << 3)
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#define COREMMC_MBIMR_CRCERR (1 << 2)
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#define COREMMC_MBIMR_RDONE (1 << 1)
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#define COREMMC_MBIMR_WDONE (1 << 0)
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#define COREMMC_MBIMR_ERROR (COREMMC_MBIMR_WDATAINFIFOTO | \
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COREMMC_MBIMR_WBUSYTO | \
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COREMMC_MBIMR_WCRCSTAERR | \
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COREMMC_MBIMR_RSTPERR | \
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COREMMC_MBIMR_RSTTO | \
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COREMMC_MBIMR_CRCERR)
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/* Interrupt Status Register */
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#define COREMMC_ISR_UER (1 << 7) /* User error is detected. Write FIFO overrun or Read FIFO underrun error. */
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#define COREMMC_ISR_SBI (1 << 6) /* Response start bit error detected or time-out error while waiting for a response. */
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#define COREMMC_ISR_TBI (1 << 5) /* Stop bit error is detected on response to command. */
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#define COREMMC_ISR_TXI (1 << 4) /* Transmit bit error is detected on response to command. */
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#define COREMMC_ISR_RRI (1 << 3) /* Response to command received. */
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#define COREMMC_ISR_CSI (1 << 2) /* Command sent. */
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#define COREMMC_ISR_BOI (1 << 1) /* Buffer overflow occurred. Read FIFO was full. */
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#define COREMMC_ISR_BUI (1 << 0) /* Underrun occurred. Write FIFO was empty. */
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#define COREMMC_ISR_ERROR (COREMMC_ISR_UER | COREMMC_ISR_SBI | \
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COREMMC_ISR_TBI | COREMMC_ISR_TXI | \
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COREMMC_ISR_BOI | COREMMC_ISR_BUI)
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/* Single and Multiple Block Interrupt Status Registers */
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/* Single / multiple block Write FIFO timeout. Asserted when less than block
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* length amount of data in the Write FIFO after the period defined in the
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* DATOTO register at the start of a block within a single / multiple block
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* write transfer. Prevents Write FIFO underruns during Multiple block write
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* transfers.
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*/
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#define COREMMC_XBISR_WDATAINFIFOTO (1 << 7)
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/* Single / multiple block write busy timeout. Set when eMMC slave device
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* holds DAT0 low for longer than the period defined in DATATO register at
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* the start of a block within a single / multiple block write transfer.
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* Indicates that the slave device is not ready to receive data.
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*/
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#define COREMMC_XBISR_WBUSYTO (1 << 6)
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/* Single / multiple block write CRC response error. Set when start bit of
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* CRC Status frame not received within period defined in DATATO register or
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* when no valid stop bit detected for CRC status frame for a block within a
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* single / multiple block write transfer.
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*/
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#define COREMMC_XBISR_WCRCSTAERR (1 << 5)
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/* Single / multiple Block Read Stop Error. Set when valid stop bit not
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* detected on all active DATI lines for a block within a single / multiple
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* block read transfer.
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*/
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#define COREMMC_XBISR_RSTPERR (1 << 4)
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/* Single / multiple Block Read start time-out. Set when no incoming
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* start-bit found on DAT for period defined in DATATO register for a block
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* within a single / multiple block read transfer.
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*/
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#define COREMMC_XBISR_RSTTO (1 << 3)
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/* Single / multiple block read or write encountered CRC error. */
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#define COREMMC_XBISR_CRCERR (1 << 2)
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/* Single / multiple block read done. */
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#define COREMMC_XBISR_RDONE (1 << 1)
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/* Single / multiple block write done. */
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#define COREMMC_XBISR_WDONE (1 << 0)
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#define COREMMC_XBISR_ERROR (COREMMC_XBISR_WDATAINFIFOTO | \
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COREMMC_XBISR_WBUSYTO | \
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COREMMC_XBISR_WCRCSTAERR | \
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COREMMC_XBISR_RSTPERR | \
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COREMMC_XBISR_RSTTO | \
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COREMMC_XBISR_CRCERR)
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/* Interrupt Clear Register */
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#define COREMMC_ICR_CLRUER (1 << 7)
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#define COREMMC_ICR_CLRSBI (1 << 6)
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#define COREMMC_ICR_CLRTBI (1 << 5)
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#define COREMMC_ICR_CLRTXI (1 << 4)
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#define COREMMC_ICR_CLRRRI (1 << 3)
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#define COREMMC_ICR_CLRCSI (1 << 2)
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#define COREMMC_ICR_CLRBOI (1 << 1)
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#define COREMMC_ICR_CLRBUI (1 << 0)
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#define COREMMC_ICR_ERROR (COREMMC_ICR_CLRUER | \
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COREMMC_ICR_CLRSBI | \
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COREMMC_ICR_CLRTBI | \
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COREMMC_ICR_CLRTXI | \
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COREMMC_ICR_CLRBOI | \
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COREMMC_ICR_CLRBUI)
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/* Single Block Interrupt Clear Register */
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#define COREMMC_SBICR_WDATAINFIFOTO (1 << 7)
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#define COREMMC_SBICR_WBUSYTO (1 << 6)
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#define COREMMC_SBICR_WCRCSTAERR (1 << 5)
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#define COREMMC_SBICR_RSTPERR (1 << 4)
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#define COREMMC_SBICR_RSTTO (1 << 3)
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#define COREMMC_SBICR_CRCERR (1 << 2)
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#define COREMMC_SBICR_RDONE (1 << 1)
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#define COREMMC_SBICR_WDONE (1 << 0)
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#define COREMMC_SBICR_ERROR (COREMMC_SBICR_WDATAINFIFOTO | \
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COREMMC_SBICR_WBUSYTO | \
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COREMMC_SBICR_WCRCSTAERR | \
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COREMMC_SBICR_RSTPERR | \
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COREMMC_SBICR_RSTTO | \
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COREMMC_SBICR_CRCERR)
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/* Multiple Block Interrupt Clear Register */
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#define COREMMC_MBICR_WDATAINFIFOTO (1 << 7)
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#define COREMMC_MBICR_WBUSYTO (1 << 6)
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#define COREMMC_MBICR_WCRCSTAERR (1 << 5)
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#define COREMMC_MBICR_RSTPERR (1 << 4)
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#define COREMMC_MBICR_RSTTO (1 << 3)
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#define COREMMC_MBICR_CRCERR (1 << 2)
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#define COREMMC_MBICR_RDONE (1 << 1)
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#define COREMMC_MBICR_WDONE (1 << 0)
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#define COREMMC_MBICR_ERROR (COREMMC_MBICR_WDATAINFIFOTO | \
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COREMMC_MBICR_WBUSYTO | \
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COREMMC_MBICR_WCRCSTAERR | \
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COREMMC_MBICR_RSTPERR | \
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COREMMC_MBICR_RSTTO | \
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COREMMC_MBICR_CRCERR)
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/* Control Register */
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#define COREMMC_CTRL_BUSY (1 << 7) /* Slave device is indicating that it is busy by asserting DAT[0] low. */
|
||||||
|
#define COREMMC_CTRL_RESERVED (1 << 6) /* Reserved. */
|
||||||
|
#define COREMMC_CTRL_FIFORESET (1 << 5) /* FIFO reset. */
|
||||||
|
#define COREMMC_CTRL_CMDFORCELOW (1 << 4) /* Force CMD line to 0 (low). Used for boot operation. */
|
||||||
|
#define COREMMC_CTRL_MIDLE (1 << 3) /* MMC Idle. When set to 1, it indicates that the core is in Idle state. */
|
||||||
|
#define COREMMC_CTRL_CLKOE (1 << 2) /* CLK Output Enable. */
|
||||||
|
#define COREMMC_CTRL_SLRST (1 << 1) /* Slave Reset. */
|
||||||
|
#define COREMMC_CTRL_SWRST (1 << 0) /* Software reset */
|
||||||
|
|
||||||
|
/* Single Block Control and Status Register */
|
||||||
|
|
||||||
|
#define COREMMC_SBCSR_RESERVED (1 << 7)
|
||||||
|
#define COREMMC_SBCSR_WST (0x7 << 4) /* Single Block Write Status - CRC Status bits. Good CRC Status = 010. */
|
||||||
|
#define COREMMC_SBCSR_CRCERR (1 << 3) /* Single Block CRC Error. */
|
||||||
|
#define COREMMC_SBCSR_DONE (1 << 2) /* Single Block Done. */
|
||||||
|
#define COREMMC_SBCSR_RSTRT (1 << 1) /* Single Block Read Start. */
|
||||||
|
#define COREMMC_SBCSR_WSTRT (1 << 0) /* Single Block Write Start. */
|
||||||
|
|
||||||
|
/* Multiple Block Control and Status Register */
|
||||||
|
|
||||||
|
#define COREMMC_MBCSR_RESERVED (1 << 7)
|
||||||
|
#define COREMMC_MBCSR_WST (0x7 << 4) /* Multiple Block Write Status - CRC Status bits. Good CRC Status = 010. */
|
||||||
|
#define COREMMC_MBCSR_CRCERR (1 << 3) /* Multiple Block CRC Error. */
|
||||||
|
#define COREMMC_MBCSR_DONE (1 << 2) /* Multiple Block Done. */
|
||||||
|
#define COREMMC_MBCSR_RSTRT (1 << 1) /* Multiple Block Read Start. */
|
||||||
|
#define COREMMC_MBCSR_WSTRT (1 << 0) /* Multiple Block Write Start. */
|
||||||
|
|
||||||
|
/* Data Control Register */
|
||||||
|
|
||||||
|
#define COREMMC_DCTRL_DSIZE (0x3 << 0)
|
||||||
|
#define COREMMC_DCTRL_DSIZE_1BIT (0x0)
|
||||||
|
#define COREMMC_DCTRL_DSIZE_4BIT (0x1)
|
||||||
|
#define COREMMC_DCTRL_DSIZE_8BIT (0x2)
|
||||||
|
|
||||||
|
#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_COREMMC_H */
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,113 @@
|
|||||||
|
/****************************************************************************
|
||||||
|
* arch/risc-v/src/mpfs/mpfs_coremmc.h
|
||||||
|
*
|
||||||
|
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||||
|
* contributor license agreements. See the NOTICE file distributed with
|
||||||
|
* this work for additional information regarding copyright ownership. The
|
||||||
|
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||||
|
* "License"); you may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||||
|
* License for the specific language governing permissions and limitations
|
||||||
|
* under the License.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_RISCV_SRC_MPFS_MPFS_COREMMC_H
|
||||||
|
#define __ARCH_RISCV_SRC_MPFS_MPFS_COREMMC_H
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Included Files
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
#include <sys/types.h>
|
||||||
|
#include <stdbool.h>
|
||||||
|
|
||||||
|
#include "chip.h"
|
||||||
|
#include "hardware/mpfs_coremmc.h"
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Public Function Prototypes
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
#undef EXTERN
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
#define EXTERN extern "C"
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#else
|
||||||
|
#define EXTERN extern
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: sdio_initialize
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Initialize SDIO for operation.
|
||||||
|
*
|
||||||
|
* Input Parameters:
|
||||||
|
* slotno - Not used.
|
||||||
|
*
|
||||||
|
* Returned Values:
|
||||||
|
* A reference to an SDIO interface structure. NULL is returned on
|
||||||
|
* failures.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
struct sdio_dev_s; /* See include/nuttx/sdio.h */
|
||||||
|
struct sdio_dev_s *sdio_initialize(int slotno);
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: sdio_mediachange
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Called by board-specific logic -- possibly from an interrupt handler --
|
||||||
|
* in order to signal to the driver that a card has been inserted or
|
||||||
|
* removed from the slot.
|
||||||
|
*
|
||||||
|
* Input Parameters:
|
||||||
|
* dev - An instance of the SDIO driver device state structure.
|
||||||
|
* cardinslot - true is a card has been detected in the slot; false if a
|
||||||
|
* card has been removed from the slot. Only transitions
|
||||||
|
* (inserted->removed or removed->inserted should be reported)
|
||||||
|
*
|
||||||
|
* Returned Values:
|
||||||
|
* None
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot);
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: sdio_wrprotect
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Called by board-specific logic to report if the card in the slot is
|
||||||
|
* mechanically write protected.
|
||||||
|
*
|
||||||
|
* Input Parameters:
|
||||||
|
* dev - An instance of the SDIO driver device state structure.
|
||||||
|
* wrprotect - true is a card is writeprotected.
|
||||||
|
*
|
||||||
|
* Returned Values:
|
||||||
|
* None
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect);
|
||||||
|
|
||||||
|
#undef EXTERN
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __ASSEMBLY__ */
|
||||||
|
#endif /* __ARCH_RISCV_SRC_MPFS_MPFS_COREMMC_H */
|
||||||
Reference in New Issue
Block a user