Add special register definitions needed for z80181 and z80182

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5434 42af7a65-404d-4744-a932-0658087f49c3

arch/z80/include/z180/chip.h

@@ -93,6 +93,9 @@
       defined(CONFIG_ARCH_CHIP_Z8018006VEG)    /* 68-pin PLCC */
 
 #  undef  HAVE_Z8S180                             /* Not Z8S180 (5V) or Z8L180 (3.3V) core */
+#  define HAVE_Z8X180    1                        /* Z8x180 registers */
+#  undef  HAVE_Z8X181                             /* Z8x181 registers */
+#  undef  HAVE_Z8X182                             /* Z8x182 registers */
 #  define HAVE ROM       0                        /* No on-chip ROM */
 #  define HAVE_SERIALIO  1                        /* Have clocked serial I/O */
 #  undef  HAVE_WDT                                /* No Watchdog timer */
@@ -117,6 +120,9 @@
       defined(CONFIG_ARCH_CHIP_Z8018006FSG)    /* 80-pin QFP (11 pins N/C) 6MHz 5V */
 
 #  undef  HAVE_Z8S180                             /* Not Z8S180 (5V) or Z8L180 (3.3V) core */
+#  define HAVE_Z8X180    1                        /* Z8x180 registers */
+#  undef  HAVE_Z8X181                             /* Z8x181 registers */
+#  undef  HAVE_Z8X182                             /* Z8x182 registers */
 #  define HAVE ROM       0                        /* No on-chip ROM */
 #  undef  HAVE_SERIALIO                           /* No clocked serial I/O ? */
 #  undef  HAVE_WDT                                /* No Watchdog timer */
@@ -137,6 +143,9 @@
       defined(CONFIG_ARCH_CHIP_Z8018008PEG)
 
 #  undef  HAVE_Z8S180                             /* Not Z8S180 (5V) or Z8L180 (3.3V) core */
+#  define HAVE_Z8X180    1                        /* Z8x180 registers */
+#  undef  HAVE_Z8X181                             /* Z8x181 registers */
+#  undef  HAVE_Z8X182                             /* Z8x182 registers */
 #  define HAVE ROM       0                        /* No on-chip ROM */
 #  define HAVE_SERIALIO  1                        /* Have clocked serial I/O */
 #  undef  HAVE_WDT                                /* No Watchdog timer */
@@ -175,6 +184,9 @@
 #elif defined(CONFIG_ARCH_CHIP_Z8018110FEG)       /* 100-pin QFP */
 
 #  undef  HAVE_Z8S180                             /* Not Z8S180 (5V) or Z8L180 (3.3V) core */
+#  undef  HAVE_Z8X180                             /* Z8x180 registers */
+#  define HAVE_Z8X181    1                        /* Z8x181 registers */
+#  undef  HAVE_Z8X182                             /* Z8x182 registers */
 #  define HAVE ROM       0                        /* No on-chip ROM */
 #  define HAVE_SERIALIO  1                        /* Have clocked serial I/O */
 #  undef  HAVE_WDT                                /* No Watchdog timer */
@@ -220,6 +232,9 @@
       defined(CONFIG_ARCH_CHIP_Z8018233ASG)       /* 100-pin LQFP 33MHz 5V */
 
 #  undef  HAVE_Z8S180                             /* Not Z8S180 (5V) or Z8L180 (3.3V) core */
+#  undef  HAVE_Z8X180                             /* Z8x180 registers */
+#  undef  HAVE_Z8X181                             /* Z8x181 registers */
+#  define HAVE_Z8X182    1                        /* Z8x182 registers */
 #  define HAVE ROM       0                        /* No on-chip ROM */
 #  define HAVE_SERIALIO  1                        /* Have clocked serial I/O */
 #  undef  HAVE_WDT                                /* No Watchdog timer */
@@ -304,6 +319,9 @@
       defined(CONFIG_ARCH_CHIP_Z8L18020PSG)
 
 #  define HAVE_Z8S180    1                        /* Uses Z8S180 (5V) or Z8L180 (3.3V) core */
+#  define HAVE_Z8X180    1                        /* Z8x180 registers */
+#  undef  HAVE_Z8X181                             /* Z8x181 registers */
+#  undef  HAVE_Z8X182                             /* Z8x182 registers */
 #  define HAVE ROM       0                        /* No on-chip ROM */
 #  define HAVE_SERIALIO  1                        /* Have clocked serial I/O */
 #  undef  HAVE_WDT                                /* No Watchdog timer */
@@ -348,6 +366,9 @@
       defined(CONFIG_ARCH_CHIP_Z8L18220AEG)
 
 #  define HAVE_Z8S180    1                        /* Uses Z8S180 (5V) or Z8L180 (3.3V) core */
+#  undef  HAVE_Z8X180                             /* Z8x180 registers */
+#  undef  HAVE_Z8X181                             /* Z8x181 registers */
+#  define HAVE_Z8X182    1                        /* Z8x182 registers */
 #  define HAVE ROM       0                        /* No on-chip ROM */
 #  define HAVE_SERIALIO  1                        /* Have clocked serial I/O */
 #  undef  HAVE_WDT                                /* No Watchdog timer */
@@ -405,6 +426,9 @@
       defined(CONFIG_ARCH_CHIP_Z8S18010FEG)
 
 #  define HAVE_Z8S180    1                        /* Uses Z8S180 (5V) or Z8L180 (3.3V) core */
+#  define HAVE_Z8X180    1                        /* Z8x180 registers */
+#  undef  HAVE_Z8X181                             /* Z8x181 registers */
+#  undef  HAVE_Z8X182                             /* Z8x182 registers */
 #  define HAVE ROM       0                        /* No on-chip ROM */
 #  define HAVE_SERIALIO  1                        /* Have clocked serial I/O */
 #  undef  HAVE_WDT                                /* No Watchdog timer */

arch/z80/src/z180/z180_iomap.h

@@ -1,4 +1,4 @@
-/****************************************************************************
+/************************************************************************************
  * arch/z80/src/z180/z180_iomap.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
@@ -31,101 +31,260 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ****************************************************************************/
+ ************************************************************************************/
 
 #ifndef __ARCH_Z80_SRC_Z180_Z180_IOMAP_H
 #define __ARCH_Z80_SRC_Z180_Z180_IOMAP_H
 
-/****************************************************************************
+/************************************************************************************
  * Included Files
- ****************************************************************************/
+ ************************************************************************************/
 
 #include <arch/z180/chip.h>
 
-/****************************************************************************
+/************************************************************************************
  * Pre-processor Definitions
- ****************************************************************************/
+ ************************************************************************************/
+/* Configuration ********************************************************************/
 
- /* Z180 Register Bit addresses **********************************************/
+/* These registers may be relocated to multiples of 0x40 by setting the IO Control
+ * Register (ICR).  Relocatable to 0x40-0x7f, or 0x80-0xbf. The configuration setting,
+ * CONFIG_Z180_SFROFFSET, indicates that offset (but is not fully supported yet!)
+ */
 
-#define Z180_ASCI0_CNTLA     0x00 /* ASCI Control Register A Ch 0 */
+#ifdef CONFIG_Z180_SFROFFSET
-#define Z180_ASCI1_CNTLA     0x01 /* ASCI Control Register A Ch 1 */
+#  define SFR_OFFSET CONFIG_Z180_SFROFFSET
-#define Z180_ASCI0_CNTLB     0x02 /* ASCI Control Register B Ch 0 */
+#else
-#define Z180_ASCI1_CNTLB     0x03 /* ASCI Control Register B Ch 1 */
+#  define SFR_OFFSET 0
-#define Z180_ASCI0_STAT      0x04 /* ASCI Status Register Ch 0 */
-#define Z180_ASCI1_STAT      0x05 /* ASCI Status Register Ch 1 */
-#define Z180_ASCI0_TDR       0x06 /* ASCI Transmit Data Register Ch 0 */
-#define Z180_ASCI1_TDR       0x07 /* ASCI Transmit Data Register Ch 1 */
-#define Z180_ASCI0_RDR       0x08 /* ASCI Receive Data Register Ch 0 */
-#define Z180_ASCI1_RDR       0x09 /* ASCI Receive Data Register Ch 1 */
-
-#define Z180_CSIO_CNTR       0x0a /* CSI/O Control Register */
-#define Z180_CSIO_TRD        0x0b /* Transmit/Receive Data Register */
-
-#define Z180_TMR0_DRL        0x0c /* Timer Data Register Ch 0 L */
-#define Z180_TMR0_DRH        0x0d /* Data Register Ch 0 H */
-#define Z180_TMR0_RLDRL      0x0e /* Reload Register Ch 0 L */
-#define Z180_TMR0_RLDRH      0x0f /* Reload Register Ch 0 H */
-#define Z180_TMR_TCR         0x10 /* Timer Control Register */
-
-#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
-#  define Z180_ASCI0_ASEXT   0x12 /* ASCI Extension Control Register */
-#  define Z180_ASCI1_ASEXT   0x13 /* ASCI Extension Control Register */
 #endif
 
-#define Z180_TMR1_DRL        0x14 /* Data Register Ch 1 L */
+/* Z180 Register Bit addresses ******************************************************/
-#define Z180_TMR1_DRH        0x15 /* Data Register Ch 1 H */
+/* ASCI Registers */
-#define Z180_TMR1_RLDRL      0x16 /* Reload Register Ch 1 L */
-#define Z180_TMR1_RLDRH      0x17 /* Reload Register Ch 1 H */
 
-#define Z180_FRC             0x18 /* Free Running Counter */
+#define Z180_ASCI0_CNTLA     (SFR_OFFSET+0x00) /* ASCI Control Register A Ch 0 */
+#define Z180_ASCI1_CNTLA     (SFR_OFFSET+0x01) /* ASCI Control Register A Ch 1 */
+#define Z180_ASCI0_CNTLB     (SFR_OFFSET+0x02) /* ASCI Control Register B Ch 0 */
+#define Z180_ASCI1_CNTLB     (SFR_OFFSET+0x03) /* ASCI Control Register B Ch 1 */
+#define Z180_ASCI0_STAT      (SFR_OFFSET+0x04) /* ASCI Status Register Ch 0 */
+#define Z180_ASCI1_STAT      (SFR_OFFSET+0x05) /* ASCI Status Register Ch 1 */
+#define Z180_ASCI0_TDR       (SFR_OFFSET+0x06) /* ASCI Transmit Data Register Ch 0 */
+#define Z180_ASCI1_TDR       (SFR_OFFSET+0x07) /* ASCI Transmit Data Register Ch 1 */
+#define Z180_ASCI0_RDR       (SFR_OFFSET+0x08) /* ASCI Receive Data Register Ch 0 */
+#define Z180_ASCI1_RDR       (SFR_OFFSET+0x09) /* ASCI Receive Data Register Ch 1 */
 
 #ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
-#  define Z180_ASCI0_ASTCL   0x1a /* ASCI Time Constant Low */
+#  define Z180_ASCI0_ASEXT   (SFR_OFFSET+0x12) /* ASCI Extension Control Register */
-#  define Z180_ASCI0_ASTCH   0x1b /* ASCI Time Constant High */
+#  define Z180_ASCI1_ASEXT   (SFR_OFFSET+0x13) /* ASCI Extension Control Register */
-#  define Z180_ASCI1_ASTCL   0x1c /* ASCI Time Constant Low */
-#  define Z180_ASCI1_ASTCH   0x1d /* ASCI Time Constant High */
-
-#  define Z180_CMR           0x1e /* Clock Multiplier Register */
-#  define Z180_CCR           0x1f /* CPU Control Register */
 #endif
 
-#define Z180_DMA_SAR0L       0x20 /* DMA Source Address Register Ch 0L */
-#define Z180_DMA_SAR0H       0x21 /* DMA Source Address Register Ch 0H */
-#define Z180_DMA_SAR0B       0x22 /* DMA Source Address Register Ch 0B */
-#define Z180_DMA_DAR0L       0x23 /* DMA Destination Address Register Ch 0L */
-#define Z180_DMA_DAR0H       0x24 /* DMA Destination Address Register Ch 0H */
-#define Z180_DMA_DAR0B       0x25 /* DMA Destination Address Register Ch 0B */
-#define Z180_DMA_BCR0L       0x26 /* DMA Byte Count Register Ch 0L */
-#define Z180_DMA_BCR0H       0x27 /* DMA Byte Count Register Ch 0H */
-#define Z180_DMA_MAR1L       0x28 /* DMA Memory Address Register Ch 1L */
-#define Z180_DMA_MAR1H       0x29 /* DMA Memory Address Register Ch 1H */
-#define Z180_DMA_MAR1B       0x2a /* DMA Memory Address Register Ch 1B */
-#define Z180_DMA_IAR1L       0x2b /* DMA I/0 Address Register Ch 1L */
-#define Z180_DMA_IAR1H       0x2c /* DMA I/0 Address Register Ch 1H */
 #ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
-#  define Z180_DMA_IAR1B     0x2d /* DMA I/O Address Register Ch 1B */
+#  define Z180_ASCI0_ASTCL   (SFR_OFFSET+0x1a) /* ASCI Time Constant Low */
+#  define Z180_ASCI0_ASTCH   (SFR_OFFSET+0x1b) /* ASCI Time Constant High */
+#  define Z180_ASCI1_ASTCL   (SFR_OFFSET+0x1c) /* ASCI Time Constant Low */
+#  define Z180_ASCI1_ASTCH   (SFR_OFFSET+0x1d) /* ASCI Time Constant High */
 #endif
-#define Z180_DMA_BCR1L       0x2e /* DMA Byte Count Register Ch 1L */
-#define Z180_DMA_BCR1H       0x2f /* DMA Byte Count Register Ch 1H */
-#define Z180_DMA_DSTAT       0x30 /* DMA Status Register */
-#define Z180_DMA_DMODE       0x31 /* DMA Mode Register */
-#define Z180_DMA_DCNTL       0x32 /* DMA/WAIT Control Register */
 
-#define Z180_INT_IL          0x33 /* IL Register (Interrupt Vector Low Register) */
+/* CSI/O Registers */
-#define Z180_INT_ITC         0x34 /* INT/TRAP Control Register */
 
-#define Z180_RCR             0x36 /*  Refresh Control Register */
+#define Z180_CSIO_CNTR       (SFR_OFFSET+0x0a) /* CSI/O Control Register */
+#define Z180_CSIO_TRD        (SFR_OFFSET+0x0b) /* Transmit/Receive Data Register */
 
-#define Z180_MMU_CBR         0x38 /* MMU Common Base Register */
+/* Timer Registers */
-#define Z180_MMU_BBR         0x39 /* MMU Bank Base Register */
-#define Z180_MMU_CBAR        0x3a /* MMU Common/Bank Area Register */
 
-#define Z180_OMCR            0x3e /* Operation Mode Control Register */
+#define Z180_TMR0_DRL        (SFR_OFFSET+0x0c) /* Timer Data Register Ch 0 L */
-#define Z180_ICR             0x3f /* I/O Control Register */
+#define Z180_TMR0_DRH        (SFR_OFFSET+0x0d) /* Data Register Ch 0 H */
+#define Z180_TMR0_RLDRL      (SFR_OFFSET+0x0e) /* Reload Register Ch 0 L */
+#define Z180_TMR0_RLDRH      (SFR_OFFSET+0x0f) /* Reload Register Ch 0 H */
+#define Z180_TMR_TCR         (SFR_OFFSET+0x10) /* Timer Control Register */
 
-/* Z180 Register Bit definitions ********************************************/
+#define Z180_TMR1_DRL        (SFR_OFFSET+0x14) /* Data Register Ch 1 L */
+#define Z180_TMR1_DRH        (SFR_OFFSET+0x15) /* Data Register Ch 1 H */
+#define Z180_TMR1_RLDRL      (SFR_OFFSET+0x16) /* Reload Register Ch 1 L */
+#define Z180_TMR1_RLDRH      (SFR_OFFSET+0x17) /* Reload Register Ch 1 H */
 
+#define Z180_FRC             (SFR_OFFSET+0x18) /* Free Running Counter */
+
+/* DMA Registers */
+
+#define Z180_DMA_SAR0L       (SFR_OFFSET+0x20) /* DMA Source Address Register Ch 0L */
+#define Z180_DMA_SAR0H       (SFR_OFFSET+0x21) /* DMA Source Address Register Ch 0H */
+#define Z180_DMA_SAR0B       (SFR_OFFSET+0x22) /* DMA Source Address Register Ch 0B */
+#define Z180_DMA_DAR0L       (SFR_OFFSET+0x23) /* DMA Destination Address Register Ch 0L */
+#define Z180_DMA_DAR0H       (SFR_OFFSET+0x24) /* DMA Destination Address Register Ch 0H */
+#define Z180_DMA_DAR0B       (SFR_OFFSET+0x25) /* DMA Destination Address Register Ch 0B */
+#define Z180_DMA_BCR0L       (SFR_OFFSET+0x26) /* DMA Byte Count Register Ch 0L */
+#define Z180_DMA_BCR0H       (SFR_OFFSET+0x27) /* DMA Byte Count Register Ch 0H */
+#define Z180_DMA_MAR1L       (SFR_OFFSET+0x28) /* DMA Memory Address Register Ch 1L */
+#define Z180_DMA_MAR1H       (SFR_OFFSET+0x29) /* DMA Memory Address Register Ch 1H */
+#define Z180_DMA_MAR1B       (SFR_OFFSET+0x2a) /* DMA Memory Address Register Ch 1B */
+#define Z180_DMA_IAR1L       (SFR_OFFSET+0x2b) /* DMA I/0 Address Register Ch 1L */
+#define Z180_DMA_IAR1H       (SFR_OFFSET+0x2c) /* DMA I/0 Address Register Ch 1H */
+#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
+#  define Z180_DMA_IAR1B     (SFR_OFFSET+0x2d) /* DMA I/O Address Register Ch 1B */
+#endif
+#define Z180_DMA_BCR1L       (SFR_OFFSET+0x2e) /* DMA Byte Count Register Ch 1L */
+#define Z180_DMA_BCR1H       (SFR_OFFSET+0x2f) /* DMA Byte Count Register Ch 1H */
+#define Z180_DMA_DSTAT       (SFR_OFFSET+0x30) /* DMA Status Register */
+#define Z180_DMA_DMODE       (SFR_OFFSET+0x31) /* DMA Mode Register */
+#define Z180_DMA_DCNTL       (SFR_OFFSET+0x32) /* DMA/WAIT Control Register */
+
+/* System Control Registers */
+
+#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
+#  define Z180_CMR           (SFR_OFFSET+0x1e) /* Clock Multiplier Register */
+#endif
+
+#if defined(HAVE_Z8S180) || defined(HAVE_Z8X182)
+#  define Z180_CCR           (SFR_OFFSET+0x1f) /* CPU Control Register */
+#endif
+
+#define Z180_INT_IL          (SFR_OFFSET+0x33) /* IL Register (Interrupt Vector Low Register) */
+#define Z180_INT_ITC         (SFR_OFFSET+0x34) /* INT/TRAP Control Register */
+
+#define Z180_RCR             (SFR_OFFSET+0x36) /* Refresh Control Register */
+
+#define Z180_MMU_CBR         (SFR_OFFSET+0x38) /* MMU Common Base Register */
+#define Z180_MMU_BBR         (SFR_OFFSET+0x39) /* MMU Bank Base Register */
+#define Z180_MMU_CBAR        (SFR_OFFSET+0x3a) /* MMU Common/Bank Area Register */
+
+#define Z180_OMCR            (SFR_OFFSET+0x3e) /* Operation Mode Control Register */
+#define Z180_ICR             (SFR_OFFSET+0x3f) /* I/O Control Register */
+
+/* The following registers are not relocatable */
+/* Registers unique to Z8x181 class CPUs */
+
+#ifdef HAVE_Z8X181
+
+/* PIA Registers */
+
+#  define Z181_PIA1_DDR      0xe0 /* PIA1 Data Direction Register */
+#  define Z181_PIA1_DP       0xe1 /* PIA1 Data Port */
+#  define Z181_PIA2_DDR      0xe2 /* PIA2 Data Direction Register */
+#  define Z181_PIA1_DP       0xe3 /* PIA2 Data Register */
+
+/* CTC Registers */
+
+#  define Z181_CTC0          0xe4 /* CTC Channel 0 Control Register */
+#  define Z181_CTC1          0xe5 /* CTC Channel 1 Control Register */
+#  define Z181_CTC2          0xe6 /* CTC Channel 2 Control Register */
+#  define Z181_CTC3          0xe7 /* CTC Channel 3 Control Register */
+
+/* SCC Registers */
+
+#  define Z181_SCC_CR        0xe8 /* SCC Control Register */
+#  define Z181_SCC_DR        0xe9 /* SCC Data Register */
+
+/* System Control Registers */
+
+#  define Z181_RAM_UBR       0xea /* RAM Upper Boundary Address Register */
+#  define Z181_RAM_LBR       0xeb /* RAM Lower Boundary Address Register*/
+#  define Z181_ROM_BR        0xec /* ROM Address Boundary Register */
+#  define Z181_SCR           0xed /* System Configuration Register */
+#endif
+
+/* Registers unique to Z8x182 class CPUs */
+
+#ifdef HAVE_Z8X182
+#  define Z182_WSGCS       0xd8 /* WSG Chip Select Register */
+#  define Z182_ENH182      0xd9 /* Z80182 Enhancements Register */
+#  define Z182_INTEDGE     0xdf /* Interrupt Edge/Pin MUX Control */
+#  define Z182_PINMUX      0xdf /* Interrupt Edge/Pin MUX Control */
+
+/* PIA Registers */
+
+#  define Z182_PA_DDR      0xed /* PA Data Direction Register */
+#  define Z182_PA_DR       0xee /* PA Data Register */
+#  define Z182_PB_DDR      0xe4 /* PB Data Direction Register */
+#  define Z182_PB_DR       0xe5 /* PB Data Register */
+#  define Z182_PC_DDR      0xdd /* PC Data Direction Register */
+#  define Z182_PC_DR       0xde /* PC Data Register */
+
+/* ESCC Registers */
+
+#  define Z182_ESCCA_CR    0xe0 /* ESCC Chan A Control Register */
+#  define Z182_ESCCA_DR    0xe1 /* ESCC Chan A Data Register */
+#  define Z182_ESCCB_CR    0xe2 /* ESCC Chan B Control Register */
+#  define Z182_ESCCB_DR    0xe3 /* ESCC Chan B Data Register */
+
+/* System Control Registers */
+
+#  define Z182_RAM_UBR     0xe6 /* RAMUBR RAM Upper Boundary Register */
+#  define Z182_RAM_LBR     0xe7 /* RAMLBR RAM Lower Boundary Register */
+#  define Z182_ROM_BR      0xe8 /* ROM Address Boundary Register */
+#  define Z182_SCR         0xef /* System Configuration Register */
+
+/* 16550 MIMIC Registers */
+
+#  define Z182_MIMIC_FCR   0xe9 /* FIFO Control Register */
+#  define Z182_MIMIC_MM    0xe9 /* MM register */
+#  define Z182_MIMIC_RTTC  0xea /* Receive Timeout Time Constant */
+#  define Z182_MIMIC_TTTC  0xeb /* Transmit Timeout Time Constant */
+#  define Z182_MIMIC_FSCR  0xec /* FIFO Status and Control */
+#  define Z182_MIMIC_RBR   0xf0 /* Receive Buffer Register */
+#  define Z182_MIMIC_THR   0xf0 /* Transmit Holding Register */
+#  define Z182_MIMIC_IER   0xf1 /* Interrupt Enable Register */
+#  define Z182_MIMIC_LCR   0xf3 /* Line Control Register */
+#  define Z182_MIMIC_MCR   0xf4 /* Modem Control Register */
+#  define Z182_MIMIC_LSR   0xf5 /* Line Status Register */
+#  define Z182_MIMIC_MSR   0xf6 /* Modem Status Register */
+#  define Z182_MIMIC_SCR   0xf7 /* Scratch Register */
+#  define Z182_MIMIC_DLL   0xf8 /* Divisor Latch (LSByte) */
+#  define Z182_MIMIC_DLM   0xf9 /* Divisor Latch (MSByte) */
+#  define Z182_MIMIC_TTCR  0xfa /* Transmit Time Constant */
+#  define Z182_MIMIC_RTCR  0xfb /* Receive Time Constant */
+#  define Z182_MIMIC_IVEC  0xfc /* Interrupt Vector */
+#  define Z182_MIMIC_IE    0xfd /* Interrupt Enable */
+
+#  define Z182_MIMIC_IUSIP 0xfe /* Interrupt Under-Service/Interrupt Pending */
+#  define Z182_MIMIC_MMC   0xff /* MIMIC Master Control Register  */
+
+/* Some of the MIMIC registers are accessible to memory-mapped addresses */
+
+#  define Z182_MIMIC_RBR_ADDR 0x0000 /* Receive Buffer Register */
+#  define Z182_MIMIC_DLL_ADDR 0x0000 /* Divisor Latch (LSByte) */
+#  define Z182_MIMIC_THR_ADDR 0x0000 /* Transmit Holding Register */
+#  define Z182_MIMIC_DLM_ADDR 0x0001 /* Divisor Latch (MSByte) */
+#  define Z182_MIMIC_IER_ADDR 0x0001 /* Interrupt Enable Register */
+#  define Z182_MIMIC_IIR_ADDR 0x0002 /* Interrupt Identification */
+#  define Z182_MIMIC_FCR_ADDR 0x0002 /* FIFO Control Register */
+#  define Z182_MIMIC_LCR_ADDR 0x0003 /* Line Control Register */
+#  define Z182_MIMIC_MCR_ADDR 0x0004 /* Modem Control Register */
+#  define Z182_MIMIC_LSR_ADDR 0x0005 /* Line Status Register */
+#  define Z182_MIMIC_MSR_ADDR 0x0006 /* Modem Status Register */
+#  define Z182_MIMIC_SCR_ADDR 0x0007 /* Scratch Register */
+#endif
+
+/* [E]SCC Internal Register Definitions */
+
+#define Z18X_SCC_RR0       0x00
+#define Z18X_SCC_RR1       0x01
+#define Z18X_SCC_RR2       0x02
+#define Z18X_SCC_RR3       0x03
+#define Z18X_SCC_RR6       0x06
+#define Z18X_SCC_RR7       0x07
+#define Z18X_SCC_RR10      0x0a
+#define Z18X_SCC_RR12      0x0c
+#define Z18X_SCC_RR13      0x0d
+#define Z18X_SCC_RR15      0x0f
+
+#define Z18X_SCC_WR0       0x00
+#define Z18X_SCC_WR1       0x01
+#define Z18X_SCC_WR2       0x02
+#define Z18X_SCC_WR3       0x03
+#define Z18X_SCC_WR4       0x04
+#define Z18X_SCC_WR5       0x05
+#define Z18X_SCC_WR6       0x06
+#define Z18X_SCC_WR7       0x07
+#define Z18X_SCC_WR9       0x09
+#define Z18X_SCC_WR10      0x0a
+#define Z18X_SCC_WR11      0x0b
+#define Z18X_SCC_WR12      0x0c
+#define Z18X_SCC_WR13      0x0d
+#define Z18X_SCC_WR14      0x0e
+#define Z18X_SCC_WR15      0x0f
+
+/* Z180 Register Bit definitions ****************************************************/
+/* ASCI Registers *******************************************************************/
 /* ASCI Control Register A 0 (CNTLA0: 0x00) */
 /* ASCI Control Register A 1 (CNTLA1: 0x01) */
 
@@ -179,6 +338,26 @@
 /* ASCI Receive Data Register Ch. 0 (RDR0: 0x08) - 8-bit data */
 /* ASCI Receive Data Register Ch. 1 (RDR0: 0x09) - 8-bit data */
 
+/* ASCI0 Extension Control Register (I/O Address: 0x12) (Z8S180/L180-Class Processors Only) */
+/* ASCI1 Extension Control Register (I/O Address: 0x13) (Z8S180/L180-Class Processors Only) */
+
+#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
+#  define ASCI_ASEXT_RDRF    (0x80) /* Bit 7: RDRF Interrupt Inhibit */
+#  define ASCI0_ASEXT_DCD0   (0x80) /* Bit 6: DCD0 advisory to SW (ASCI0 only) */
+#  define ASCI0_ASEXT_CTS0   (0x80) /* Bit 5: CTS0 advisory to SW (ASCI0 only) */
+#  define ASCI_ASEXT_X1BC    (0x80) /* Bit 4: CKA0 is bit clock */
+#  define ASCI_ASEXT_BRG     (0x80) /* Bit 3: Enable 16-bit BRG counter */
+#  define ASCI_ASEXT_BRKEN   (0x80) /* Bit 2: Break Feature Enable */
+#  define ASCI_ASEXT_BRKDET  (0x80) /* Bit 1: Break Detect */
+#  define ASCI_ASEXT_SNDBRK  (0x80) /* Bit 0: Send Break */
+#endif
+
+/* ASCI0 Time Constant Low Register (I/O Address: 0x1a) (Z8S180/L180-Class Processors Only) -- 8-bit data */
+/* ASCI0 Time Constant High Register (I/O Address: 0x1b) (Z8S180/L180-Class Processors Only) -- 8-bit data */
+/* ASCI1 Time Constant Low Register (I/O Address: 0x1c) (Z8S180/L180-Class Processors Only) -- 8-bit data */
+/* ASCI1 Time Constant High Register (I/O Address: 0x1d) (Z8S180/L180-Class Processors Only) -- 8-bit data */
+
+/* CSI/O Registers ******************************************************************/
 /* CSI/O Control/Status Register (CNTR: 0x0a) */
 
 #define CSIO_CNTR_EF         (0x80) /* Bit 7: End Flag */
@@ -196,8 +375,9 @@
 #  define CSIO_CNTR_DIV1280  (6 << CSIO_CNTR_SS_SHIFT) /* Divide Ratio: 1280 Baud: 3125 */
 #  define CSIO_CNTR_EXT      (7 << CSIO_CNTR_SS_SHIFT) /* External Clock input (less than 20) */
                                                        /* Baud at Phi = 4 MHz */
-
 /* CSI/O Transmit/Receive Register (TRDR: 0x0b) -- 8-bit data */
+
+/* Timer Registers ******************************************************************/
 /* Timer Data Register 0L (TMDR0L: 0x0c) -- 8-bit data */
 /* Timer Data Register 0H (TMDR0H: 0x0d) -- 8-bit data */
 /* Timer Reload Register Channel 0L (RLDR0L: 0x0e) -- 8-bit data */
@@ -214,55 +394,15 @@
 #define TMR_TCR_TDE1         (0x02) /* Bit 1: Timer 1 Down Count Enable */
 #define TMR_TCR_TDE0         (0x01) /* Bit 0: Timer 0 Down Count Enable */
 
-/* ASCI0 Extension Control Register (I/O Address: 0x12) (Z8S180/L180-Class Processors Only) */
-/* ASCI1 Extension Control Register (I/O Address: 0x13) (Z8S180/L180-Class Processors Only) */
-
-#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
-#  define ASCI_ASEXT_RDRF    (0x80) /* Bit 7: RDRF Interrupt Inhibit */
-#  define ASCI0_ASEXT_DCD0   (0x80) /* Bit 6: DCD0 advisory to SW (ASCI0 only) */
-#  define ASCI0_ASEXT_CTS0   (0x80) /* Bit 5: CTS0 advisory to SW (ASCI0 only) */
-#  define ASCI_ASEXT_X1BC    (0x80) /* Bit 4: CKA0 is bit clock */
-#  define ASCI_ASEXT_BRG     (0x80) /* Bit 3: Enable 16-bit BRG counter */
-#  define ASCI_ASEXT_BRKEN   (0x80) /* Bit 2: Break Feature Enable */
-#  define ASCI_ASEXT_BRKDET  (0x80) /* Bit 1: Break Detect */
-#  define ASCI_ASEXT_SNDBRK  (0x80) /* Bit 0: Send Break */
-#endif
-
 /* Timer Data Register 1L (TMDR1L: 0x14) -- 8-bit data */
 /* Timer Data Register 1H (TMDR1H: 0x15) -- 8-bit data */
 /* Timer Reload Register Channel 1L (RLDR1L: 0x16) -- 8-bit data */
 /* Timer Reload Register Channel 1H (RLDR1H: 0x17) -- 8-bit data */
 /* Free Running counter (FRC: 0x18) -- 8-bit data */
 
-/* ASCI0 Time Constant Low Register (I/O Address: 0x1a) (Z8S180/L180-Class Processors Only) -- 8-bit data */
+/* DMA Registers ********************************************************************/
-/* ASCI0 Time Constant High Register (I/O Address: 0x1b) (Z8S180/L180-Class Processors Only) -- 8-bit data */
-/* ASCI1 Time Constant Low Register (I/O Address: 0x1c) (Z8S180/L180-Class Processors Only) -- 8-bit data */
-/* ASCI1 Time Constant High Register (I/O Address: 0x1d) (Z8S180/L180-Class Processors Only) -- 8-bit data */
-
-/* Clock Multiplier Register (CMR: 0x1e) (Z8S180/L180-Class Processors Only) */
-
-#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
-#  define CMR_CMM            (0x80) /* Bit 7: X2 Clock Multiplier Mode */
-#endif
-
-/* CPU Control Register (CCR: 0x1f) (Z8S180/L180-Class Processors Only) */
-
-#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
-#  define CCR_XTAL_DIV       (0x80) /* Bit 7: Clock Divide */
-#  define CCR_STBYIDLE       (0x48) /* Bits 3 & 6: STANDBY/IDLE mode */
-#    define CCR_NOSTDBY      (0x00) /* No STANDBY */
-#    define CCR_IDLE         (0x08) /* IDLE after SLEEP */
-#    define CCR_STBY         (0x40) /* STANDBY after SLEEP */
-#    define CCR_STBY64       (0x48) /* STANDBY after SLEEP 64 Cycle Exit */
-#  define CCR_BREXT          (0x20) /* Bit 5: STANDBY/IDLE exit on BUSREQ */
-#  define CCR_LNPHI          (0x10) /* Bit 4: 33% Drive on EXTPHI Clock */
-#  define CCR_LNIO           (0x04) /* Bit 2: 33% Drive on certain external I/O */
-#  define CCR_LNCPUCTLR      (0x02) /* Bit 1: 33% Drive on CPU control signals */
-#  define LNADDATA           (0x01) /* Bit 0: 33% drive on A10–A0, D7–D0 */
-#endif
-
 /* DMA Destination Address Register Channel 0 (DAR0 I/O Address 0x23 to 0x25) -- 8-bit data */
-/*DMA Byte Count Register Channel 0 (BCR0 I/O Address = 0x26 to 0x27) -- 8-bit data */
+/* DMA Byte Count Register Channel 0 (BCR0 I/O Address = 0x26 to 0x27) -- 8-bit data */
 /* DMA Memory Address Register Channel 1 (MAR1: I/O Address = 0x28 to 0x2a) -- 8-bit data */
 /* DMA I/O Address Register Channel 1 (IAR1: I/O Address = 0x2b to 0x2c) -- 8-bit data */
 
@@ -327,6 +467,29 @@
 #  define DCNTL_DIM_IO2MI    (2 << DCNTL_DIM_SHIFT) /* I/O to memory, increment MARI */
 #  define DCNTL_DIM_IO2MD    (3 << DCNTL_DIM_SHIFT) /* I/O to memory, decrement MARI */
 
+/* System Control Registers *********************************************************/
+/* Clock Multiplier Register (CMR: 0x1e) (Z8S180/L180-Class Processors Only) */
+
+#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
+#  define CMR_CMM            (0x80) /* Bit 7: X2 Clock Multiplier Mode */
+#endif
+
+/* CPU Control Register (CCR: 0x1f) (Z8S180/L180-Class Processors Only) */
+
+#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
+#  define CCR_XTAL_DIV       (0x80) /* Bit 7: Clock Divide */
+#  define CCR_STBYIDLE       (0x48) /* Bits 3 & 6: STANDBY/IDLE mode */
+#    define CCR_NOSTDBY      (0x00) /* No STANDBY */
+#    define CCR_IDLE         (0x08) /* IDLE after SLEEP */
+#    define CCR_STBY         (0x40) /* STANDBY after SLEEP */
+#    define CCR_STBY64       (0x48) /* STANDBY after SLEEP 64 Cycle Exit */
+#  define CCR_BREXT          (0x20) /* Bit 5: STANDBY/IDLE exit on BUSREQ */
+#  define CCR_LNPHI          (0x10) /* Bit 4: 33% Drive on EXTPHI Clock */
+#  define CCR_LNIO           (0x04) /* Bit 2: 33% Drive on certain external I/O */
+#  define CCR_LNCPUCTLR      (0x02) /* Bit 1: 33% Drive on CPU control signals */
+#  define LNADDATA           (0x01) /* Bit 0: 33% drive on A10-A0, D7-D0 */
+#endif
+
 /* Interrupt Vector Low Register (IL: 0x33) */
 
 #define IL_SHIFT             (5)   /* Bits 5-7: 3-bits of vector interrupt table address */
@@ -375,4 +538,34 @@
 #  define ICR_IOA7           (2 << ICR_IOA_SHIFT)
 #define ICR_IOSTP            (0x20) /* Bit 5: Enable I/O stop mode */
 
+/* Registers unique to Z8x181 class CPUs ********************************************/
+
+#ifdef HAVE_Z8X181
+/* To be provided */
+
+/* PIA Registers */
+
+/* CTC Registers */
+
+/* SCC Registers */
+
+/* System Control Registers */
+
+#endif
+
+/* Registers unique to Z8x182 class CPUs ********************************************/
+
+#ifdef HAVE_Z8X182
+/* To be provided */
+
+/* PIA Registers */
+
+/* ESCC Registers */
+
+/* System Control Registers */
+
+/* 16550 MIMIC Registers */
+
+#endif
+
 #endif /* __ARCH_Z80_SRC_Z180_Z180_IOMAP_H */

configs/p112/README.txt

@@ -1,5 +1,5 @@
 P112 README
-^^^^^^^^^^^
+===========
 
 The P112 is notable because it was the first of the hobbyist single board
 computers to reach the production stage. The P112 hobbyist computers
@@ -24,3 +24,108 @@ Gulczynski makes additional P112 derivative hobbyist home brew computers.
 Hal Bower was very active in the mid 1990's on the P112 project and ported
 the "Banked/Portable BIOS".
 
+Pin Configuration
+=================
+
+The P112 is based on the 5V Z8018216FSG running at 16MHz.  The Z8018216FSG
+comes in a 100-pin QFP package:
+
+PIN  NAME
+  1  /INT0                      INT0, pulled up, J1 DIN48 pin 13C
+  2  /INT1/PC6                  FINTR, Floppy disk controller
+  3  /INT2/PC7                  PINTR1, Floppy disk controller
+  4  ST                         ST, to AEN of Floppy disk controller
+  5  A0                         A0-A12 Common memory bus
+  ...
+ 17  A12                        "               "
+ 18  VSS                        ---
+ 19  A13                        A13-A17 Common memory bus
+  ...
+ 23  A17                        "               "
+ 24  A18/TOUT                   A18 Common memory bus
+ 25  VDD                        ---
+ 26  A19                        A19 Common memory bus
+ 27  D0                         D0-D4 Common memory bus
+ ...
+ 30  D3                         "              "
+
+ 31  D4                         D4-D7 Common memory bus
+ ...
+ 34  D7                         "              "
+ 35  /RTS0/PB0                  RTS0, 20-pin P14, pin 3
+ 36  /CTS0/PB1                  CTS0, pulled high (U16), 20-pin P14, pin 4
+ 37  /DCD0/PB2                  DCD0, pulled high (U16), 20-pin P14, pin 10
+ 38  TXA0/PB3                   TXA0, 20-pin P14, pin 8
+ 39  RXA0/PB4                   RXA0, pulled high (U17), 20-pin P14, pin 2
+ 40  TXA1/PB5                   TXA1, 20-pin P14, pin 1
+ 41  RXA1/PB6                   RXA1, pulled high (U17), 20-pin P14, pin 9
+ 42  RXS//CTS1/PB7              CTS1, pulled high (U17), 20-pin P14, pin 7
+ 43  CKA0//DREQ0                /DREQ0, DMA Request Select, 5-pin P2, pin 2
+ 44  VSS                        ---
+ 45  CKA1//TEND0                /TEND0, J1 DIN48 pin 14A
+ 46  TXS//DTR//REQB//HINTR      DTRB, 20-pin P14, pin 6
+ 47  CKS//W//REQB//HTXRDY       SIORQ, DMA Request Select, 5-pin P2, pin 5 (may be DREQ 0 or DREQ1)
+ 48  /DREQ1                     /DREQ1, DMA Request Select, 5-pin P2, pin 4
+ 49  VDD                        ---
+ 50  /TEND1//RTSB//HRXRDY       NB /TEND1 = RTSB, 20-pin P14, pin 5; J1 DIN48 pin 14B
+
+ 51  /RAMCS                     /RAMCS, Chip select logic (U11B); also J1 DIN48 pin 9B
+ 52  /ROMCS                     /ROMCS, Chip select logic (P2); also J1 DIN48 pin 12B
+ 53  EV1                        Grounded
+ 54  EV2                        Grounded
+ 55  PA0/HD0                    IO, U6 DS1202 Serial Timekeeping chip
+ 56  PA1/HD1                    CLK, U6 DS1202 Serial Timekeeping chip
+ 57  PA2/HD2                    /RST, U6 DS1202 Serial Timekeeping chip
+ 58  PA3/HD3                    N/C
+ 59  PA4/HD4                    N/C
+ 60  PA5/HD5                    U12 NMF0512S, Isolated 1W regulated single output DC/DC converter
+ 61  PA6/HD6                    DSR, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
+ 62  PA7/HD7                    RTS, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
+ 63  /W//REQA/PC5               WREQA, N/C
+ 64  /DTR//REQA/PC3             DTRA, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
+ 65  /MWR/PC2//RTSA             /MWR, Common memory bus signal
+ 66  /CTSA/PC1                  CTSA, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
+ 67  /DCDA/PC0                  DCDA, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
+ 68  /SYNCA/PC4                 SYNCA, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
+ 69  /RTXCA                     ?
+ 70  VSS                        ---
+ 71  /IOCS/IEO                  /IOCS, Logic circuit with M1, generates LIVE which conditions inputs
+                                to the floppy disk controller
+ 72  IEI                        IEI, J1 DIN48 pin 14C
+ 73  VDD                        ---
+ 74  RXDA                       RXDA, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
+ 75  /TRXCA                     ?
+ 76  TXDA                       TXDA, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
+ 77  /DCDB//HRD                 DCDB, pulled high (U16), 20-pin P14, pin 12
+ 78  /CTSB//HWR                 DCDB, pulled high (U17), 20-pin P14, pin 11
+ 79  TXDB//HDDIS                TXDB, 20-pin P14, pin 14
+ 80  /TRXCB/HA0                 TRXCB, pulled high (U17), 20-pin P14, pin 15
+
+ 81  RXDB/HA1                   RXDB, pulled high (U16), 20-pin P14, pin 16
+ 82  /RTXCB/HA2                 RTXCB, pulled high (U17), 20-pin P14, pin 17
+ 83  /SYNCB//HCS                SYNCB, pulled high (U16), 20-pin P14, pin 18
+ 84  /HALT                      ?
+ 85  /RFSH                      ?
+ 86  /IORQ                      /IORQ, J1 DIN48 pin 12A
+ 87  /MRD//MREQ                 /MRD, Common memory bus signal
+ 88  E                          E, Conditions inputs to floppy disk controller; also J1 DIN48 pin 13B
+ 89  /M1                        /M1, Logic circuit with /IOCS, generates LIVE which conditions inputs
+                                to the floppy disk controller; also J1 DIN48 pin 11A
+ 90  /WR                        /WR, Common memory bus; Conditions inputs to floppy disk controller;
+                                also J1 DIN48 pin 12C
+ 91  /RD                        /RD, J1 DIN48 pin 11C
+ 92  PHI                        PHI, J1 DIN48 pin 15B
+ 93  VSS                        ---
+ 94  XTAL                       16 MHz XTAL
+ 95  EXTAL                      16 MHz XTAL
+ 96  /WAIT                      /WAIT, J1 DIN48 pin 11B
+ 97  /BUSACK                    ?
+ 98  /BUSREQ                    /BUSREQ, Pulled high
+ 99  /RESET                     /RST (to lots of places)
+100  /NMI                       /NMI, Pulled high
+
+P112 Serial Console
+===================
+
+The serial console is proved by U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
+that connects to the P112 via the Z85230 ESCC channel A.

configs/xtrs/src/xtr_irq.c

@@ -71,7 +71,7 @@
 
 void up_irqinitialize(void)
 {
-  /* Attach the timer interrupt -- There is not special timer interrupt
+  /* Attach the timer interrupt -- There is no special timer interrupt
    * enable in the simulation so it must be enabled here before interrupts
    * are enabled.
    *
@@ -97,10 +97,12 @@ void up_irqinitialize(void)
  *
  ****************************************************************************/
 
+#ifndef CONFIG_ARCH_NOINTC
 void up_disable_irq(int irq)
 {
   irqrestore(0);
 }
+#endif
 
 /****************************************************************************
  * Name: up_enable_irq
@@ -110,7 +112,9 @@ void up_disable_irq(int irq)
  *
  ****************************************************************************/
 
+#ifndef CONFIG_ARCH_NOINTC
 void up_enable_irq(int irq)
 {
- irqrestore(true);
+ irqrestore(Z80_C_FLAG);
 }
+#endif

configs/z80sim/src/z80_irq.c

@@ -97,10 +97,12 @@ void up_irqinitialize(void)
  *
  ****************************************************************************/
 
+#ifndef CONFIG_ARCH_NOINTC
 void up_disable_irq(int irq)
 {
   irqrestore(0);
 }
+#endif
 
 /****************************************************************************
  * Name: up_enable_irq
@@ -110,7 +112,9 @@ void up_disable_irq(int irq)
  *
  ****************************************************************************/
 
+#ifndef CONFIG_ARCH_NOINTC
 void up_enable_irq(int irq)
 {
- irqrestore(true);
+ irqrestore(Z80_C_FLAG);
 }
+#endif