diff --git a/Documentation/platforms/risc-v/bl808/boards/ox64/index.rst b/Documentation/platforms/risc-v/bl808/boards/ox64/index.rst
index 70e5fa48f3f..799a5304432 100644
--- a/Documentation/platforms/risc-v/bl808/boards/ox64/index.rst
+++ b/Documentation/platforms/risc-v/bl808/boards/ox64/index.rst
@@ -154,5 +154,6 @@ Serial Console is enabled on UART3 at 2 Mbps.
 timer
 -----
 
-This configuration enables support for hardware timers and the timer example app.
+This configuration enables support for general purpose and watchdog timers,
+as well as the timer and watchdog examples.
 Serial Console is enabled on UART3 at 2 Mbps.
diff --git a/Documentation/platforms/risc-v/bl808/index.rst b/Documentation/platforms/risc-v/bl808/index.rst
index c7c68bdbcf1..dfb9b3c981e 100644
--- a/Documentation/platforms/risc-v/bl808/index.rst
+++ b/Documentation/platforms/risc-v/bl808/index.rst
@@ -55,6 +55,7 @@ SPI          Yes
 Timers       Yes
 UART         Yes
 USB          No
+Watchdogs    Yes
 =========== ======= ====================
 
 Supported Boards
diff --git a/arch/risc-v/include/bl808/irq.h b/arch/risc-v/include/bl808/irq.h
index 752832bfcd1..a368a511981 100644
--- a/arch/risc-v/include/bl808/irq.h
+++ b/arch/risc-v/include/bl808/irq.h
@@ -56,6 +56,7 @@
 #define BL808_IRQ_D0_IPC (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 38)
 #define BL808_IRQ_TIMER1_CH0 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 61)
 #define BL808_IRQ_TIMER1_CH1 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 62)
+#define BL808_IRQ_WDT1 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 63)
 #define BL808_IRQ_M0IC (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 65)
 
 /* M0 IRQs ******************************************************************/
@@ -67,5 +68,6 @@
 #define BL808_IRQ_UART2 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 30)
 #define BL808_IRQ_TIMER0_CH0 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 36)
 #define BL808_IRQ_TIMER0_CH1 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 37)
+#define BL808_IRQ_WDT0 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 38)
 
 #endif /* __ARCH_RISCV_INCLUDE_BL808_IRQ_H */
diff --git a/arch/risc-v/src/bl808/Kconfig b/arch/risc-v/src/bl808/Kconfig
index d534dedfc06..d23cb0e060a 100644
--- a/arch/risc-v/src/bl808/Kconfig
+++ b/arch/risc-v/src/bl808/Kconfig
@@ -229,4 +229,9 @@ config BL808_TIMERS
 	default n
 	select TIMER
 
+config BL808_WDT
+	bool "Watchdog Timers"
+	default n
+	select WATCHDOG
+
 endmenu
diff --git a/arch/risc-v/src/bl808/Make.defs b/arch/risc-v/src/bl808/Make.defs
index 308c0e76038..9fa806413de 100644
--- a/arch/risc-v/src/bl808/Make.defs
+++ b/arch/risc-v/src/bl808/Make.defs
@@ -28,4 +28,4 @@ HEAD_ASRC = bl808_head.S
 CHIP_CSRCS  = bl808_start.c bl808_irq_dispatch.c bl808_irq.c
 CHIP_CSRCS += bl808_timerisr.c bl808_allocateheap.c
 CHIP_CSRCS += bl808_gpio.c bl808_mm_init.c bl808_pgalloc.c bl808_serial.c
-CHIP_CSRCS += bl808_gpadc.c bl808_spi.c bl808_timer.c
+CHIP_CSRCS += bl808_gpadc.c bl808_spi.c bl808_timer.c bl808_wdt.c
diff --git a/arch/risc-v/src/bl808/bl808_timer.c b/arch/risc-v/src/bl808/bl808_timer.c
index 9a666a456fd..4f1bc84925c 100644
--- a/arch/risc-v/src/bl808/bl808_timer.c
+++ b/arch/risc-v/src/bl808/bl808_timer.c
@@ -28,15 +28,12 @@
 #include <sys/types.h>
 #include <stdint.h>
 #include <stdbool.h>
-#include <unistd.h>
-#include <string.h>
 #include <errno.h>
 #include <debug.h>
 
 #include <nuttx/irq.h>
 #include <nuttx/timers/timer.h>
 #include <nuttx/fs/ioctl.h>
-#include <nuttx/serial/tioctl.h>
 
 #include "hardware/bl808_timer.h"
 #include "riscv_internal.h"
diff --git a/arch/risc-v/src/bl808/bl808_wdt.c b/arch/risc-v/src/bl808/bl808_wdt.c
new file mode 100644
index 00000000000..7f92666439f
--- /dev/null
+++ b/arch/risc-v/src/bl808/bl808_wdt.c
@@ -0,0 +1,383 @@
+/****************************************************************************
+ * arch/risc-v/src/bl808/bl808_wdt.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/timers/watchdog.h>
+#include <nuttx/fs/ioctl.h>
+
+#include "hardware/bl808_timer.h"
+#include "riscv_internal.h"
+#include "chip.h"
+#include "bl808_wdt.h"
+
+#ifdef CONFIG_BL808_WDT
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define WDT_CLK_SRC_1K 2
+#define WDT_CLK_SRC_NONE 5
+
+#define BL808_UNLOCK_WDT(n) \
+  ({ \
+    putreg32(0xbaba, BL808_WDT_KEY1(n)); \
+    putreg32(0xeb10, BL808_WDT_KEY2(n)); \
+  })
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct bl808_wdt_s
+{
+  const struct watchdog_ops_s *ops;
+  int idx;
+  xcpt_t callback;
+  bool started;
+  uint32_t timeout;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+int bl808_wdt_start(FAR struct watchdog_lowerhalf_s *lower);
+int bl808_wdt_stop(FAR struct watchdog_lowerhalf_s *lower);
+int bl808_wdt_keepalive(FAR struct watchdog_lowerhalf_s *lower);
+int bl808_wdt_getstatus(FAR struct watchdog_lowerhalf_s *lower,
+                          FAR struct watchdog_status_s *status);
+int bl808_wdt_settimeout(FAR struct watchdog_lowerhalf_s *lower,
+                           uint32_t timeout);
+xcpt_t bl808_wdt_capture(FAR struct watchdog_lowerhalf_s *lower,
+                       CODE xcpt_t callback);
+int bl808_wdt_ioctl(FAR struct watchdog_lowerhalf_s *lower,
+                      int cmd, unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static struct watchdog_ops_s bl808_wdt_ops =
+  {
+    .start = bl808_wdt_start,
+    .stop = bl808_wdt_stop,
+    .keepalive = bl808_wdt_keepalive,
+    .getstatus = bl808_wdt_getstatus,
+    .settimeout = bl808_wdt_settimeout,
+    .capture = bl808_wdt_capture,
+    .ioctl = bl808_wdt_ioctl,
+  };
+
+static struct bl808_wdt_s wdt0 =
+  {
+    .ops = &bl808_wdt_ops,
+    .idx = 0,
+    .callback = NULL,
+    .started = false,
+    .timeout = 0
+  };
+
+static struct bl808_wdt_s wdt1 =
+  {
+    .ops = &bl808_wdt_ops,
+    .idx = 1,
+    .callback = NULL,
+    .started = false,
+    .timeout = 0
+  };
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: wdt_interrupt
+ *
+ * Description:
+ *   Watchdog interrupt handler. Clears the interrupt and
+ *   Calls the attached callback if there is one.
+ *
+ ****************************************************************************/
+
+static int __wdt_interrupt(int irq, void *context, void *arg)
+{
+  struct bl808_wdt_s *priv = (struct bl808_wdt_s *)arg;
+
+  /* Clear IRQ */
+
+  BL808_UNLOCK_WDT(priv->idx);
+  modifyreg32(BL808_WDT_ICLR(priv->idx), 0, WDT_CLEAR_IRQ);
+
+  if (priv->callback != NULL)
+    {
+      priv->callback(irq, context, arg);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: bl808_wdt_start
+ *
+ * Description:
+ *   Reset the time to the current timeout and start the watchdog.
+ *
+ ****************************************************************************/
+
+int bl808_wdt_start(FAR struct watchdog_lowerhalf_s *lower)
+{
+  struct bl808_wdt_s *priv = (struct bl808_wdt_s *)lower;
+
+  /* Enable clock */
+
+  modifyreg32(BL808_TIMER_TCCR(priv->idx), WDT_CLKSEL_MASK,
+              WDT_CLK_SRC_1K << WDT_CLKSEL_SHIFT);
+
+  /* Clear counter */
+
+  BL808_UNLOCK_WDT(priv->idx);
+  modifyreg32(BL808_WDT_COUNT_CLEAR(priv->idx), 0, WDT_CLEAR_COUNT);
+  while (getreg32(BL808_WDT_COUNTER(priv->idx)) != 0);
+  BL808_UNLOCK_WDT(priv->idx);
+  modifyreg32(BL808_WDT_COUNT_CLEAR(priv->idx), WDT_CLEAR_COUNT, 0);
+
+  priv->started = true;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: bl808_timer_stop
+ *
+ * Description:
+ *   Stop the watchdog.
+ *
+ ****************************************************************************/
+
+int bl808_wdt_stop(FAR struct watchdog_lowerhalf_s *lower)
+{
+  struct bl808_wdt_s *priv = (struct bl808_wdt_s *)lower;
+
+  /* WDTs are stopped by setting the input clock to NONE.
+   * This is done to allow calling watchdog_stop and then get
+   * the time left to timeout afterwards. If we used the
+   * watchdog enable bits, the counter would reset to 0 when stopped.
+   */
+
+  modifyreg32(BL808_TIMER_TCCR(priv->idx), WDT_CLKSEL_MASK,
+              WDT_CLK_SRC_NONE << WDT_CLKSEL_SHIFT);
+
+  priv->started = false;
+  return OK;
+}
+
+int bl808_wdt_keepalive(FAR struct watchdog_lowerhalf_s *lower)
+{
+  struct bl808_wdt_s *priv = (struct bl808_wdt_s *)lower;
+
+  /* Check that the watchdog is running */
+
+  if (priv->started == false)
+    {
+      return -EIO;
+    }
+
+  BL808_UNLOCK_WDT(priv->idx);
+  modifyreg32(BL808_WDT_COUNT_CLEAR(priv->idx), 0, WDT_CLEAR_COUNT);
+  while (getreg32(BL808_WDT_COUNTER(priv->idx)) != 0);
+  BL808_UNLOCK_WDT(priv->idx);
+  modifyreg32(BL808_WDT_COUNT_CLEAR(priv->idx), WDT_CLEAR_COUNT, 0);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: bl808_wdt_getstatus
+ *
+ * Description:
+ *   Get current watchdog status. Returns to status parameter.
+ *
+ ****************************************************************************/
+
+int bl808_wdt_getstatus(FAR struct watchdog_lowerhalf_s *lower,
+                          FAR struct watchdog_status_s *status)
+{
+  struct bl808_wdt_s *priv = (struct bl808_wdt_s *)lower;
+
+  status->flags = priv->started
+    | ((priv->callback == NULL) << 1)
+    | ((priv->callback != NULL) << 2);
+
+  status->timeout = priv->timeout;
+
+  uint32_t current_count = getreg32(BL808_WDT_COUNTER(priv->idx));
+  status->timeleft = priv->timeout - current_count;
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: bl808_wdt_settimeout
+ *
+ * Description:
+ *   Set a new timeout value and reset the watchdog.
+ *
+ ****************************************************************************/
+
+int bl808_wdt_settimeout(FAR struct watchdog_lowerhalf_s *lower,
+                           uint32_t timeout)
+{
+  struct bl808_wdt_s *priv = (struct bl808_wdt_s *)lower;
+
+  BL808_UNLOCK_WDT(priv->idx);
+  modifyreg32(BL808_WDT_COMP(priv->idx), 0xffff, timeout);
+  priv->timeout = timeout;
+
+  /* Clock is needed to clear counter (assuming same behavior as GP timers) */
+
+  modifyreg32(BL808_TIMER_TCCR(priv->idx), WDT_CLKSEL_MASK,
+              WDT_CLK_SRC_1K << WDT_CLKSEL_SHIFT);
+
+  BL808_UNLOCK_WDT(priv->idx);
+  modifyreg32(BL808_WDT_COUNT_CLEAR(priv->idx), 0, WDT_CLEAR_COUNT);
+  while (getreg32(BL808_WDT_COUNTER(priv->idx)) != 0);
+
+  /* Disable clock to stop timer from running after clear */
+
+  modifyreg32(BL808_TIMER_TCCR(priv->idx), WDT_CLKSEL_MASK,
+              WDT_CLK_SRC_NONE << WDT_CLKSEL_SHIFT);
+
+  BL808_UNLOCK_WDT(priv->idx);
+  modifyreg32(BL808_WDT_COUNT_CLEAR(priv->idx), WDT_CLEAR_COUNT, 0);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: bl808_wdt_capture
+ *
+ * Description:
+ *   Assigns a callback to be called on timeout. If
+ *   the callback is null, configure the watchdog
+ *   as a reset source.
+ *
+ ****************************************************************************/
+
+xcpt_t bl808_wdt_capture(FAR struct watchdog_lowerhalf_s *lower,
+                         CODE xcpt_t callback)
+{
+  struct bl808_wdt_s *priv = (struct bl808_wdt_s *)lower;
+  priv->callback = callback;
+
+  /* Configure watchdog mode */
+
+  if (callback == NULL)
+    {
+      BL808_UNLOCK_WDT(priv->idx);
+      modifyreg32(BL808_WDT_MODE(priv->idx), 0, WDT_RESET_EN);
+      if (priv->idx == 0)
+        {
+          up_disable_irq(BL808_IRQ_WDT0);
+        }
+      else
+        {
+          up_disable_irq(BL808_IRQ_WDT1);
+        }
+    }
+  else
+    {
+      BL808_UNLOCK_WDT(priv->idx);
+      modifyreg32(BL808_WDT_MODE(priv->idx), WDT_RESET_EN, 0);
+      if (priv->idx == 0)
+        {
+          up_enable_irq(BL808_IRQ_WDT0);
+        }
+      else
+        {
+          up_enable_irq(BL808_IRQ_WDT1);
+        }
+    }
+
+  return NULL;
+}
+
+/****************************************************************************
+ * Name: bl808_wdt_ioctl
+ *
+ * Description:
+ *   Handle ioctl commands not recognized by upper-half.
+ *
+ ****************************************************************************/
+
+int bl808_wdt_ioctl(FAR struct watchdog_lowerhalf_s *lower,
+                      int cmd, unsigned long arg)
+{
+  /* No additional ioctl commands implemented */
+
+  return -EIO;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+int bl808_wdt_init(void)
+{
+  int ret = OK;
+
+  /* Watchdog 0 */
+
+  modifyreg32(BL808_TIMER_TCCR(0), WDT_CLKSEL_MASK,
+              WDT_CLK_SRC_NONE << WDT_CLKSEL_SHIFT);
+  BL808_UNLOCK_WDT(0);
+  modifyreg32(BL808_WDT_MODE(0), 0, WDT_EN | WDT_RESET_EN);
+  ret |= irq_attach(BL808_IRQ_WDT0, __wdt_interrupt,
+                    (void *)&wdt0);
+  watchdog_register("/dev/watchdog0",
+                    (struct watchdog_lowerhalf_s *)&wdt0);
+
+  /* Watchdog 1 */
+
+  modifyreg32(BL808_TIMER_TCCR(1), WDT_CLKSEL_MASK,
+              WDT_CLK_SRC_NONE << WDT_CLKSEL_SHIFT);
+  BL808_UNLOCK_WDT(1);
+  modifyreg32(BL808_WDT_MODE(1), 0, WDT_EN | WDT_RESET_EN);
+  ret |= irq_attach(BL808_IRQ_WDT1, __wdt_interrupt,
+                    (void *)&wdt1);
+  watchdog_register("/dev/watchdog1",
+                    (struct watchdog_lowerhalf_s *)&wdt0);
+
+  return ret;
+}
+
+#endif /* CONFIG_BL808_WDT */
diff --git a/arch/risc-v/src/bl808/bl808_wdt.h b/arch/risc-v/src/bl808/bl808_wdt.h
new file mode 100644
index 00000000000..00084c2337c
--- /dev/null
+++ b/arch/risc-v/src/bl808/bl808_wdt.h
@@ -0,0 +1,39 @@
+/****************************************************************************
+ * arch/risc-v/src/bl808/bl808_wdt.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISC_V_SRC_BL808_BL808_WDT_H
+#define __ARCH_RISC_V_SRC_BL808_BL808_WDT_H
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: bl808_wdt_init
+ *
+ * Description:
+ *   Initialize timer hardware and register character drivers
+ *   for enabled timer channels.
+ *
+ ****************************************************************************/
+
+int bl808_wdt_init(void);
+
+#endif /* __ARCH_RISC_V_SRC_BL808_BL808_WDT_H */
diff --git a/arch/risc-v/src/bl808/hardware/bl808_timer.h b/arch/risc-v/src/bl808/hardware/bl808_timer.h
index 01f342e9c6f..8d4efdba6ac 100644
--- a/arch/risc-v/src/bl808/hardware/bl808_timer.h
+++ b/arch/risc-v/src/bl808/hardware/bl808_timer.h
@@ -32,7 +32,7 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-#define BL808_TIMER_BASE(n) ((n == 0) ? BL808_TIMER0_BASE \
+#define BL808_TIMER_BASE(n) (((n) == 0) ? BL808_TIMER0_BASE \
                              : BL808_TIMER1_BASE)
 
 /* Register offsets *********************************************************/
@@ -44,10 +44,17 @@
 #define BL808_TIMER_CH1_COUNTER_OFFSET 0x30
 #define BL808_TIMER_CH0_IE_OFFSET      0x44
 #define BL808_TIMER_CH1_IE_OFFSET      0x48
+#define BL808_WDT_MODE_OFFSET          0x64
+#define BL808_WDT_COMP_OFFSET          0x68
+#define BL808_WDT_COUNTER_OFFSET       0x6C
 #define BL808_TIMER_CH0_ICLR_OFFSET    0x78
 #define BL808_TIMER_CH1_ICLR_OFFSET    0x7c
+#define BL808_WDT_ICLR_OFFSET          0x80
 #define BL808_TIMER_EN_CLR_OFFSET      0x84
 #define BL808_TIMER_MODE_OFFSET        0x88
+#define BL808_WDT_COUNT_CLEAR_OFFSET   0x98
+#define BL808_WDT_KEY1_OFFSET          0x9C
+#define BL808_WDT_KEY2_OFFSET          0xA0
 #define BL808_TIMER_DIV_OFFSET         0xBC
 
 /* Register definitions *****************************************************/
@@ -59,10 +66,17 @@
 #define BL808_TIMER_CH1_COUNTER(n) (BL808_TIMER_BASE(n) + BL808_TIMER_CH1_COUNTER_OFFSET)
 #define BL808_TIMER_CH0_IE(n) (BL808_TIMER_BASE(n) + BL808_TIMER_CH0_IE_OFFSET)
 #define BL808_TIMER_CH1_IE(n) (BL808_TIMER_BASE(n) + BL808_TIMER_CH1_IE_OFFSET)
+#define BL808_WDT_MODE(n) (BL808_TIMER_BASE(n) + BL808_WDT_MODE_OFFSET)
+#define BL808_WDT_COMP(n) (BL808_TIMER_BASE(n) + BL808_WDT_COMP_OFFSET)
+#define BL808_WDT_COUNTER(n) (BL808_TIMER_BASE(n) + BL808_WDT_COUNTER_OFFSET)
 #define BL808_TIMER_CH0_ICLR(n) (BL808_TIMER_BASE(n) + BL808_TIMER_CH0_ICLR_OFFSET)
 #define BL808_TIMER_CH1_ICLR(n) (BL808_TIMER_BASE(n) + BL808_TIMER_CH1_ICLR_OFFSET)
+#define BL808_WDT_ICLR(n) (BL808_TIMER_BASE(n) + BL808_WDT_ICLR_OFFSET)
 #define BL808_TIMER_EN_CLR(n) (BL808_TIMER_BASE(n) + BL808_TIMER_EN_CLR_OFFSET)
 #define BL808_TIMER_MODE(n) (BL808_TIMER_BASE(n) + BL808_TIMER_MODE_OFFSET)
+#define BL808_WDT_COUNT_CLEAR(n) (BL808_TIMER_BASE(n) + BL808_WDT_COUNT_CLEAR_OFFSET)
+#define BL808_WDT_KEY1(n) (BL808_TIMER_BASE(n) + BL808_WDT_KEY1_OFFSET)
+#define BL808_WDT_KEY2(n) (BL808_TIMER_BASE(n) + BL808_WDT_KEY2_OFFSET)
 #define BL808_TIMER_DIV(n) (BL808_TIMER_BASE(n) + BL808_TIMER_DIV_OFFSET)
 
 /* Register bit definitions *************************************************/
@@ -73,11 +87,26 @@
 #define TIMER_CH0_CLKSEL_MASK    (0xf << TIMER_CH0_CLKSEL_SHIFT)
 #define TIMER_CH1_CLKSEL_SHIFT   (4)
 #define TIMER_CH1_CLKSEL_MASK    (0xf << TIMER_CH1_CLKSEL_SHIFT)
+#define WDT_CLKSEL_SHIFT         (8)
+#define WDT_CLKSEL_MASK          (0xf << WDT_CLKSEL_SHIFT)
 
 /* TIMER_CH(0/1)_I(E/CLR) */
 
 #define TIMER_COMP0_INT          (1 << 0)
 
+/* WDT_MODE */
+
+#define WDT_EN                   (1 << 0)
+#define WDT_RESET_EN             (1 << 1)
+
+/* WDT_COMP */
+
+#define WDT_COMP_MASK            (0xffff)
+
+/* WDT_ICLR */
+
+#define WDT_CLEAR_IRQ            (1 << 0)
+
 /* TIMER_EN_CLR */
 
 #define TIMER_CH0_EN             (1 << 1)
@@ -90,6 +119,10 @@
 #define TIMER_CH0_MODE           (1 << 1)
 #define TIMER_CH1_MODE           (1 << 2)
 
+/* WDT_COUNT_CLEAR */
+
+#define WDT_CLEAR_COUNT          (1 << 0)
+
 /* TIMER_DIV */
 
 #define TIMER_CH0_DIV_SHIFT      (8)
diff --git a/boards/risc-v/bl808/ox64/configs/timer/defconfig b/boards/risc-v/bl808/ox64/configs/timer/defconfig
index 351387af2ea..456617bcdfb 100644
--- a/boards/risc-v/bl808/ox64/configs/timer/defconfig
+++ b/boards/risc-v/bl808/ox64/configs/timer/defconfig
@@ -36,6 +36,7 @@ CONFIG_BL808_UART0=y
 CONFIG_BL808_UART1=y
 CONFIG_BL808_UART2=y
 CONFIG_BL808_UART3=y
+CONFIG_BL808_WDT=y
 CONFIG_BOARDCTL_ROMDISK=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=1120
@@ -49,6 +50,7 @@ CONFIG_DEV_ZERO=y
 CONFIG_ELF=y
 CONFIG_EXAMPLES_HELLO=m
 CONFIG_EXAMPLES_TIMER=y
+CONFIG_EXAMPLES_WATCHDOG=y
 CONFIG_FS_PROCFS=y
 CONFIG_FS_ROMFS=y
 CONFIG_IDLETHREAD_STACKSIZE=3072
diff --git a/boards/risc-v/bl808/ox64/src/bl808_appinit.c b/boards/risc-v/bl808/ox64/src/bl808_appinit.c
index 7236b5e598b..681219595db 100644
--- a/boards/risc-v/bl808/ox64/src/bl808_appinit.c
+++ b/boards/risc-v/bl808/ox64/src/bl808_appinit.c
@@ -44,6 +44,9 @@
 #ifdef CONFIG_BL808_TIMERS
 #include "bl808_timer.h"
 #endif
+#ifdef CONFIG_BL808_WDT
+#include "bl808_wdt.h"
+#endif
 #include "bl808_gpadc.h"
 
 /****************************************************************************
@@ -188,6 +191,10 @@ void board_late_initialize(void)
   bl808_timer_init();
 #endif
 
+#ifdef CONFIG_BL808_WDT
+  bl808_wdt_init();
+#endif
+
 #ifdef CONFIG_NSH_ARCHINIT
 
   mount(NULL, "/proc", "procfs", 0, NULL);