diff --git a/Kconfig b/Kconfig index 0479955f529..f0dd167c3c1 100644 --- a/Kconfig +++ b/Kconfig @@ -1098,15 +1098,6 @@ config DEBUG_ANALOG_INFO endif # DEBUG_ANALOG -config DEBUG_WIRELESS - bool "Wireless Device Debug Output" - default n - depends on WIRELESS - ---help--- - Enable low level debug SYSLOG output from the wireless subsystem and - device drivers. (disabled by default). Support for this debug option - is architecture-specific and may not be available for some MCUs. - config DEBUG_CAN bool "CAN Debug Features" default n diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h b/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h index 806b22e0502..ef65a7d436b 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h @@ -344,7 +344,7 @@ # define RCC_CFGR3_USART1SW_HSI (0 << RCC_CFGR3_USART1SW_SHIFT) /* HSI clock */ #define RCC_CFGR3_I2C1SW (1 << 4) /* Bit 4: I2C1 clock source selection */ #define RCC_CFGR3_TIM1SW (1 << 8) /* Bit 8: TIM1 clock source selection */ -#define RCC_CFGR3_HRTIM1SW (1 << 9) /* Bit 9: HRTIM clock source selection */ +#define RCC_CFGR3_HRTIM1SW (1 << 12) /* Bit 12: HRTIM clock source selection */ #define RCC_CFGR3_USART2SW_SHIFT (16) /* Bits 16-17: USART2 clock source selection */ #define RCC_CFGR3_USART2SW_MASK (3 << RCC_CFGR3_USART2SW_SHIFT) # define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) /* PCLK */ diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c index 109cf19da36..c553fdd6e22 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/stm32/stm32_hrtim.c @@ -437,10 +437,8 @@ static int stm32_hrtim_ioctl(FAR struct file *filep, int cmd, unsigned long arg) /* HRTIM Register access */ -#ifdef HRTIM_HAVE_CLK_FROM_PLL static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, uint32_t setbits); -#endif static uint32_t hrtim_cmn_getreg(FAR struct stm32_hrtim_s *priv, int offset); static void hrtim_cmn_putreg(FAR struct stm32_hrtim_s *priv, int offset, uint32_t value); @@ -954,13 +952,11 @@ static int stm32_hrtim_ioctl(FAR struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -#ifdef HRTIM_HAVE_CLK_FROM_PLL static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, uint32_t setbits) { putreg32((getreg32(addr) & ~clrbits) | setbits, addr); } -#endif /**************************************************************************** * Name: hrtim_cmn_getreg @@ -2921,12 +2917,6 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv) int ret; uint32_t regval = 0; - /* Configure PLL VCO output as HRTIM clock source */ - -#ifdef HRTIM_HAVE_CLK_FROM_PLL - stm32_modifyreg32(STM32_RCC_CFGR3, 0, RCC_CFGR3_HRTIM1SW); -#endif - /* HRTIM DLL calibration */ ret = hrtim_dll_cal(priv); diff --git a/arch/arm/src/stm32/stm32f33xxx_rcc.c b/arch/arm/src/stm32/stm32f33xxx_rcc.c index 6254294f5e2..76e19858f4b 100644 --- a/arch/arm/src/stm32/stm32f33xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f33xxx_rcc.c @@ -342,129 +342,13 @@ static inline void rcc_enableapb2(void) * Name: stm32_stdclockconfig * * Description: - * Called to change to new clock based on settings in board.h. This - * version is for the Connectivity Line parts. + * Called to change to new clock based on settings in board.h. * * NOTE: This logic would need to be extended if you need to select low- * power clocking modes! ****************************************************************************/ -#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && defined(CONFIG_STM32_CONNECTIVITYLINE) -static void stm32_stdclockconfig(void) -{ - uint32_t regval; - - /* Enable HSE */ - - regval = getreg32(STM32_RCC_CR); - regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */ - regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32_RCC_CR); - - /* Set flash wait states - * Sysclk runs with 72MHz -> 2 waitstates. - * 0WS from 0-24MHz - * 1WS from 24-48MHz - * 2WS from 48-72MHz - */ - - regval = getreg32(STM32_FLASH_ACR); - regval &= ~FLASH_ACR_LATENCY_MASK; - regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE); - putreg32(regval, STM32_FLASH_ACR); - - /* Set up PLL input scaling (with source = PLL2) */ - - regval = getreg32(STM32_RCC_CFGR2); - regval &= ~(RCC_CFGR2_PREDIV2_MASK | RCC_CFGR2_PLL2MUL_MASK | - RCC_CFGR2_PREDIV1SRC_MASK | RCC_CFGR2_PREDIV1_MASK); - regval |= (STM32_PLL_PREDIV2 | STM32_PLL_PLL2MUL | - RCC_CFGR2_PREDIV1SRC_PLL2 | STM32_PLL_PREDIV1); - putreg32(regval, STM32_RCC_CFGR2); - - /* Set the PCLK2 divider */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_PPRE2_MASK | RCC_CFGR_HPRE_MASK); - regval |= STM32_RCC_CFGR_PPRE2; - regval |= RCC_CFGR_HPRE_SYSCLK; - putreg32(regval, STM32_RCC_CFGR); - - /* Set the PCLK1 divider */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32_RCC_CFGR_PPRE1; - putreg32(regval, STM32_RCC_CFGR); - - /* Enable PLL2 */ - - regval = getreg32(STM32_RCC_CR); - regval |= RCC_CR_PLL2ON; - putreg32(regval, STM32_RCC_CR); - - /* Wait for PLL2 ready */ - - while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0); - - /* Setup PLL3 for MII/RMII clock on MCO */ - -#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) - regval = getreg32(STM32_RCC_CFGR2); - regval &= ~(RCC_CFGR2_PLL3MUL_MASK); - regval |= STM32_PLL_PLL3MUL; - putreg32(regval, STM32_RCC_CFGR2); - - /* Switch PLL3 on */ - - regval = getreg32(STM32_RCC_CR); - regval |= RCC_CR_PLL3ON; - putreg32(regval, STM32_RCC_CR); - - while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL3RDY) == 0); -#endif - - /* Set main PLL source and multiplier */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK); - regval |= (RCC_CFGR_PLLSRC | STM32_PLL_PLLMUL); - putreg32(regval, STM32_RCC_CFGR); - - /* Switch main PLL on */ - - regval = getreg32(STM32_RCC_CR); - regval |= RCC_CR_PLLON; - putreg32(regval, STM32_RCC_CR); - - while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0); - - /* Select PLL as system clock source */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~RCC_CFGR_SW_MASK; - regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32_RCC_CFGR); - - /* Wait until PLL is used as the system clock source */ - - while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_PLL) == 0); -} -#endif - -/**************************************************************************** - * Name: stm32_stdclockconfig - * - * Description: - * Called to change to new clock based on settings in board.h. This - * version is for the non-Connectivity Line parts. - * - * NOTE: This logic would need to be extended if you need to select low- - * power clocking modes! - ****************************************************************************/ - -#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && \ - !defined(CONFIG_STM32_CONNECTIVITYLINE) +#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) static void stm32_stdclockconfig(void) { uint32_t regval; @@ -507,29 +391,6 @@ static void stm32_stdclockconfig(void) } } -# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) - /* If this is a value-line part and we are using the HSE as the PLL */ - -# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1) -# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1 -# endif - - /* Set the HSE prescaler */ - - regval = STM32_CFGR2_PREDIV1; - putreg32(regval, STM32_RCC_CFGR2); - -# endif -#endif - -#ifndef CONFIG_STM32_VALUELINE - /* Value-line devices don't implement flash prefetch/waitstates */ - /* Enable FLASH prefetch buffer and 2 wait states */ - - regval = getreg32(STM32_FLASH_ACR); - regval &= ~FLASH_ACR_LATENCY_MASK; - regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE); - putreg32(regval, STM32_FLASH_ACR); #endif /* Set the HCLK source/divider */ @@ -607,6 +468,12 @@ static void stm32_stdclockconfig(void) stm32_rcc_enablelse(); #endif + +#ifdef CONFIG_STM32_HRTIM_CLK_FROM_PLL + regval = getreg32(STM32_RCC_CFGR3); + regval |= RCC_CFGR3_HRTIM1SW; + putreg32(regval, STM32_RCC_CFGR3); +#endif } #endif diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 09f5d9860ff..29086d5706a 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -3414,6 +3414,18 @@ config UART5_RXDMA ---help--- In high data rate usage, Rx DMA may eliminate Rx overrun errors +config STM32L4_SERIAL_RXDMA_BUFFER_SIZE + int "Rx DMA buffer size" + default 32 + depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half this number of bytes. + + Value given here will be rounded up to next multiple of 32 bytes. + config SERIAL_DISABLE_REORDERING bool "Disable reordering of ttySx devices." depends on STM32L4_USART1 || STM32L4_USART2 || STM32L4_USART3 || STM32L4_UART4 || STM32L4_UART5 diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index f1a5550212c..2c8e9f1ae30 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -133,9 +133,18 @@ * * When streaming data, the generic serial layer will be called * every time the FIFO receives half this number of bytes. + * + * If there ever is a STM32L4 with D-cache, the buffer size + * should be an even multiple of ARMV7M_DCACHE_LINESIZE, so that it + * can be individually invalidated. */ -# define RXDMA_BUFFER_SIZE 32 +# if !defined(CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE == 0 +# define RXDMA_BUFFER_SIZE 32 +# else +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# endif /* DMA priority */ diff --git a/configs/clicker2-stm32/README.txt b/configs/clicker2-stm32/README.txt index af3cdcf38cf..b5bd02d9288 100644 --- a/configs/clicker2-stm32/README.txt +++ b/configs/clicker2-stm32/README.txt @@ -516,6 +516,8 @@ Configurations 2017-05-25: After some rather extensive debug, the TCP test was made to with (HC06 and short addressing). + 2017-06-26: Verified with HC06 and extended addressing. + Test Matrix: The following configurations have been tested: @@ -523,7 +525,7 @@ Configurations COMPRESSION ADDRESSING UDP TCP ----------- ---------- ---- ---- hc06 short 6/21 6/25 - extended 6/22 --- + extended 6/22 6/26 hc1 short 6/23 --- extended 6/23 --- ipv6 short --- --- diff --git a/net/sixlowpan/sixlowpan_framelist.c b/net/sixlowpan/sixlowpan_framelist.c index d98caff602a..53921963acc 100644 --- a/net/sixlowpan/sixlowpan_framelist.c +++ b/net/sixlowpan/sixlowpan_framelist.c @@ -122,8 +122,8 @@ * ****************************************************************************/ -static void sixlowpan_compress_ipv6hdr(FAR const struct ipv6_hdr_s *ipv6hdr, - FAR uint8_t *fptr) +static int sixlowpan_compress_ipv6hdr(FAR const struct ipv6_hdr_s *ipv6hdr, + FAR uint8_t *fptr) { /* Indicate the IPv6 dispatch and length */ @@ -135,6 +135,8 @@ static void sixlowpan_compress_ipv6hdr(FAR const struct ipv6_hdr_s *ipv6hdr, memcpy(&fptr[g_frame_hdrlen], ipv6hdr, IPv6_HDRLEN); g_frame_hdrlen += IPv6_HDRLEN; g_uncomp_hdrlen += IPv6_HDRLEN; + + return COMPRESS_HDR_INLINE; } /**************************************************************************** @@ -151,48 +153,42 @@ static uint16_t sixlowpan_protosize(FAR const struct ipv6_hdr_s *ipv6hdr, { uint16_t protosize; - /* Do we already have an encoded protocol header? If not, it needs to - * coped as raw data in the fist packet of a fragement. - */ + /* Copy the following protocol header, */ - if (!g_have_protohdr) - { - /* Copy the following protocol header, */ - - switch (ipv6hdr->proto) - { + switch (ipv6hdr->proto) + { #ifdef CONFIG_NET_TCP - case IP_PROTO_TCP: - { - FAR struct tcp_hdr_s *tcp = - &((FAR struct ipv6tcp_hdr_s *)ipv6hdr)->tcp; + case IP_PROTO_TCP: + { + FAR struct tcp_hdr_s *tcp = + &((FAR struct ipv6tcp_hdr_s *)ipv6hdr)->tcp; - /* The TCP header length is encoded in the top 4 bits of the - * tcpoffset field (in units of 32-bit words). - */ + /* The TCP header length is encoded in the top 4 bits of the + * tcpoffset field (in units of 32-bit words). + */ - protosize = ((uint16_t)tcp->tcpoffset >> 4) << 2; - } - break; + protosize = ((uint16_t)tcp->tcpoffset >> 4) << 2; + } + break; #endif #ifdef CONFIG_NET_UDP - case IP_PROTO_UDP: - protosize = UDP_HDRLEN; - break; + case IP_PROTO_UDP: + protosize = UDP_HDRLEN; + break; #endif #ifdef CONFIG_NET_ICMPv6 - case IP_PROTO_ICMP6: - protosize = ICMPv6_HDRLEN; - break; + case IP_PROTO_ICMP6: + protosize = ICMPv6_HDRLEN; + break; #endif - default: - nwarn("WARNING: Unrecognized proto: %u\n", ipv6hdr->proto); - return 0; - } - } + default: + nwarn("WARNING: Unrecognized proto: %u\n", ipv6hdr->proto); + protosize = 0; + break; + } return protosize; } @@ -260,7 +256,7 @@ int sixlowpan_queue_frames(FAR struct ieee802154_driver_s *ieee, g_uncomp_hdrlen = 0; g_frame_hdrlen = 0; - g_have_protohdr = false; + protosize = 0; /* Reset frame meta data */ @@ -381,9 +377,9 @@ int sixlowpan_queue_frames(FAR struct ieee802154_driver_s *ieee, /* Try to compress the headers */ #if defined(CONFIG_NET_6LOWPAN_COMPRESSION_HC1) - sixlowpan_compresshdr_hc1(ieee, destip, destmac, fptr); + ret = sixlowpan_compresshdr_hc1(ieee, destip, destmac, fptr); #elif defined(CONFIG_NET_6LOWPAN_COMPRESSION_HC06) - sixlowpan_compresshdr_hc06(ieee, destip, destmac, fptr); + ret = sixlowpan_compresshdr_hc06(ieee, destip, destmac, fptr); #else # error No compression specified #endif @@ -393,14 +389,17 @@ int sixlowpan_queue_frames(FAR struct ieee802154_driver_s *ieee, { /* Small.. use IPv6 dispatch (no compression) */ - sixlowpan_compress_ipv6hdr(destip, fptr); + ret = sixlowpan_compress_ipv6hdr(destip, fptr); } - ninfo("Header of length %d\n", g_frame_hdrlen); - /* Get the size of any uncompressed protocol headers */ - protosize = sixlowpan_protosize(destip, fptr); + if (ret == COMPRESS_HDR_INLINE) + { + protosize = sixlowpan_protosize(destip, fptr); + } + + ninfo("Header of length=%u protosize=%u\n", g_frame_hdrlen, protosize); /* Check if we need to fragment the packet into several frames */ diff --git a/net/sixlowpan/sixlowpan_globals.c b/net/sixlowpan/sixlowpan_globals.c index 0d9aa8f4411..6d52082df18 100644 --- a/net/sixlowpan/sixlowpan_globals.c +++ b/net/sixlowpan/sixlowpan_globals.c @@ -67,8 +67,4 @@ uint8_t g_uncomp_hdrlen; uint8_t g_frame_hdrlen; -/* g_have_protohdr: true=Protocal header copied. */ - -bool g_have_protohdr; - #endif /* CONFIG_NET_6LOWPAN */ diff --git a/net/sixlowpan/sixlowpan_hc06.c b/net/sixlowpan/sixlowpan_hc06.c index 1ed058a0243..ec9577e1dc6 100644 --- a/net/sixlowpan/sixlowpan_hc06.c +++ b/net/sixlowpan/sixlowpan_hc06.c @@ -587,20 +587,22 @@ void sixlowpan_hc06_initialize(void) * fptr - Pointer to frame to be compressed. * * Returned Value: - * None + * On success the indications of the defines COMPRESS_HDR_* are returned. + * A negated errno value is returned on failure. * ****************************************************************************/ -void sixlowpan_compresshdr_hc06(FAR struct ieee802154_driver_s *ieee, - FAR const struct ipv6_hdr_s *ipv6, - FAR const struct sixlowpan_tagaddr_s *destmac, - FAR uint8_t *fptr) +int sixlowpan_compresshdr_hc06(FAR struct ieee802154_driver_s *ieee, + FAR const struct ipv6_hdr_s *ipv6, + FAR const struct sixlowpan_tagaddr_s *destmac, + FAR uint8_t *fptr) { FAR uint8_t *iphc = fptr + g_frame_hdrlen; FAR struct sixlowpan_addrcontext_s *addrcontext; uint8_t iphc0; uint8_t iphc1; uint8_t tmp; + int ret = COMPRESS_HDR_INLINE; ninfo("fptr=%p g_frame_hdrlen=%u iphc=%p\n", fptr, g_frame_hdrlen, iphc); @@ -956,7 +958,7 @@ void sixlowpan_compresshdr_hc06(FAR struct ieee802154_driver_s *ieee, memcpy(g_hc06ptr, &udp->udpchksum, 2); g_hc06ptr += 2; g_uncomp_hdrlen += UDP_HDRLEN; - g_have_protohdr = true; + ret = COMPRESS_HDR_ELIDED; } #endif /* CONFIG_NET_UDP */ @@ -970,7 +972,7 @@ void sixlowpan_compresshdr_hc06(FAR struct ieee802154_driver_s *ieee, ninfo("fptr=%p g_frame_hdrlen=%u iphc=%02x:%02x:%02x g_hc06ptr=%p\n", fptr, g_frame_hdrlen, iphc[0], iphc[1], iphc[2], g_hc06ptr); - return; + return ret; } /**************************************************************************** diff --git a/net/sixlowpan/sixlowpan_hc1.c b/net/sixlowpan/sixlowpan_hc1.c index 82019aaae76..7f24654262e 100644 --- a/net/sixlowpan/sixlowpan_hc1.c +++ b/net/sixlowpan/sixlowpan_hc1.c @@ -140,16 +140,18 @@ static void sixlowpan_uncompress_addr(FAR const struct ieee802154_addr_s *addr, * fptr - Pointer to frame to be compressed. * * Returned Value: - * None + * On success the indications of the defines COMPRESS_HDR_* are returned. + * A negated errno value is returned on failure. * ****************************************************************************/ -void sixlowpan_compresshdr_hc1(FAR struct ieee802154_driver_s *ieee, - FAR const struct ipv6_hdr_s *ipv6, - FAR const struct sixlowpan_tagaddr_s *destmac, - FAR uint8_t *fptr) +int sixlowpan_compresshdr_hc1(FAR struct ieee802154_driver_s *ieee, + FAR const struct ipv6_hdr_s *ipv6, + FAR const struct sixlowpan_tagaddr_s *destmac, + FAR uint8_t *fptr) { FAR uint8_t *hc1 = fptr + g_frame_hdrlen; + int ret = COMPRESS_HDR_INLINE; /* Check if all the assumptions for full compression are valid */ @@ -266,7 +268,7 @@ void sixlowpan_compresshdr_hc1(FAR struct ieee802154_driver_s *ieee, g_frame_hdrlen += SIXLOWPAN_HC1_HDR_LEN; } - g_have_protohdr = true; + ret = COMPRESS_HDR_ELIDED; } break; #endif /* CONFIG_NET_UDP */ @@ -281,6 +283,8 @@ void sixlowpan_compresshdr_hc1(FAR struct ieee802154_driver_s *ieee, break; } } + + return ret; } /**************************************************************************** diff --git a/net/sixlowpan/sixlowpan_internal.h b/net/sixlowpan/sixlowpan_internal.h index 8a263131695..0c94d05dbaf 100644 --- a/net/sixlowpan/sixlowpan_internal.h +++ b/net/sixlowpan/sixlowpan_internal.h @@ -119,6 +119,13 @@ } \ while(0) +/* Return values ************************************************************/ + +/* Sucessful return values from header compression logic */ + +#define COMPRESS_HDR_INLINE 0 /* L2 header not compressed */ +#define COMPRESS_HDR_ELIDED 1 /* L2 header compressed */ + /* Debug ********************************************************************/ #ifdef CONFIG_NET_6LOWPAN_DUMPBUFFER @@ -209,10 +216,6 @@ extern uint8_t g_uncomp_hdrlen; extern uint8_t g_frame_hdrlen; -/* g_have_protohdr: true=Protocal header copied. */ - -extern bool g_have_protohdr; - /**************************************************************************** * Public Types ****************************************************************************/ @@ -422,15 +425,16 @@ void sixlowpan_hc06_initialize(void); * fptr - Pointer to frame to be compressed. * * Returned Value: - * None + * On success the indications of the defines COMPRESS_HDR_* are returned. + * A negated errno value is returned on failure. * ****************************************************************************/ #ifdef CONFIG_NET_6LOWPAN_COMPRESSION_HC06 -void sixlowpan_compresshdr_hc06(FAR struct ieee802154_driver_s *ieee, - FAR const struct ipv6_hdr_s *ipv6, - FAR const struct sixlowpan_tagaddr_s *destmac, - FAR uint8_t *fptr); +int sixlowpan_compresshdr_hc06(FAR struct ieee802154_driver_s *ieee, + FAR const struct ipv6_hdr_s *ipv6, + FAR const struct sixlowpan_tagaddr_s *destmac, + FAR uint8_t *fptr); #endif /**************************************************************************** @@ -485,15 +489,16 @@ void sixlowpan_uncompresshdr_hc06(FAR const struct ieee802154_data_ind_s *ind, * fptr - Pointer to frame to be compressed. * * Returned Value: - * None + * On success the indications of the defines COMPRESS_HDR_* are returned. + * A negated errno value is returned on failure. * ****************************************************************************/ #ifdef CONFIG_NET_6LOWPAN_COMPRESSION_HC1 -void sixlowpan_compresshdr_hc1(FAR struct ieee802154_driver_s *ieee, - FAR const struct ipv6_hdr_s *ipv6, - FAR const struct sixlowpan_tagaddr_s *destmac, - FAR uint8_t *fptr); +int sixlowpan_compresshdr_hc1(FAR struct ieee802154_driver_s *ieee, + FAR const struct ipv6_hdr_s *ipv6, + FAR const struct sixlowpan_tagaddr_s *destmac, + FAR uint8_t *fptr); #endif /**************************************************************************** diff --git a/wireless/ieee802154/mac802154_loopback.c b/wireless/ieee802154/mac802154_loopback.c index 63ec1bd4182..f0bf2c70d64 100644 --- a/wireless/ieee802154/mac802154_loopback.c +++ b/wireless/ieee802154/mac802154_loopback.c @@ -205,8 +205,6 @@ static void lo_addr2ip(FAR struct net_driver_s *dev) dev->d_ipv6addr[6] = (uint16_t)g_eaddr[4] << 8 | (uint16_t)g_eaddr[5]; dev->d_ipv6addr[7] = (uint16_t)g_eaddr[6] << 8 | (uint16_t)g_eaddr[7]; dev->d_ipv6addr[4] ^= 0x200; - - memcpy(dev->d_mac.ieee802154, g_eaddr, IEEE802154_EADDRSIZE); } #else static void lo_addr2ip(FAR struct net_driver_s *dev)