From 406bc5e67e8291303adfdbc48f9ee8f8e79b5e1f Mon Sep 17 00:00:00 2001 From: pnb Date: Tue, 22 Dec 2015 13:26:22 +0100 Subject: [PATCH] continue capture --- arch/arm/src/stm32/stm32_capture.c | 148 ++++++- arch/arm/src/stm32/stm32_capture.h | 604 +---------------------------- 2 files changed, 141 insertions(+), 611 deletions(-) diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/stm32/stm32_capture.c index fd85d2d3fab..360c9101c08 100644 --- a/arch/arm/src/stm32/stm32_capture.c +++ b/arch/arm/src/stm32/stm32_capture.c @@ -99,17 +99,11 @@ defined(CONFIG_STM32_TIM9_CAP) || defined(CONFIG_STM32_TIM10_CAP) || defined(CONFIG_STM32_TIM11_CAP) || \ defined(CONFIG_STM32_TIM12_CAP) || defined(CONFIG_STM32_TIM13_CAP) || defined(CONFIG_STM32_TIM14_CAP) + /************************************************************************************ * Private Types ************************************************************************************/ -struct stm32_cap_channel_s -{ - uint8_t ch_id; - uint16_t ccmr; - uint32_t gpio; -} - /* TIM Device Structure */ struct stm32_cap_priv_s @@ -120,7 +114,6 @@ struct stm32_cap_priv_s #define HAVE_ADANCED_TIM 1 const int irq_of; /* irq timer overflow is deferent in advanced timer */ #endif - const stm32_cap_channel_s channels[CAP_NCHANNELS]; }; /************************************************************************************ @@ -172,6 +165,134 @@ static inline void stm32_putreg32(FAR struct stm32_cap_priv_s *priv, uint8_t off putreg32(value, priv->base + offset); } + +/************************************************************************************ + * gpio Functions + ************************************************************************************/ + +static inline uint32_t stm32_cap_gpio(FAR struct stm32_cap_priv_s *priv, int channel) +{ + + switch(priv->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + switch (channel) + { +#if defined(GPIO_TIM1_CH1IN) + case 0: return GPIO_TIM1_CH1IN; +#endif +#if defined(GPIO_TIM1_CH2IN) + case 1: return GPIO_TIM1_CH2IN; +#endif +#if defined(GPIO_TIM1_CH3IN) + case 2: return GPIO_TIM1_CH3IN; +#endif +#if defined(GPIO_TIM1_CH4IN) + case 3: return GPIO_TIM1_CH4IN; +#endif + } + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + switch (channel) + { +#if defined(GPIO_TIM2_CH1IN) + case 0: return GPIO_TIM2_CH1IN; +#endif +#if defined(GPIO_TIM2_CH2IN) + case 1: return GPIO_TIM2_CH2IN; +#endif +#if defined(GPIO_TIM2_CH3IN) + case 2: return GPIO_TIM2_CH3IN; +#endif +#if defined(GPIO_TIM2_CH4IN) + case 3: return GPIO_TIM2_CH4IN; +#endif + } + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + switch (channel) + { +#if defined(GPIO_TIM3_CH1IN) + case 0: return GPIO_TIM3_CH1IN; +#endif +#if defined(GPIO_TIM3_CH2IN) + case 1: return GPIO_TIM3_CH2IN; +#endif +#if defined(GPIO_TIM3_CH3IN) + case 2: return GPIO_TIM3_CH3IN; +#endif +#if defined(GPIO_TIM3_CH4IN) + case 3: return GPIO_TIM3_CH4IN; +#endif + } + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + switch (channel) + { +#if defined(GPIO_TIM4_CH1IN) + case 0: return GPIO_TIM4_CH1IN; +#endif +#if defined(GPIO_TIM4_CH2IN) + case 1: return GPIO_TIM4_CH2IN; +#endif +#if defined(GPIO_TIM4_CH3IN) + case 2: return GPIO_TIM4_CH3IN; +#endif +#if defined(GPIO_TIM4_CH4IN) + case 3: return GPIO_TIM4_CH4IN; +#endif + } + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + switch (channel) + { +#if defined(GPIO_TIM5_CH1IN) + case 0: return GPIO_TIM5_CH1IN; +#endif +#if defined(GPIO_TIM5_CH2IN) + case 1: return GPIO_TIM5_CH2IN; +#endif +#if defined(GPIO_TIM5_CH3IN) + case 2: return GPIO_TIM5_CH3IN; +#endif +#if defined(GPIO_TIM5_CH4IN) + case 3: return GPIO_TIM5_CH4IN; +#endif + } + break; +#endif + +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + switch (channel) + { +#if defined(GPIO_TIM8_CH1IN) + case 0: return GPIO_TIM8_CH1OUIN ; +#endif +#if defined(GPIO_TIM8_CH2IN) + case 1: return GPIO_TIM8_CH2OUIN ; +#endif +#if defined(GPIO_TIM8_CH3IN) + case 2: return GPIO_TIM8_CH3OUIN ; +#endif +#if defined(GPIO_TIM8_CH4IN) + case 3: return GPIO_TIM8_CH4OUIN ; +#endif + } + break; +#endif + } + return gpio; +} /************************************************************************************ * Basic Functions ************************************************************************************/ @@ -408,15 +529,7 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel ASSERT(dev); - i = CAP_NCHANNELS; - while(i--) - { - if ( priv->channels[i].ch_id == channel ) - { - gpio = priv->channels[i].gpio; - break; - } - } + gpio = stm32_cap_gpio(priv,channel); if ( gpio == 0 ) return ERROR; @@ -424,7 +537,6 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel /* change to zero base index */ channel--; - /* Set ccer */ switch (cfg & STM32_CAP_EDGE_MASK) { diff --git a/arch/arm/src/stm32/stm32_capture.h b/arch/arm/src/stm32/stm32_capture.h index e3eb1f388ec..744b6852690 100644 --- a/arch/arm/src/stm32/stm32_capture.h +++ b/arch/arm/src/stm32/stm32_capture.h @@ -48,588 +48,6 @@ #include "chip/stm32_tim.h" -#ifdef CONFIG_STM32_TIM1_CHANNEL1 -# ifdef CONFIG_STM32_TIM1_CH1OUT -# define CAP_TIM1_CH1CFG GPIO_TIM1_CH1OUT -# else -# define CAP_TIM1_CH1CFG 0 -# endif -# define CAP_TIM1_CHANNEL1 1 -#else -# define CAP_TIM1_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL2 -# ifdef CONFIG_STM32_TIM1_CH2OUT -# define CAP_TIM1_CH2CFG GPIO_TIM1_CH2OUT -# else -# define CAP_TIM1_CH2CFG 0 -# endif -# define CAP_TIM1_CHANNEL2 1 -#else -# define CAP_TIM1_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL3 -# ifdef CONFIG_STM32_TIM1_CH3OUT -# define CAP_TIM1_CH3CFG GPIO_TIM1_CH3OUT -# else -# define CAP_TIM1_CH3CFG 0 -# endif -# define CAP_TIM1_CHANNEL3 1 -#else -# define CAP_TIM1_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM1_CHANNEL4 -# ifdef CONFIG_STM32_TIM1_CH4OUT -# define CAP_TIM1_CH4CFG GPIO_TIM1_CH4OUT -# else -# define CAP_TIM1_CH4CFG 0 -# endif -# define CAP_TIM1_CHANNEL4 1 -#else -# define CAP_TIM1_CHANNEL4 0 -#endif -#define CAP_TIM1_NCHANNELS (CAP_TIM1_CHANNEL1 + CAP_TIM1_CHANNEL2 + \ - CAP_TIM1_CHANNEL3 + CAP_TIM1_CHANNEL4) - -#ifdef CONFIG_STM32_TIM2_CHANNEL1 -# ifdef CONFIG_STM32_TIM2_CH1OUT -# define CAP_TIM2_CH1CFG GPIO_TIM2_CH1OUT -# else -# define CAP_TIM2_CH1CFG 0 -# endif -# define CAP_TIM2_CHANNEL1 1 -#else -# define CAP_TIM2_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM2_CHANNEL2 -# ifdef CONFIG_STM32_TIM2_CH2OUT -# define CAP_TIM2_CH2CFG GPIO_TIM2_CH2OUT -# else -# define CAP_TIM2_CH2CFG 0 -# endif -# define CAP_TIM2_CHANNEL2 1 -#else -# define CAP_TIM2_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM2_CHANNEL3 -# ifdef CONFIG_STM32_TIM2_CH3OUT -# define CAP_TIM2_CH3CFG GPIO_TIM2_CH3OUT -# else -# define CAP_TIM2_CH3CFG 0 -# endif -# define CAP_TIM2_CHANNEL3 1 -#else -# define CAP_TIM2_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM2_CHANNEL4 -# ifdef CONFIG_STM32_TIM2_CH4OUT -# define CAP_TIM2_CH4CFG GPIO_TIM2_CH4OUT -# else -# define CAP_TIM2_CH4CFG 0 -# endif -# define CAP_TIM2_CHANNEL4 1 -#else -# define CAP_TIM2_CHANNEL4 0 -#endif -#define CAP_TIM2_NCHANNELS (CAP_TIM2_CHANNEL1 + CAP_TIM2_CHANNEL2 + \ - CAP_TIM2_CHANNEL3 + CAP_TIM2_CHANNEL4) - -#ifdef CONFIG_STM32_TIM3_CHANNEL1 -# ifdef CONFIG_STM32_TIM3_CH1OUT -# define CAP_TIM3_CH1CFG GPIO_TIM3_CH1OUT -# else -# define CAP_TIM3_CH1CFG 0 -# endif -# define CAP_TIM3_CHANNEL1 1 -#else -# define CAP_TIM3_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM3_CHANNEL2 -# ifdef CONFIG_STM32_TIM3_CH2OUT -# define CAP_TIM3_CH2CFG GPIO_TIM3_CH2OUT -# else -# define CAP_TIM3_CH2CFG 0 -# endif -# define CAP_TIM3_CHANNEL2 1 -#else -# define CAP_TIM3_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM3_CHANNEL3 -# ifdef CONFIG_STM32_TIM3_CH3OUT -# define CAP_TIM3_CH3CFG GPIO_TIM3_CH3OUT -# else -# define CAP_TIM3_CH3CFG 0 -# endif -# define CAP_TIM3_CHANNEL3 1 -#else -# define CAP_TIM3_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM3_CHANNEL4 -# ifdef CONFIG_STM32_TIM3_CH4OUT -# define CAP_TIM3_CH4CFG GPIO_TIM3_CH4OUT -# else -# define CAP_TIM3_CH4CFG 0 -# endif -# define CAP_TIM3_CHANNEL4 1 -#else -# define CAP_TIM3_CHANNEL4 0 -#endif -#define CAP_TIM3_NCHANNELS (CAP_TIM3_CHANNEL1 + CAP_TIM3_CHANNEL2 + \ - CAP_TIM3_CHANNEL3 + CAP_TIM3_CHANNEL4) - -#ifdef CONFIG_STM32_TIM4_CHANNEL1 -# ifdef CONFIG_STM32_TIM4_CH1OUT -# define CAP_TIM4_CH1CFG GPIO_TIM4_CH1OUT -# else -# define CAP_TIM4_CH1CFG 0 -# endif -# define CAP_TIM4_CHANNEL1 1 -#else -# define CAP_TIM4_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM4_CHANNEL2 -# ifdef CONFIG_STM32_TIM4_CH2OUT -# define CAP_TIM4_CH2CFG GPIO_TIM4_CH2OUT -# else -# define CAP_TIM4_CH2CFG 0 -# endif -# define CAP_TIM4_CHANNEL2 1 -#else -# define CAP_TIM4_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM4_CHANNEL3 -# ifdef CONFIG_STM32_TIM4_CH3OUT -# define CAP_TIM4_CH3CFG GPIO_TIM4_CH3OUT -# else -# define CAP_TIM4_CH3CFG 0 -# endif -# define CAP_TIM4_CHANNEL3 1 -#else -# define CAP_TIM4_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM4_CHANNEL4 -# ifdef CONFIG_STM32_TIM4_CH4OUT -# define CAP_TIM4_CH4CFG GPIO_TIM4_CH4OUT -# else -# define CAP_TIM4_CH4CFG 0 -# endif -# define CAP_TIM4_CHANNEL4 1 -#else -# define CAP_TIM4_CHANNEL4 0 -#endif -#define CAP_TIM4_NCHANNELS (CAP_TIM4_CHANNEL1 + CAP_TIM4_CHANNEL2 + \ - CAP_TIM4_CHANNEL3 + CAP_TIM4_CHANNEL4) - -#ifdef CONFIG_STM32_TIM5_CHANNEL1 -# ifdef CONFIG_STM32_TIM5_CH1OUT -# define CAP_TIM5_CH1CFG GPIO_TIM5_CH1OUT -# else -# define CAP_TIM5_CH1CFG 0 -# endif -# define CAP_TIM5_CHANNEL1 1 -#else -# define CAP_TIM5_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM5_CHANNEL2 -# ifdef CONFIG_STM32_TIM5_CH2OUT -# define CAP_TIM5_CH2CFG GPIO_TIM5_CH2OUT -# else -# define CAP_TIM5_CH2CFG 0 -# endif -# define CAP_TIM5_CHANNEL2 1 -#else -# define CAP_TIM5_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM5_CHANNEL3 -# ifdef CONFIG_STM32_TIM5_CH3OUT -# define CAP_TIM5_CH3CFG GPIO_TIM5_CH3OUT -# else -# define CAP_TIM5_CH3CFG 0 -# endif -# define CAP_TIM5_CHANNEL3 1 -#else -# define CAP_TIM5_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM5_CHANNEL4 -# ifdef CONFIG_STM32_TIM5_CH4OUT -# define CAP_TIM5_CH4CFG GPIO_TIM5_CH4OUT -# else -# define CAP_TIM5_CH4CFG 0 -# endif -# define CAP_TIM5_CHANNEL4 1 -#else -# define CAP_TIM5_CHANNEL4 0 -#endif -#define CAP_TIM5_NCHANNELS (CAP_TIM5_CHANNEL1 + CAP_TIM5_CHANNEL2 + \ - CAP_TIM5_CHANNEL3 + CAP_TIM5_CHANNEL4) - -#ifdef CONFIG_STM32_TIM8_CHANNEL1 -# ifdef CONFIG_STM32_TIM8_CH1OUT -# define CAP_TIM8_CH1CFG GPIO_TIM8_CH1OUT -# else -# define CAP_TIM8_CH1CFG 0 -# endif -# define CAP_TIM8_CHANNEL1 1 -#else -# define CAP_TIM8_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL2 -# ifdef CONFIG_STM32_TIM8_CH2OUT -# define CAP_TIM8_CH2CFG GPIO_TIM8_CH2OUT -# else -# define CAP_TIM8_CH2CFG 0 -# endif -# define CAP_TIM8_CHANNEL2 1 -#else -# define CAP_TIM8_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL3 -# ifdef CONFIG_STM32_TIM8_CH3OUT -# define CAP_TIM8_CH3CFG GPIO_TIM8_CH3OUT -# else -# define CAP_TIM8_CH3CFG 0 -# endif -# define CAP_TIM8_CHANNEL3 1 -#else -# define CAP_TIM8_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM8_CHANNEL4 -# ifdef CONFIG_STM32_TIM8_CH4OUT -# define CAP_TIM8_CH4CFG GPIO_TIM8_CH4OUT -# else -# define CAP_TIM8_CH4CFG 0 -# endif -# define CAP_TIM8_CHANNEL4 1 -#else -# define CAP_TIM8_CHANNEL4 0 -#endif -#define CAP_TIM8_NCHANNELS (CAP_TIM8_CHANNEL1 + CAP_TIM8_CHANNEL2 + \ - CAP_TIM8_CHANNEL3 + CAP_TIM8_CHANNEL4) - -#ifdef CONFIG_STM32_TIM9_CHANNEL1 -# ifdef CONFIG_STM32_TIM9_CH1OUT -# define CAP_TIM9_CH1CFG GPIO_TIM9_CH1OUT -# else -# define CAP_TIM9_CH1CFG 0 -# endif -# define CAP_TIM9_CHANNEL1 1 -#else -# define CAP_TIM9_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM9_CHANNEL2 -# ifdef CONFIG_STM32_TIM9_CH2OUT -# define CAP_TIM9_CH2CFG GPIO_TIM9_CH2OUT -# else -# define CAP_TIM9_CH2CFG 0 -# endif -# define CAP_TIM9_CHANNEL2 1 -#else -# define CAP_TIM9_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM9_CHANNEL3 -# ifdef CONFIG_STM32_TIM9_CH3OUT -# define CAP_TIM9_CH3CFG GPIO_TIM9_CH3OUT -# else -# define CAP_TIM9_CH3CFG 0 -# endif -# define CAP_TIM9_CHANNEL3 1 -#else -# define CAP_TIM9_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM9_CHANNEL4 -# ifdef CONFIG_STM32_TIM9_CH4OUT -# define CAP_TIM9_CH4CFG GPIO_TIM9_CH4OUT -# else -# define CAP_TIM9_CH4CFG 0 -# endif -# define CAP_TIM9_CHANNEL4 1 -#else -# define CAP_TIM9_CHANNEL4 0 -#endif -#define CAP_TIM9_NCHANNELS (CAP_TIM9_CHANNEL1 + CAP_TIM9_CHANNEL2 + \ - CAP_TIM9_CHANNEL3 + CAP_TIM9_CHANNEL4) - -#ifdef CONFIG_STM32_TIM10_CHANNEL1 -# ifdef CONFIG_STM32_TIM10_CH1OUT -# define CAP_TIM10_CH1CFG GPIO_TIM10_CH1OUT -# else -# define CAP_TIM10_CH1CFG 0 -# endif -# define CAP_TIM10_CHANNEL1 1 -#else -# define CAP_TIM10_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM10_CHANNEL2 -# ifdef CONFIG_STM32_TIM10_CH2OUT -# define CAP_TIM10_CH2CFG GPIO_TIM10_CH2OUT -# else -# define CAP_TIM10_CH2CFG 0 -# endif -# define CAP_TIM10_CHANNEL2 1 -#else -# define CAP_TIM10_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM10_CHANNEL3 -# ifdef CONFIG_STM32_TIM10_CH3OUT -# define CAP_TIM10_CH3CFG GPIO_TIM10_CH3OUT -# else -# define CAP_TIM10_CH3CFG 0 -# endif -# define CAP_TIM10_CHANNEL3 1 -#else -# define CAP_TIM10_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM10_CHANNEL4 -# ifdef CONFIG_STM32_TIM10_CH4OUT -# define CAP_TIM10_CH4CFG GPIO_TIM10_CH4OUT -# else -# define CAP_TIM10_CH4CFG 0 -# endif -# define CAP_TIM10_CHANNEL4 1 -#else -# define CAP_TIM10_CHANNEL4 0 -#endif -#define CAP_TIM10_NCHANNELS (CAP_TIM10_CHANNEL1 + CAP_TIM10_CHANNEL2 + \ - CAP_TIM10_CHANNEL3 + CAP_TIM10_CHANNEL4) - -#ifdef CONFIG_STM32_TIM11_CHANNEL1 -# ifdef CONFIG_STM32_TIM11_CH1OUT -# define CAP_TIM11_CH1CFG GPIO_TIM11_CH1OUT -# else -# define CAP_TIM11_CH1CFG 0 -# endif -# define CAP_TIM11_CHANNEL1 1 -#else -# define CAP_TIM11_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM11_CHANNEL2 -# ifdef CONFIG_STM32_TIM11_CH2OUT -# define CAP_TIM11_CH2CFG GPIO_TIM11_CH2OUT -# else -# define CAP_TIM11_CH2CFG 0 -# endif -# define CAP_TIM11_CHANNEL2 1 -#else -# define CAP_TIM11_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM11_CHANNEL3 -# ifdef CONFIG_STM32_TIM11_CH3OUT -# define CAP_TIM11_CH3CFG GPIO_TIM11_CH3OUT -# else -# define CAP_TIM11_CH3CFG 0 -# endif -# define CAP_TIM11_CHANNEL3 1 -#else -# define CAP_TIM11_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM11_CHANNEL4 -# ifdef CONFIG_STM32_TIM11_CH4OUT -# define CAP_TIM11_CH4CFG GPIO_TIM11_CH4OUT -# else -# define CAP_TIM11_CH4CFG 0 -# endif -# define CAP_TIM11_CHANNEL4 1 -#else -# define CAP_TIM11_CHANNEL4 0 -#endif -#define CAP_TIM11_NCHANNELS (CAP_TIM11_CHANNEL1 + CAP_TIM11_CHANNEL2 + \ - CAP_TIM11_CHANNEL3 + CAP_TIM11_CHANNEL4) - -#ifdef CONFIG_STM32_TIM12_CHANNEL1 -# ifdef CONFIG_STM32_TIM12_CH1OUT -# define CAP_TIM12_CH1CFG GPIO_TIM12_CH1OUT -# else -# define CAP_TIM12_CH1CFG 0 -# endif -# define CAP_TIM12_CHANNEL1 1 -#else -# define CAP_TIM12_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM12_CHANNEL2 -# ifdef CONFIG_STM32_TIM12_CH2OUT -# define CAP_TIM12_CH2CFG GPIO_TIM12_CH2OUT -# else -# define CAP_TIM12_CH2CFG 0 -# endif -# define CAP_TIM12_CHANNEL2 1 -#else -# define CAP_TIM12_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM12_CHANNEL3 -# ifdef CONFIG_STM32_TIM12_CH3OUT -# define CAP_TIM12_CH3CFG GPIO_TIM12_CH3OUT -# else -# define CAP_TIM12_CH3CFG 0 -# endif -# define CAP_TIM12_CHANNEL3 1 -#else -# define CAP_TIM12_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM12_CHANNEL4 -# ifdef CONFIG_STM32_TIM12_CH4OUT -# define CAP_TIM12_CH4CFG GPIO_TIM12_CH4OUT -# else -# define CAP_TIM12_CH4CFG 0 -# endif -# define CAP_TIM12_CHANNEL4 1 -#else -# define CAP_TIM12_CHANNEL4 0 -#endif -#define CAP_TIM12_NCHANNELS (CAP_TIM12_CHANNEL1 + CAP_TIM12_CHANNEL2 + \ - CAP_TIM12_CHANNEL3 + CAP_TIM12_CHANNEL4) - -#ifdef CONFIG_STM32_TIM13_CHANNEL1 -# ifdef CONFIG_STM32_TIM13_CH1OUT -# define CAP_TIM13_CH1CFG GPIO_TIM13_CH1OUT -# else -# define CAP_TIM13_CH1CFG 0 -# endif -# define CAP_TIM13_CHANNEL1 1 -#else -# define CAP_TIM13_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM13_CHANNEL2 -# ifdef CONFIG_STM32_TIM13_CH2OUT -# define CAP_TIM13_CH2CFG GPIO_TIM13_CH2OUT -# else -# define CAP_TIM13_CH2CFG 0 -# endif -# define CAP_TIM13_CHANNEL2 1 -#else -# define CAP_TIM13_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM13_CHANNEL3 -# ifdef CONFIG_STM32_TIM13_CH3OUT -# define CAP_TIM13_CH3CFG GPIO_TIM13_CH3OUT -# else -# define CAP_TIM13_CH3CFG 0 -# endif -# define CAP_TIM13_CHANNEL3 1 -#else -# define CAP_TIM13_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM13_CHANNEL4 -# ifdef CONFIG_STM32_TIM13_CH4OUT -# define CAP_TIM13_CH4CFG GPIO_TIM13_CH4OUT -# else -# define CAP_TIM13_CH4CFG 0 -# endif -# define CAP_TIM13_CHANNEL4 1 -#else -# define CAP_TIM13_CHANNEL4 0 -#endif -#define CAP_TIM13_NCHANNELS (CAP_TIM13_CHANNEL1 + CAP_TIM13_CHANNEL2 + \ - CAP_TIM13_CHANNEL3 + CAP_TIM13_CHANNEL4) - -#ifdef CONFIG_STM32_TIM14_CHANNEL1 -# ifdef CONFIG_STM32_TIM14_CH1OUT -# define CAP_TIM14_CH1CFG GPIO_TIM14_CH1OUT -# else -# define CAP_TIM14_CH1CFG 0 -# endif -# define CAP_TIM14_CHANNEL1 1 -#else -# define CAP_TIM14_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM14_CHANNEL2 -# ifdef CONFIG_STM32_TIM14_CH2OUT -# define CAP_TIM14_CH2CFG GPIO_TIM14_CH2OUT -# else -# define CAP_TIM14_CH2CFG 0 -# endif -# define CAP_TIM14_CHANNEL2 1 -#else -# define CAP_TIM14_CHANNEL2 0 -#endif -#ifdef CONFIG_STM32_TIM14_CHANNEL3 -# ifdef CONFIG_STM32_TIM14_CH3OUT -# define CAP_TIM14_CH3CFG GPIO_TIM14_CH3OUT -# else -# define CAP_TIM14_CH3CFG 0 -# endif -# define CAP_TIM14_CHANNEL3 1 -#else -# define CAP_TIM14_CHANNEL3 0 -#endif -#ifdef CONFIG_STM32_TIM14_CHANNEL4 -# ifdef CONFIG_STM32_TIM14_CH4OUT -# define CAP_TIM14_CH4CFG GPIO_TIM14_CH4OUT -# else -# define CAP_TIM14_CH4CFG 0 -# endif -# define CAP_TIM14_CHANNEL4 1 -#else -# define CAP_TIM14_CHANNEL4 0 -#endif -#define CAP_TIM14_NCHANNELS (CAP_TIM14_CHANNEL1 + CAP_TIM14_CHANNEL2 + \ - CAP_TIM14_CHANNEL3 + CAP_TIM14_CHANNEL4) - -#ifdef CONFIG_STM32_TIM15_CHANNEL1 -# ifdef CONFIG_STM32_TIM15_CH1OUT -# define CAP_TIM15_CH1CFG GPIO_TIM15_CH1OUT -# else -# define CAP_TIM15_CH1CFG 0 -# endif -# define CAP_TIM15_CHANNEL1 1 -#else -# define CAP_TIM15_CHANNEL1 0 -#endif -#ifdef CONFIG_STM32_TIM15_CHANNEL2 -# ifdef CONFIG_STM32_TIM15_CH2OUT -# define CAP_TIM15_CH2CFG GPIO_TIM15_CH2OUT -# else -# define CAP_TIM15_CH2CFG 0 -# endif -# define CAP_TIM15_CHANNEL2 1 -#else -# define CAP_TIM15_CHANNEL2 0 -#endif -#define CAP_TIM15_NCHANNELS (CAP_TIM15_CHANNEL1 + CAP_TIM15_CHANNEL2) - -#ifdef CONFIG_STM32_TIM16_CHANNEL1 -# ifdef CONFIG_STM32_TIM16_CH1OUT -# define CAP_TIM16_CH1CFG GPIO_TIM16_CH1OUT -# else -# define CAP_TIM16_CH1CFG 0 -# endif -# define CAP_TIM16_CHANNEL1 1 -#else -# define CAP_TIM16_CHANNEL1 0 -#endif -#define CAP_TIM16_NCHANNELS CAP_TIM16_CHANNEL1 - -#ifdef CONFIG_STM32_TIM17_CHANNEL1 -# ifdef CONFIG_STM32_TIM17_CH1OUT -# define CAP_TIM17_CH1CFG GPIO_TIM17_CH1OUT -# else -# define CAP_TIM17_CH1CFG 0 -# endif -# define CAP_TIM17_CHANNEL1 1 -#else -# define CAP_TIM17_CHANNEL1 0 -#endif -#define CAP_TIM17_NCHANNELS CAP_TIM17_CHANNEL1 - -#define CAP_MAX(a, b) ((a) > (b) ? (a) : (b)) - -#define CAP_NCHANNELS CAP_MAX(CAP_TIM1_NCHANNELS, \ - CAP_MAX(CAP_TIM2_NCHANNELS, \ - CAP_MAX(CAP_TIM3_NCHANNELS, \ - CAP_MAX(CAP_TIM4_NCHANNELS, \ - CAP_MAX(CAP_TIM5_NCHANNELS, \ - CAP_MAX(CAP_TIM8_NCHANNELS, \ - CAP_MAX(CAP_TIM9_NCHANNELS, \ - CAP_MAX(CAP_TIM10_NCHANNELS, \ - CAP_MAX(CAP_TIM11_NCHANNELS, \ - CAP_MAX(CAP_TIM12_NCHANNELS, \ - CAP_MAX(CAP_TIM13_NCHANNELS, \ - CAP_MAX(CAP_TIM14_NCHANNELS, \ - CAP_MAX(CAP_TIM15_NCHANNELS, \ - CAP_MAX(CAP_TIM16_NCHANNELS, \ - CAP_TIM17_NCHANNELS)))))))))))))) - -#endif - /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -640,8 +58,8 @@ #define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) #define STM32_TIM_SETISR(d,hnd,s) ((d)->ops->setisr(d,hnd,s)) #define STM32_TIM_ENABLEINT(d,s,on) ((d)->ops->enableint(d,s,on)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_GETINT(d) ((d)->ops->getint(d)) +#define STM32_TIM_ACKFLAGS(d,s) ((d)->ops->ackflags(d,s)) +#define STM32_TIM_GETFLAGS(d) ((d)->ops->getflags(d)) /************************************************************************************ * Public Types @@ -731,17 +149,17 @@ typedef enum { /* One of the following */ - STM32_CAP_FLAG_IRQ_TIMER = (1<< 0), + STM32_CAP_FLAG_IRQ_TIMER = (GTIM_SR_UIF), - STM32_CAP_FLAG_IRQ_CH_1 = (1<< 1), - STM32_CAP_FLAG_IRQ_CH_2 = (1<< 2), - STM32_CAP_FLAG_IRQ_CH_3 = (1<< 3), - STM32_CAP_FLAG_IRQ_CH_4 = (1<< 4), + STM32_CAP_FLAG_IRQ_CH_1 = (GTIM_SR_CC1IF), + STM32_CAP_FLAG_IRQ_CH_2 = (GTIM_SR_CC2IF), + STM32_CAP_FLAG_IRQ_CH_3 = (GTIM_SR_CC3IF), + STM32_CAP_FLAG_IRQ_CH_4 = (GTIM_SR_CC4IF), - STM32_CAP_FLAG_OF_CH_1 = (1<< 9), - STM32_CAP_FLAG_OF_CH_2 = (1<<10), - STM32_CAP_FLAG_OF_CH_3 = (1<<11), - STM32_CAP_FLAG_OF_CH_4 = (1<<12) + STM32_CAP_FLAG_OF_CH_1 = (GTIM_SR_CC1OF), + STM32_CAP_FLAG_OF_CH_2 = (GTIM_SR_CC2OF), + STM32_CAP_FLAG_OF_CH_3 = (GTIM_SR_CC3OF), + STM32_CAP_FLAG_OF_CH_4 = (GTIM_SR_CC4OF) } stm32_cap_flags_t;