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Add support for RAMTRON NVRAM devices

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3347 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2011-03-06 15:39:02 +00:00
parent e7fd9883f0
commit 3e63074d34
7 changed files with 221 additions and 191 deletions
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arch/arm/src/stm32/chip.h
+9 -9
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@@ -53,7 +53,7 @@
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ # undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */ # define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# define STM32_NATIM 1 /* One advanced timers TIM1 */ # define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 4 /* General timers TIM2,3,4,5 */ # define STM32_NGTIM 4 /* General timers TIM2,3,4,5 */
# define STM32 NBTIM 0 /* No basic timers */ # define STM32 NBTIM 0 /* No basic timers */
# define STM32_NDMA 2 /* DMA1-2 */ # define STM32_NDMA 2 /* DMA1-2 */
@@ -73,19 +73,19 @@
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ # undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */ # define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ # undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# define STM32_NATIM 1 /* One advanced timers TIM1 */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
# define STM32_NGTIM 4 /* General timers TIM2,3,4,5 */ # define STM32_NGTIM 4 /* General timers TIM2,3,4,5 */
# define STM32 NBTIM 0 /* No basic timers */ # define STM32 NBTIM 2 /* Two basic timers TIM6 and TIM7 */
# define STM32_NDMA 2 /* DMA1-2 */ # define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 2 /* SPI1-2 */ # define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NUSART 3 /* USART1-3 */ # define STM32_NUSART 5 /* USART1-5 */
# define STM32_NI2C 2 /* I2C1-2 */ # define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 1 /* bxCAN1 */ # define STM32_NCAN 1 /* bxCAN1 */
# define STM32_NSDIO 1 /* SDIO */ # define STM32_NSDIO 1 /* SDIO */
# define STM32_NGPIO 112 /* GPIOA-G */ # define STM32_NGPIO 51 /* GPIOA-D */
# define STM32_NADC 1 /* ADC1 */ # define STM32_NADC 2 /* ADC1-2 */
# define STM32_NDAC 0 /* No DAC */ # define STM32_NDAC 2 /* DAC1-2 */
# define STM32_NCRC 0 /* No CRC */ # define STM32_NCRC 1 /* CRC */
# define STM32_NTHERNET 0 /* No ethernet */ # define STM32_NTHERNET 0 /* No ethernet */
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC) #elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
arch/arm/src/stm32/stm32_rcc.c
+1 -1
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@@ -210,7 +210,7 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR_SPI2EN; regval |= RCC_APB1ENR_SPI2EN;
#endif #endif
#if CONFIG_STM32_SPI4 #if CONFIG_STM32_SPI3
/* SPI 3 clock enable */ /* SPI 3 clock enable */
regval |= RCC_APB1ENR_SPI3EN; regval |= RCC_APB1ENR_SPI3EN;
arch/arm/src/stm32/stm32_sdio.c
+9 -5
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@@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/stm32/stm32_sdio.c * arch/arm/src/stm32/stm32_sdio.c
* *
* Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -1415,13 +1415,15 @@ static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
clckr = SDIO_CLKCR_MMCXFR; clckr = SDIO_CLKCR_MMCXFR;
break; break;
case CLOCK_SD_TRANSFER_4BIT: /* SD normal operation clocking (wide 4-bit mode) */
#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
clckr = SDIO_CLCKR_SDWIDEXFR;
break;
#endif
case CLOCK_SD_TRANSFER_1BIT: /* SD normal operation clocking (narrow 1-bit mode) */ case CLOCK_SD_TRANSFER_1BIT: /* SD normal operation clocking (narrow 1-bit mode) */
clckr = SDIO_CLCKR_SDXFR; clckr = SDIO_CLCKR_SDXFR;
break; break;
case CLOCK_SD_TRANSFER_4BIT: /* SD normal operation clocking (wide 4-bit mode) */
clckr = SDIO_CLCKR_SDWIDEXFR;
break;
}; };
/* Set the new clock frequency and make sure that the clock is enabled or /* Set the new clock frequency and make sure that the clock is enabled or
@@ -2531,9 +2533,11 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
*/ */
stm32_configgpio(GPIO_SDIO_D0); stm32_configgpio(GPIO_SDIO_D0);
#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
stm32_configgpio(GPIO_SDIO_D1); stm32_configgpio(GPIO_SDIO_D1);
stm32_configgpio(GPIO_SDIO_D2); stm32_configgpio(GPIO_SDIO_D2);
stm32_configgpio(GPIO_SDIO_D3); stm32_configgpio(GPIO_SDIO_D3);
#endif
stm32_configgpio(GPIO_SDIO_CK); stm32_configgpio(GPIO_SDIO_CK);
stm32_configgpio(GPIO_SDIO_CMD); stm32_configgpio(GPIO_SDIO_CMD);
arch/arm/src/stm32/stm32_spi.c
+10 -3
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@@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arm/arm/src/stm32/stm32_spi.c * arm/arm/src/stm32/stm32_spi.c
* *
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -760,6 +760,13 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
uint16_t setbits; uint16_t setbits;
uint32_t actual; uint32_t actual;
/* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */
if (frequency > STM32_SPI_CLK_MAX)
{
frequency = STM32_SPI_CLK_MAX;
}
/* Has the frequency changed? */ /* Has the frequency changed? */
#ifndef CONFIG_SPI_OWNBUS #ifndef CONFIG_SPI_OWNBUS
@@ -1286,7 +1293,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
flags = irqsave(); flags = irqsave();
#ifdef CONFIG_STM32_SPI1 #ifdef CONFIG_STM32_SPI1
if (port == 0) if (port == 1)
{ {
uint32_t mapr; uint32_t mapr;
@@ -1317,7 +1324,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
else else
#endif #endif
#ifdef CONFIG_STM32_SPI2 #ifdef CONFIG_STM32_SPI2
if (port == 1) if (port == 2)
{ {
/* Select SPI2 */ /* Select SPI2 */
arch/arm/src/stm32/stm32_spi.h
+12
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@@ -48,6 +48,8 @@
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
#define STM32_SPI_CLK_MAX 18000000UL /* Maximum allowed speed as per specifications for all SPIs */
/* Register Offsets *****************************************************************/ /* Register Offsets *****************************************************************/
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ #define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
@@ -80,6 +82,16 @@
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET) # define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
#endif #endif
#if STM32_NSPI > 2
# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/ /* Register Bitfield Definitions ****************************************************/
/* SPI Control Register 1 */ /* SPI Control Register 1 */
arch/arm/src/stm32/stm32f103re_pinmap.h
+4 -1
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@@ -284,6 +284,8 @@
/* SDIO */ /* SDIO */
#define GPIO_SDIO_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8) #define GPIO_SDIO_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
# define GPIO_SDIO_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9) # define GPIO_SDIO_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
# define GPIO_SDIO_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10) # define GPIO_SDIO_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
# define GPIO_SDIO_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11) # define GPIO_SDIO_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11)
@@ -291,10 +293,11 @@
# define GPIO_SDIO_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9) # define GPIO_SDIO_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
# define GPIO_SDIO_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6) # define GPIO_SDIO_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
# define GPIO_SDIO_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7) # define GPIO_SDIO_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
#endif
#define GPIO_SDIO_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12) #define GPIO_SDIO_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDIO_CMD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN2) #define GPIO_SDIO_CMD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN2)
/************************************************************************************ /************************************************************************************
* Public Types * Public Types
************************************************************************************/ ************************************************************************************/
arch/arm/src/stm32/stm32f103ze_pinmap.h
+4
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@@ -356,6 +356,8 @@
/* SDIO */ /* SDIO */
#define GPIO_SDIO_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8) #define GPIO_SDIO_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
# define GPIO_SDIO_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9) # define GPIO_SDIO_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
# define GPIO_SDIO_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10) # define GPIO_SDIO_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
# define GPIO_SDIO_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11) # define GPIO_SDIO_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11)
@@ -363,6 +365,8 @@
# define GPIO_SDIO_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9) # define GPIO_SDIO_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
# define GPIO_SDIO_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6) # define GPIO_SDIO_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
# define GPIO_SDIO_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7) # define GPIO_SDIO_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
#endif
#define GPIO_SDIO_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12) #define GPIO_SDIO_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDIO_CMD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN2) #define GPIO_SDIO_CMD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN2)