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esp32[c6|h2|s2|s3]: Assign Edge/Level GPIO pin numbers when in Quadrature Encoder mode

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Only 2 pins are needed in this mode for both channels. The wiring
is such that Edge and Level pins are cross-connected for both
channels.
This commit is contained in:
Martin Vajnar
2025-04-27 16:05:56 +02:00
committed by Alan C. Assis
parent abac610d13
commit 3e100e3c86
5 changed files with 175 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files
boards/xtensa/esp32/common/src/esp32_board_pcnt.c
+35 -3
View File
@@ -193,14 +193,22 @@ int board_pcnt_initialize(void)
};
#ifdef CONFIG_ESP_PCNT_U0
#ifdef CONFIG_ESP_PCNT_U0_QE
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
#else
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_LEVEL_PIN;
#ifdef CONFIG_ESP_PCNT_TEST_MODE
chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
#endif
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
#endif
#ifdef CONFIG_ESP_PCNT_TEST_MODE
chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
#endif
#ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
glitch_threshold = 0;
#else
@@ -229,11 +237,19 @@ int board_pcnt_initialize(void)
#endif
#ifdef CONFIG_ESP_PCNT_U1
#ifdef CONFIG_ESP_PCNT_U1_QE
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
#else
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_EDGE_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
#endif
#ifndef CONFIG_ESP_PCNT_U1_FILTER_EN
glitch_threshold = 0;
#else
@@ -262,11 +278,19 @@ int board_pcnt_initialize(void)
#endif
#ifdef CONFIG_ESP_PCNT_U2
#ifdef CONFIG_ESP_PCNT_U2_QE
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
#else
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_EDGE_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
#endif
#ifndef CONFIG_ESP_PCNT_U2_FILTER_EN
glitch_threshold = 0;
#else
@@ -296,11 +320,19 @@ int board_pcnt_initialize(void)
#endif
#ifdef CONFIG_ESP_PCNT_U3
#ifdef CONFIG_ESP_PCNT_U3_QE
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
#else
chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_LEVEL_PIN;
chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_EDGE_PIN;
chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
#endif
#ifndef CONFIG_ESP_PCNT_U3_FILTER_EN
glitch_threshold = 0;
#else