diff --git a/configs/samv71-xult/README.txt b/configs/samv71-xult/README.txt
index 5d8944a1a50..81b36d3accf 100644
--- a/configs/samv71-xult/README.txt
+++ b/configs/samv71-xult/README.txt
@@ -437,7 +437,40 @@ Configuration sub-directories
        Application Configuration:
          CONFIG_NSH_BUILTIN_APPS=y  : Enable starting apps from NSH command line
 
-    3. The button test at apps/examples/buttons is included in the
+    4. SDRAM is not enabled in this configuration.  I have enabled SDRAM and
+       the apps/examples RAM test using this configuration settings:
+
+       System Type
+         CONFIG_SAMV7_SDRAMC=y
+         CONFIG_SAMV7_SDRAMSIZE=2097152
+
+       Application Configuration:
+         CONFIG_SYSTEM_RAMTEST=y
+
+       The RAM test can be executed as follows:
+
+         nsh> ramtest -w 70000000 209152
+
+       STATUS: As of this writing, SDRAM does not pass the RAM test.  This is the sympton:
+
+        nsh> mw 70000000
+          70000000 = 0x00000000
+        nsh> mw 70000000=55555555
+          70000000 = 0x00000000 -> 0x55555555
+        nsh> mw 70000000
+          70000000 = 0x55555555
+
+        nsh> mw 70100000
+          70100000 = 0x00000000
+        nsh> mw 70100000=aaaaaaaa
+          70100000 = 0x00000000 -> 0xaaaaaaaa
+        nsh> mw 70100000
+          70100000 = 0xaaaaaaaa
+
+        nsh> mw 70000000
+          70000000 = 0x00000000 <<< Lost RAM content
+
+    5. The button test at apps/examples/buttons is included in the
        configuration.  This configuration illustrates (1) use of the buttons
        on the evaluation board, and (2) the use of PIO interrupts.  Example
        usage:
@@ -466,7 +499,7 @@ Configuration sub-directories
          SW1 depressed
        nsh>
 
-    4. TWI/I2C
+    6. TWI/I2C
 
        TWIHS0 is enabled in this configuration.  The SAM V71 Xplained Ultra
        supports two devices on the one on-board I2C device on the TWIHS0 bus:
@@ -544,7 +577,7 @@ Configuration sub-directories
 
        CAREFUL!!! You can trash your MAC address using the I2C tool!
 
-    5. Performance-related Configuration settings:
+    7. Performance-related Configuration settings:
 
        CONFIG_ARMV7M_ICACHE=y                : Instruction cache is enabled
        CONFIG_ARMV7M_DCACHE=y                : Data cache is enabled
diff --git a/configs/samv71-xult/src/sam_sdram.c b/configs/samv71-xult/src/sam_sdram.c
index 0c893136663..3a3d2393d80 100644
--- a/configs/samv71-xult/src/sam_sdram.c
+++ b/configs/samv71-xult/src/sam_sdram.c
@@ -118,27 +118,49 @@ void sam_sdram_config(void)
   sam_configgpio(GPIO_SMC_D14);
   sam_configgpio(GPIO_SMC_D15);
 
-  sam_configgpio(GPIO_SMC_A0);
-  sam_configgpio(GPIO_SMC_A1);
-  sam_configgpio(GPIO_SMC_A2);
-  sam_configgpio(GPIO_SMC_A3);
-  sam_configgpio(GPIO_SMC_A4);
-  sam_configgpio(GPIO_SMC_A5);
-  sam_configgpio(GPIO_SMC_A6);
-  sam_configgpio(GPIO_SMC_A7);
-  sam_configgpio(GPIO_SMC_A8);
-  sam_configgpio(GPIO_SMC_A9);
-  sam_configgpio(GPIO_SDRAMC_A10_1);
+  /*   SAMV71          SDRAM
+   *   --------------- -----------
+   *   PC20 A2         A0
+   *   PC21 A3         A1
+   *   PC22 A4         A2
+   *   PC23 A5         A3
+   *   PC24 A6         A4
+   *   PC25 A7         A5
+   *   PC26 A8         A6
+   *   PC27 A9         A7
+   *   PC28 A10        A8
+   *   PC29 A11        A9
+   *   PD13 SDA10      A10
+   *   PA20 BA0        A11
+   *   PD17 CAS        nCAS
+   *   PD14 SDCKE      CKE
+   *   PD23 SDCK       CLK
+   *   PC15 SDCS       nCS
+   *   PC18 A0/NBS0    LDQM
+   *   PD16 RAS        nRAS
+   *   PD15 NWR1/NBS1  UDQM
+   *   PD29 SDWE       nWE
+   */
 
-  sam_configgpio(GPIO_SDRAMC_CAS);
-  sam_configgpio(GPIO_SDRAMC_RAS);
-  sam_configgpio(GPIO_SDRAMC_CKE);
-  sam_configgpio(GPIO_SDRAMC_CK);
-  sam_configgpio(GPIO_SDRAMC_CS_1);
-  sam_configgpio(GPIO_SMC_NBS0);
-  sam_configgpio(GPIO_SMC_NBS1);
-  sam_configgpio(GPIO_SDRAMC_WE);
-  sam_configgpio(GPIO_SDRAMC_BA0);
+  sam_configgpio(GPIO_SMC_A2);        /* PC20 A2        -> A0 */
+  sam_configgpio(GPIO_SMC_A3);        /* PC21 A3        -> A1 */
+  sam_configgpio(GPIO_SMC_A4);        /* PC22 A4        -> A2 */
+  sam_configgpio(GPIO_SMC_A5);        /* PC23 A5        -> A3 */
+  sam_configgpio(GPIO_SMC_A6);        /* PC24 A6        -> A4 */
+  sam_configgpio(GPIO_SMC_A7);        /* PC25 A7        -> A5 */
+  sam_configgpio(GPIO_SMC_A8);        /* PC26 A8        -> A6 */
+  sam_configgpio(GPIO_SMC_A9);        /* PC27 A9        -> A7 */
+  sam_configgpio(GPIO_SDRAMC_A10_2);  /* PD13 SDA10     -> A10 */
+  sam_configgpio(GPIO_SDRAMC_BA0);    /* PA20 BA0       -> A11 */
+
+  sam_configgpio(GPIO_SDRAMC_CAS);    /* PD17 CAS       -> nCAS */
+  sam_configgpio(GPIO_SDRAMC_CKE);    /* PD14 SDCKE     -> CKE */
+  sam_configgpio(GPIO_SDRAMC_CK);     /* PD23 SDCK      -> CLK */
+  sam_configgpio(GPIO_SDRAMC_CS_1);   /* PC15 SDCS      -> nCS */
+  sam_configgpio(GPIO_SMC_NBS0);      /* PC18 A0/NBS0   -> LDQM */
+  sam_configgpio(GPIO_SDRAMC_RAS);    /* PD16 RAS       -> nRAS */
+  sam_configgpio(GPIO_SMC_NBS1);      /* PD15 NWR1/NBS1 -> UDQM */
+  sam_configgpio(GPIO_SDRAMC_WE);     /* PD29 SDWE      -> nWE */
 
   /* Enable the SDRAMC peripheral */