diff --git a/configs/nucleo-l476rg/include/board.h b/configs/nucleo-l476rg/include/board.h index 184c78d7f56..6e7cb0aefb2 100644 --- a/configs/nucleo-l476rg/include/board.h +++ b/configs/nucleo-l476rg/include/board.h @@ -120,8 +120,8 @@ #define GPIO_USART2_RTS GPIO_USART2_RTS_2 #define GPIO_USART2_CTS GPIO_USART2_CTS_2 -#define GPIO_UART4_RX GPIO_UART4_RX_1 /* PA1 */ -#define GPIO_UART4_TX GPIO_UART4_TX_1 /* PA0 */ +#define GPIO_UART4_RX GPIO_UART4_RX_1 /* PA1 */ +#define GPIO_UART4_TX GPIO_UART4_TX_1 /* PA0 */ /* I2C * @@ -154,13 +154,13 @@ /* SPI */ -#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 -#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 -#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_2 /* PB4 */ +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 /* PB5 */ +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_2 /* PB3 */ -#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 -#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 -#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 +#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */ +#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */ +#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 /* PB13 */ /* LEDs * @@ -266,17 +266,6 @@ extern "C" /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: stm32l4_board_initialize - * - * Description: - * All STM32L4 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32l4_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/configs/nucleo-l476rg/src/Makefile b/configs/nucleo-l476rg/src/Makefile index 61049202bd1..045922dba70 100644 --- a/configs/nucleo-l476rg/src/Makefile +++ b/configs/nucleo-l476rg/src/Makefile @@ -69,6 +69,10 @@ ifeq ($(CONFIG_CAN),y) CSRCS += stm32_can.c endif +ifeq ($(CONFIG_LCD_PCD8544),y) +CSRCS += stm32_pcd8544.c +endif + ifeq ($(CONFIG_SENSORS_QENCODER),y) CSRCS += stm32_qencoder.c endif diff --git a/configs/nucleo-l476rg/src/nucleo-l476rg.h b/configs/nucleo-l476rg/src/nucleo-l476rg.h index 7b91f5ea15d..b798eee9634 100644 --- a/configs/nucleo-l476rg/src/nucleo-l476rg.h +++ b/configs/nucleo-l476rg/src/nucleo-l476rg.h @@ -125,11 +125,11 @@ /* SPI1 off */ #define GPIO_SPI1_MOSI_OFF (GPIO_INPUT | GPIO_PULLDOWN | \ - GPIO_PORTA | GPIO_PIN7) + GPIO_PORTB | GPIO_PIN5) #define GPIO_SPI1_MISO_OFF (GPIO_INPUT | GPIO_PULLDOWN | \ - GPIO_PORTA | GPIO_PIN6) + GPIO_PORTB | GPIO_PIN4) #define GPIO_SPI1_SCK_OFF (GPIO_INPUT | GPIO_PULLDOWN | \ - GPIO_PORTA | GPIO_PIN5) + GPIO_PORTB | GPIO_PIN3) #ifdef CONFIG_WL_CC1101 # define GPIO_CC1101_PWR (GPIO_PORTC | GPIO_PIN6 | GPIO_OUTPUT_SET | \ @@ -155,6 +155,18 @@ GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN5) #endif +#ifdef CONFIG_LCD_PCD8544 + +#define STM32_LCD_CS (GPIO_OUTPUT|GPIO_PULLUP|GPIO_SPEED_2MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN4) + +#define STM32_LCD_CD (GPIO_OUTPUT|GPIO_PULLUP|GPIO_SPEED_2MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN10) + +#define STM32_LCD_RST (GPIO_OUTPUT|GPIO_PULLUP|GPIO_SPEED_2MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN13) +#endif + /* Devices on the onboard bus. * * Note that these are unshifted addresses. diff --git a/configs/nucleo-l476rg/src/stm32_boot.c b/configs/nucleo-l476rg/src/stm32_boot.c index 08bc45ded00..6fbea1751d3 100644 --- a/configs/nucleo-l476rg/src/stm32_boot.c +++ b/configs/nucleo-l476rg/src/stm32_boot.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/nucleo-l476rg/src/stm32l4_boot.c * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * Librae * @@ -51,14 +51,6 @@ #include "up_arch.h" #include "nucleo-l476rg.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Data - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ diff --git a/configs/nucleo-l476rg/src/stm32_pcd8544.c b/configs/nucleo-l476rg/src/stm32_pcd8544.c new file mode 100644 index 00000000000..f0482e42af8 --- /dev/null +++ b/configs/nucleo-l476rg/src/stm32_pcd8544.c @@ -0,0 +1,145 @@ +/**************************************************************************** + * config/nucleo-l476rg/src/stm32_pcd8544.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32l4_gpio.h" +#include "stm32l4_spi.h" +#include "nucleo-l476rg.h" + +#ifdef CONFIG_NX_LCDDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LCD_SPI_PORTNO 1 /* On SPI1 */ + +#ifndef CONFIG_LCD_CONTRAST +# define CONFIG_LCD_CONTRAST 60 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +FAR struct spi_dev_s *g_spidev; +FAR struct lcd_dev_s *g_lcddev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + /* Configure the GPIO pins */ + + stm32l4_configgpio(STM32_LCD_RST); + stm32l4_configgpio(STM32_LCD_CD); + stm32l4_gpiowrite(STM32_LCD_RST, 1); + stm32l4_gpiowrite(STM32_LCD_CD, 1); + + g_spidev = stm32l4_spibus_initialize(LCD_SPI_PORTNO); + + if (!g_spidev) + { + lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); + return -ENODEV; + } + + stm32l4_gpiowrite(STM32_LCD_RST, 0); + up_mdelay(10); + stm32l4_gpiowrite(STM32_LCD_RST, 1); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +FAR struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + g_lcddev = pcd8544_initialize(g_spidev, lcddev); + if (!g_lcddev) + { + lcderr("ERROR: Failed to bind SPI port 1 to LCD %d: %d\n", lcddev); + } + else + { + lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); + + /* And turn the LCD on (CONFIG_LCD_MAXPOWER should be 1) */ + + (void)g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); + + /* Set contrast to right value, otherwise background too dark */ + + (void)g_lcddev->setcontrast(g_lcddev, CONFIG_LCD_CONTRAST); + + return g_lcddev; + } + + return NULL; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} + +#endif /* CONFIG_NX_LCDDRIVER */ diff --git a/configs/nucleo-l476rg/src/stm32_spi.c b/configs/nucleo-l476rg/src/stm32_spi.c index c0ab3d7b3bb..c4c2c4cca73 100644 --- a/configs/nucleo-l476rg/src/stm32_spi.c +++ b/configs/nucleo-l476rg/src/stm32_spi.c @@ -76,8 +76,7 @@ struct spi_dev_s *g_spi2; * Name: stm32l4_spiinitialize * * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and - * Nucleo-F411RE boards. + * Called to configure SPI chip select GPIO pins for the Nucleo-L476RG board. * ************************************************************************************/ @@ -95,6 +94,10 @@ void weak_function stm32l4_spiinitialize(void) #ifdef HAVE_MMCSD stm32l4_configgpio(GPIO_SPI_CS_SD_CARD); #endif + +#ifdef CONFIG_LCD_PCD8544 + (void)stm32l4_configgpio(STM32_LCD_CS); /* PCD8544 chip select */ +#endif #endif #ifdef CONFIG_STM32L4_SPI2 @@ -149,6 +152,13 @@ void stm32l4_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected stm32l4_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif + +#ifdef CONFIG_LCD_PCD8544 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32l4_gpiowrite(STM32_LCD_CS, !selected); + } +#endif } uint8_t stm32l4_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -215,7 +225,20 @@ uint8_t stm32l4_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_STM32L4_SPI1 int stm32l4_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) { - return OK; +#ifdef CONFIG_LCD_PCD8544 + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + (void)stm32l4_gpiowrite(STM32_LCD_CD, !cmd); + + return OK; + } +#endif + + return -ENODEV; } #endif