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Fixed a compile error, presumably caused by C&P error.

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okayserh
2022-04-15 13:06:45 +02:00
committed by Xiang Xiao
parent 6d566e0fda
commit 3a015d56b0
1 changed files with 4 additions and 2 deletions
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arch/arm/src/stm32f7/stm32_ltdc.c
+4 -2
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@@ -1283,9 +1283,11 @@ static void stm32_ltdc_periphconfig(void)
reginfo("configured RCC_PLLSAI=%08x\n", getreg32(STM32_RCC_PLLSAICFGR)); reginfo("configured RCC_PLLSAI=%08x\n", getreg32(STM32_RCC_PLLSAICFGR));
/* Configure dedicated clock external */ /* Configure dedicated clock external.
* Division factor for LCD_CLK in DCKCFGR1
*/
reginfo("configured RCC_DCKCFGR=%08x\n", getreg32(STM32_RCC_DCKCFGR)); reginfo("configured RCC_DCKCFGR1=%08x\n", getreg32(STM32_RCC_DCKCFGR1));
/* Configure LTDC_SSCR */ /* Configure LTDC_SSCR */