Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-05-30 13:27:01 +08:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Finishes the SAMA5D4 XDMAC register definition header file

Browse Source
This commit is contained in:
Gregory Nutt
2014-06-04 16:59:41 -06:00
parent 38900d8ba6
commit 3960271d06
1 changed files with 242 additions and 153 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/sama5/chip/sam_xdmac.h
+143 -54
View File
@@ -157,67 +157,156 @@
/* XDMAC Register Bit Definitions ***************************************************/ /* XDMAC Register Bit Definitions ***************************************************/
/* Global Type Register */ /* Global Type Register */
#define XDMAC_GTYPE_
/* Global Configuration Register */
#define XDMAC_GCFG_
/* Global Weighted Arbiter Configuration Register */
#define XDMAC_GWAC_
/* Global Interrupt Enable Register */
#define XDMAC_GIE_
/* Global Interrupt Disable Register */
#define XDMAC_GID_
/* Global Interrupt Mask Register */
#define XDMAC_GIM_
/* Global Interrupt Status Register */
#define XDMAC_GIS_
/* Global Channel Enable Register */
#define XDMAC_GE_
/* Global Channel Disable Register */
#define XDMAC_GD_
/* Global Channel Status Register */
#define XDMAC_GS_
/* Global Channel Read Suspend Register */
#define XDMAC_GRS_
/* Global Channel Write Suspend Register */
#define XDMAC_GWS_
/* Global Channel Read Write Suspend Register */
#define XDMAC_GRWS_
/* Global Channel Read Write Resume Register */
#define XDMAC_GRWR_
/* Global Channel Software Request Register */
#define XDMAC_GSWR_
/* Global Channel Software Request Status Register */
#define XDMAC_GSWS_
/* Global Channel Software Flush Request Register */
#define XDMAC_GSWF_
/* Channel Interrupt Enable Register */ #define XDMAC_GTYPE_NB_CH_SHIFT (0) /* Bits 0-4: Number of Channels Minus One */
#define XDMACH_CIE_ #define XDMAC_GTYPE_NB_CH_MASK (31 << XDMAC_GTYPE_NB_CH_SHIFT)
/* Channel Interrupt Disable Register */ #define XDMAC_GTYPE_NB_CH(n) ((uint32_t)(n) << XDMAC_GTYPE_NB_CH_SHIFT)
#define XDMACH_CID_ #define XDMAC_GTYPE_FIFO_SZ_SHIFT (5) /* Bits 5-15: Number of Bytes */
/* Channel Interrupt Mask Register */ #define XDMAC_GTYPE_FIFO_SZ_MASK (0x7ff << XDMAC_GTYPE_FIFO_SZ_SHIFT)
#define XDMACH_CIM_ # define XDMAC_GTYPE_FIFO_SZ(n) ((uint32_t)(n) << XDMAC_GTYPE_FIFO_SZ_SHIFT)
/* Channel Interrupt Status Register */ #define XDMAC_GTYPE_NB_REQ_SHIFT (16) /* Bits 16-22: Number of Peripheral Requests Minus One */
#define XDMACH_CIS_ #define XDMAC_GTYPE_NB_REQ_MASK (0x7f << XDMAC_GTYPE_NB_REQ_SHIFT)
/* Channel Source Address Register */ # define XDMAC_GTYPE_NB_REQ(n) ((uint32_t)(n) << XDMAC_GTYPE_NB_REQ_SHIFT)
#define XDMACH_CSA_
/* Channel Destination Address Register */ /* Global Configuration Register */
#define XDMACH_CDA_
/* Channel Next Descriptor Address Register */ #define XDMAC_GCFG_CGDISREG (1 << 0) /* Bit 0: Configuration Registers Clock Gating Disable */
#define XDMACH_CNDA_ #define XDMAC_GCFG_CGDISPIPE (1 << 1) /* Bit 1: Pipeline Clock Gating Disable */
#define XDMAC_GCFG_CGDISFIFO (1 << 2) /* Bit 2: FIFO Clock Gating Disable */
#define XDMAC_GCFG_CGDISIF (1 << 3) /* Bit 3: Bus Interface Clock Gating Disable */
#define XDMAC_GCFG_BXKBEN (1 << 8) /* Bit 8: Boundary X Kilo byte Enable */
/* Global Weighted Arbiter Configuration Register */
#define XDMAC_GWAC_PW0_SHIFT (0) /* Bits 0-3: Pool Weight 0 */
#define XDMAC_GWAC_PW0_MASK (15 << XDMAC_GWAC_PW0_SHIFT)
# define XDMAC_GWAC_PW0(n) ((uint32_t)(n) << XDMAC_GWAC_PW0_SHIFT)
#define XDMAC_GWAC_PW1_SHIFT (4) /* Bits 4-7: Pool Weight 1 */
#define XDMAC_GWAC_PW1_MASK (15 << XDMAC_GWAC_PW1_SHIFT)
# define XDMAC_GWAC_PW1(n) ((uint32_t)(n) << XDMAC_GWAC_PW1_SHIFT)
#define XDMAC_GWAC_PW2_SHIFT (8) /* Bits 8-11: Pool Weight 2 */
#define XDMAC_GWAC_PW2_MASK (15 << XDMAC_GWAC_PW2_SHIFT)
# define XDMAC_GWAC_PW2(n) ((uint32_t)(n) << XDMAC_GWAC_PW2_SHIFT)
#define XDMAC_GWAC_PW3_SHIFT (12) /* Bits 12-15: Pool Weight 3 */
#define XDMAC_GWAC_PW3_MASK (15 << XDMAC_GWAC_PW3_SHIFT)
# define XDMAC_GWAC_PW3(n) ((uint32_t)(n) << XDMAC_GWAC_PW3_SHIFT)
/* All of these registers have the same layout:
*
* - Global Interrupt Enable Register, Global Interrupt Disable Register, Interrupt
* Mask Register, and Global Interrupt Status Register.
*
* - Global Channel Enable Register, Global Channel Disable Register, and Global
* Channel Status Register
*
* - Global Channel Read Suspend Register, Global Channel Write Suspend Register,
* Channel Read Write Suspend Register, and Global Channel Read Write Resume
* Register
*
* - Global Channel Software Request Register, Global Channel Software Request
* Status Register, and Global Channel Software Flush Request Register
*/
#define XDMAC_CHAN(n) (1 << (n))
/* Channel Interrupt Enable Register, Channel Interrupt Disable Register, Channel
* Interrupt Mask Register, and Channel Interrupt Status Register.
*/
#define XDMAC_CHINT_BI (1 << 0) /* Bit 0: End of Block Interrupt */
#define XDMAC_CHINT_LI (1 << 1) /* Bit 1: End of Linked List Interrupt */
#define XDMAC_CHINT_DI (1 << 2) /* Bit 2: End of Disable Interrupt */
#define XDMAC_CHINT_FI (1 << 3) /* Bit 3: End of Flush Interrupt */
#define XDMAC_CHINT_RBI (1 << 4) /* Bit 4: Read Bus Error Interrupt */
#define XDMAC_CHINT_WBI (1 << 5) /* Bit 5: Write Bus Error Interrupt */
#define XDMAC_CHINT_ROI (1 << 6) /* Bit 6: Request Overflow Error Interrupt Disable Bit */
/* Channel Source Address Register (32-bit address) */
/* Channel Destination Address Register (32-bit address) */
/* Channel Next Descriptor Address Register (32-bit address) */
/* Channel Next Descriptor Control Register */ /* Channel Next Descriptor Control Register */
#define XDMACH_CNDC_
#define XDMACH_CNDC_NDE (1 << 0) /* Bit 0: Channel x Next Descriptor Enable */
#define XDMACH_CNDC_NDSUP (1 << 1) /* Bit 1: Channel x Next Descriptor Source Update */
#define XDMACH_CNDC_NDDUP (1 << 2) /* Bit 2: Channel x Next Descriptor Destination Update */
#define XDMACH_CNDC_NDVIEW_SHIFT (3) /* Bits 3-4: Channel x Next Descriptor View */
#define XDMACH_CNDC_NDVIEW_MASK (3 << XDMACH_CNDC_NDVIEW_SHIFT)
# define XDMACH_CNDC_NDVIEW_NDV0 (0 << XDMACH_CNDC_NDVIEW_SHIFT) /* Next Descriptor View 0 */
# define XDMACH_CNDC_NDVIEW_NDV1 (1 << XDMACH_CNDC_NDVIEW_SHIFT) /* Next Descriptor View 1 */
# define XDMACH_CNDC_NDVIEW_NDV2 (2 << XDMACH_CNDC_NDVIEW_SHIFT) /* Next Descriptor View 2 */
# define XDMACH_CNDC_NDVIEW_NDV3 (3 << XDMACH_CNDC_NDVIEW_SHIFT) /* Next Descriptor View 3 */
/* Channel Microblock Control Register */ /* Channel Microblock Control Register */
#define XDMACH_CUBC_
#define XDMACH_CUBC_UBLEN_MASK (0x00ffffff) /* Bits 0-23: Channel x Microblock Length */
/* Channel Block Control Register */ /* Channel Block Control Register */
#define XDMACH_CBC_
#define XDMACH_CBC_BLEN_MASK (0x000000fff) /* Bits 0-11: Channel x Block Length */
/* Channel Configuration Register */ /* Channel Configuration Register */
#define XDMACH_CC_
#define XDMACH_CC_TYPE (1 << 0) /* Bit 0: Channel x Transfer Type */
#define XDMACH_CC_MBSIZE_SHIFT (1) /* Bits 1-2: Channel x Memory Burst Size */
#define XDMACH_CC_MBSIZE_MASK (3 << XDMACH_CC_MBSIZE_SHIFT)
# define XDMACH_CC_MBSIZE_1 (0 << XDMACH_CC_MBSIZE_SHIFT) /* The memory burst size is set to one */
# define XDMACH_CC_MBSIZE_4 (1 << XDMACH_CC_MBSIZE_SHIFT) /* The memory burst size is set to four */
# define XDMACH_CC_MBSIZE_8 (2 << XDMACH_CC_MBSIZE_SHIFT) /* The memory burst size is set to eight */
# define XDMACH_CC_MBSIZE_16 (3 << XDMACH_CC_MBSIZE_SHIFT) /* The memory burst size is set to sixteen */
#define XDMACH_CC_DSYNC (1 << 4) /* Bit 4: Channel x Synchronization */
#define XDMACH_CC_PROT (1 << 5) /* Bit 5: Channel x Protection */
#define XDMACH_CC_SWREQ (1 << 6) /* Bit 6: Channel x Software Request Trigger */
#define XDMACH_CC_MEMSET (1 << 7) /* Bit 7: Channel x Fill Block of memory */
#define XDMACH_CC_CSIZE_SHIFT (8) /* Bits 8-10: Channel x Chunk Size */
#define XDMACH_CC_CSIZE_MASK (7 << XDMACH_CC_CSIZE_SHIFT)
# define XDMACH_CC_CSIZE_1 (0 << XDMACH_CC_CSIZE_SHIFT) /* 1 data transferred */
# define XDMACH_CC_CSIZE_2 (1 << XDMACH_CC_CSIZE_SHIFT) /* 2 data transferred */
# define XDMACH_CC_CSIZE_4 (2 << XDMACH_CC_CSIZE_SHIFT) /* 4 data transferred */
# define XDMACH_CC_CSIZE_8 (3 << XDMACH_CC_CSIZE_SHIFT) /* 8 data transferred */
# define XDMACH_CC_CSIZE_16 (4 << XDMACH_CC_CSIZE_SHIFT) /* 16 data transferred */
#define XDMACH_CC_DWIDTH_SHIFT (11) /* Bits 11-12: Channel x Data Width */
#define XDMACH_CC_DWIDTH_MASK (3 << XDMACH_CC_DWIDTH_SHIFT)
# define XDMACH_CC_DWIDTH_BYTE (0 << XDMACH_CC_DWIDTH_SHIFT) /* The data size is set to 8 bits */
# define XDMACH_CC_DWIDTH_HWORD (1 << XDMACH_CC_DWIDTH_SHIFT) /* The data size is set to 16 bits */
# define XDMACH_CC_DWIDTH_WORD (2 << XDMACH_CC_DWIDTH_SHIFT) /* The data size is set to 32 bits */
# define XDMACH_CC_DWIDTH_DWORD (3 << XDMACH_CC_DWIDTH_SHIFT) /* The data size is set to 64 bits */
#define XDMACH_CC_SIF (1 << 13) /* Bit 13: Channel x Source Interface Identifier */
#define XDMACH_CC_DIF (1 << 14) /* Bit 14: Channel x Destination Interface Identifier */
#define XDMACH_CC_SAM_SHIFT (16) /* Bits 16-17: Channel x Source Addressing Mode */
#define XDMACH_CC_SAM_MASK (3 << XDMACH_CC_SAM_SHIFT)
# define XDMACH_CC_SAM_FIXED (0 << XDMACH_CC_SAM_SHIFT) /* The address remains unchanged */
# define XDMACH_CC_SAM_INCR (1 << XDMACH_CC_SAM_SHIFT) /* Address is incremented */
# define XDMACH_CC_SAM_UBS (2 << XDMACH_CC_SAM_SHIFT) /* Microblock stride is added */
# define XDMACH_CC_SAM_UBSDS (3 << XDMACH_CC_SAM_SHIFT) /* Microblock stride and data stride is added */
#define XDMACH_CC_DAM_SHIFT (18) /* Bits 18-19: Channel x Destination Addressing Mode */
#define XDMACH_CC_DAM_MASK (3 << XDMACH_CC_DAM_SHIFT)
# define XDMACH_CC_DAM_FIXED (0 << XDMACH_CC_DAM_SHIFT) /* The address remains unchanged */
# define XDMACH_CC_DAM_INCR (1 << XDMACH_CC_DAM_SHIFT) /* Address is incremented */
# define XDMACH_CC_DAM_UBS (2 << XDMACH_CC_DAM_SHIFT) /* Microblock stride is added */
# define XDMACH_CC_DAM_UBSDS (3 << XDMACH_CC_DAM_SHIFT) /* Microblock stride and data stride is added */
#define XDMACH_CC_INITD (1 << 21) /* Bit 21: Channel Initialization Terminated */
#define XDMACH_CC_RDIP (1 << 22) /* Bit 22: Read in Progress */
#define XDMACH_CC_WRIP (1 << 23) /* Bit 23: Write in Progress */
#define XDMACH_CC_PERID_SHIFT (24) /* Bits 24-30: Channel x Peripheral Identifier */
#define XDMACH_CC_PERID_MASK (0x7f << XDMACH_CC_PERID_SHIFT)
# define XDMACH_CC_PERID(n) ((uint32_t)(n) << XDMACH_CC_PERID_SHIFT)
/* Channel Data Stride Memory Set Pattern */ /* Channel Data Stride Memory Set Pattern */
#define XDMACH_CDSMSP_
#define XDMACH_CDSMSP_SDS_MSP_SHIFT (0) /* Bits 0-15: Channel x Source Data stride or Memory Set Pattern */
#define XDMACH_CDSMSP_SDS_MSP_MASK (0xffff << XDMACH_CDSMSP_SDS_MSP_SHIFT)
# define XDMACH_CDSMSP_SDS_MSP(n) ((uint32_t)(n) << XDMACH_CDSMSP_SDS_MSP_SHIFT)
#define XDMACH_CDSMSP_DDS_MSP_SHIFT (16) /* Bits 16-31: Channel x Destination Data Stride or Memory Set Pattern */
#define XDMACH_CDSMSP_DDS_MSP_MASK (0xffff << XDMACH_CDSMSP_DDS_MSP_SHIFT)
# define XDMACH_CDSMSP_DDS_MSP(n) ((uint32_t)(n) << XDMACH_CDSMSP_DDS_MSP_SHIFT)
/* Channel Source Microblock Stride */ /* Channel Source Microblock Stride */
#define XDMACH_CSUS_
#define XDMACH_CSUS_SUBS_MASK (0x00ffffff) /* Bits 0-23: Channel x Source Microblock Stride */
/* Channel Destination Microblock Stride */ /* Channel Destination Microblock Stride */
#define XDMACH_CDUS_
#define XDMACH_CDUS_DUBS_MASK (0x00ffffff) /* Bits 0-23: Channel x Destination Microblock Stride */
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_XDMAC_H */ #endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_XDMAC_H */