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STM32 Timer Register Bit Definitions: Some CCER bit settings changed per SourceForge bug #18 submitted by CCCTSAO

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Gregory Nutt
2013-09-02 08:01:09 -06:00
parent 387795ecdf
commit 393b44f059
2 changed files with 6 additions and 4 deletions
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@@ -5487,4 +5487,6 @@
only occur when dual speed support is enabled (2013-9-1).
* arch/arm/src/sama5/sam_clockconfig.c and configs/sama5d3x-ek/include/board_*mhz.h:
Add logic to support UDPHS clocking (2013-9-13).
* arm/src/stm32/chip/stm32_tim.h: Some CCER bit settings changed
per SourceForge bug #18 submitted by CCCTSAO (2013-9-2).