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SAMA5: EHCI now handles low- and full-speed connections by giving them to OHCI; OHCI now uses the work queue to defer interrupt processing; If both OHCI and EHCI are enabled, EHCI is the master of the UHPHS interrupt

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This commit is contained in:
Gregory Nutt
2013-08-24 11:34:24 -06:00
parent cd21e6886e
commit 39052e0ae7
3 changed files with 72 additions and 23 deletions
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configs/sama5d3x-ek/include/board.h
+8 -5
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@@ -51,17 +51,20 @@
* definitions will configure operational clocking.
*/
#ifndef CONFIG_SAMA5_OHCI
#if !defined(CONFIG_SAMA5_OHCI) || defined(CONFIG_SAMA5_EHCI)
/* This is the configuration provided in the Atmel example code. This setup results
* in a CPU clock of 396MHz
* in a CPU clock of 396MHz.
*
* In this configuration, UPLL is the source of the UHPHS clock (if enabled).
*/
# include <arch/board/board_396MHz.h>
#else
/* This is an alternative slower configuration that will produce a 48MHz USB clock
* with the required accuracy. When used with OHCI, an additional requirement is
* the PLLACK be a multiple of 48MHz. This setup results in a CPU clock of 384MHz.
/* OHCI Only. This is an alternative slower configuration that will produce a 48MHz
* USB clock with the required accuracy using only PLLA. When PPLA is used to clock
* OHCI, an additional requirement is the PLLACK be a multiple of 48MHz. This setup
* results in a CPU clock of 384MHz.
*/
# include <arch/board/board_384MHz.h>