arch/tricore: support cache function

Add cache operation support for TriCore architecture including:
- Instruction cache (I-Cache) enable/disable functionality
- Data cache (D-Cache) enable/disable functionality
- Cache configuration and management interfaces
- Performance events integration with cache operations

Signed-off-by: makejian <makejian@xiaomi.com>
Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>

arch/tricore/Kconfig

@@ -45,6 +45,13 @@ config ARCH_CHIP_TC397
 	---help---
 		AURIX TC39x family: TC397
 
+config ARCH_DCACHE_ADDR
+	hex "AURIX Dcache base address"
+	default 0x7003C000
+	---help---
+		AURIX Dcache base address, dcache line clear and invalidate need
+		use the address.
+
 if ARCH_TC3XX
 source "arch/tricore/src/tc3xx/Kconfig"
 endif

arch/tricore/src/common/CMakeLists.txt

@@ -22,6 +22,7 @@
 
 set(SRCS
     tricore_allocateheap.c
+    tricore_cache.c
     tricore_checkstack.c
     tricore_createstack.c
     tricore_csa.c

arch/tricore/src/common/Make.defs

@@ -23,6 +23,7 @@
 HEAD_CSRC += tricore_doirq.c
 
 CMN_CSRCS += tricore_allocateheap.c
+CMN_CSRCS += tricore_cache.c
 CMN_CSRCS += tricore_checkstack.c
 CMN_CSRCS += tricore_createstack.c
 CMN_CSRCS += tricore_csa.c

arch/tricore/src/common/tricore_initialize.c

@@ -26,6 +26,7 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/board.h>
+#include <nuttx/cache.h>
 #include <arch/board/board.h>
 
 #include "tricore_internal.h"
@@ -63,6 +64,14 @@ void up_initialize(void)
 {
   tricore_trapinit();
 
+#ifdef CONFIG_ARCH_ICACHE
+  up_enable_icache();
+#endif
+
+#ifdef CONFIG_ARCH_DCACHE
+  up_enable_dcache();
+#endif
+
   /* Initialize the serial device driver */
 
 #ifdef USE_SERIALDRIVER