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arch: set current regs firstly in undefinedinsn

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Need to save the regs firstly in case syslog triggers another crash.
Otherwise we may loose the register contents for the first exception.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
This commit is contained in:
xuxingliang
2024-07-18 20:36:22 +08:00
committed by Xiang Xiao
parent 35f8b082a7
commit 38858b6cc3
4 changed files with 24 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/arm/arm_undefinedinsn.c
+6 -2
View File
@@ -42,6 +42,12 @@
void arm_undefinedinsn(uint32_t *regs) void arm_undefinedinsn(uint32_t *regs)
{ {
/* Save the saved processor context in current_regs where it can be
* accessed for register dumps and possibly context switching.
*/
up_set_current_regs(regs);
if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext) if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext)
{ {
_alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n", _alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n",
@@ -52,7 +58,5 @@ void arm_undefinedinsn(uint32_t *regs)
_alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
} }
up_set_current_regs(regs);
PANIC_WITH_REGS("panic", regs); PANIC_WITH_REGS("panic", regs);
} }
arch/arm/src/armv7-a/arm_undefinedinsn.c
+6 -2
View File
@@ -42,6 +42,12 @@
uint32_t *arm_undefinedinsn(uint32_t *regs) uint32_t *arm_undefinedinsn(uint32_t *regs)
{ {
/* Save the saved processor context in current_regs where it can be
* accessed for register dumps and possibly context switching.
*/
up_set_current_regs(regs);
if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext) if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext)
{ {
_alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n", _alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n",
@@ -52,8 +58,6 @@ uint32_t *arm_undefinedinsn(uint32_t *regs)
_alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
} }
up_set_current_regs(regs);
PANIC_WITH_REGS("panic", regs); PANIC_WITH_REGS("panic", regs);
return regs; /* To keep the compiler happy */ return regs; /* To keep the compiler happy */
} }
arch/arm/src/armv7-r/arm_undefinedinsn.c
+6 -2
View File
@@ -42,6 +42,12 @@
uint32_t *arm_undefinedinsn(uint32_t *regs) uint32_t *arm_undefinedinsn(uint32_t *regs)
{ {
/* Save the saved processor context in current_regs where it can be
* accessed for register dumps and possibly context switching.
*/
up_set_current_regs(regs);
if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext) if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext)
{ {
_alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n", _alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n",
@@ -52,8 +58,6 @@ uint32_t *arm_undefinedinsn(uint32_t *regs)
_alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
} }
up_set_current_regs(regs);
PANIC_WITH_REGS("panic", regs); PANIC_WITH_REGS("panic", regs);
return regs; /* To keep the compiler happy */ return regs; /* To keep the compiler happy */
} }
arch/arm/src/armv8-r/arm_undefinedinsn.c
+6 -2
View File
@@ -42,6 +42,12 @@
uint32_t *arm_undefinedinsn(uint32_t *regs) uint32_t *arm_undefinedinsn(uint32_t *regs)
{ {
/* Save the saved processor context in current_regs where it can be
* accessed for register dumps and possibly context switching.
*/
up_set_current_regs(regs);
if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext) if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext)
{ {
_alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n", _alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n",
@@ -52,8 +58,6 @@ uint32_t *arm_undefinedinsn(uint32_t *regs)
_alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
} }
up_set_current_regs(regs);
PANIC_WITH_REGS("panic", regs); PANIC_WITH_REGS("panic", regs);
return regs; /* To keep the compiler happy */ return regs; /* To keep the compiler happy */
} }