Completes clock initialization

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2465 42af7a65-404d-4744-a932-0658087f49c3

arch/arm/src/lpc313x/Make.defs

@@ -48,9 +48,9 @@ CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 CGU_ASRCS	= 
 CGU_CSRCS	= lpc313x_bcrndx.c lpc313x_clkdomain.c lpc313x_clkexten.c \
 		  lpc313x_clkfreq.c lpc313x_clkinit.c lpc313x_defclk.c \
-		  lpc313x_esrndx.c lpc313x_fdcndx.c lpc313x_freqin.c \
+		  lpc313x_esrndx.c lpc313x_fdcndx.c lpc313x_fdivinit.c \
-		  lpc313x_pllconfig.c lpc313x_resetclks.c lpc313x_setfreqin.c \
+		  lpc313x_freqin.c lpc313x_pllconfig.c lpc313x_resetclks.c \
-		  lpc313x_softreset.c
+		  lpc313x_setfreqin.c lpc313x_softreset.c
 
 CHIP_ASRCS	= $(CGU_ASRCS)
 CHIP_CSRCS	= lpc313x_allocateheap.c lpc313x_boot.c lpc313x_irq.c \

arch/arm/src/lpc313x/lpc313x_bcrndx.c

@@ -64,26 +64,16 @@
  ************************************************************************/
 
 /************************************************************************
- * Name: lp313x_esrndx
+ * Name: lp313x_bcrndx
  *
  * Description:
- *   Given a clock ID, return the index of the corresponding ESR
+ *   Only 5 of the 12 domains have an associated BCR register.  This
- *   register (or ESRNDX_INVALID if there is no ESR associated with
+ *   function returns the index to the associated BCR register (if any)
- *   this clock ID).  Indexing of ESRs differs slightly from the clock
+ *   or BCRNDX_INVALID otherwise.
- *   ID:  There are 92 clock IDs but only 89 ESR regisers. There are no
- *  ESR registers for :
- *
- *
- *  CLKID_I2SRXBCK0         Clock ID 87: I2SRX_BCK0
- *  CLKID_I2SRXBCK1,        Clock ID 88: I2SRX_BCK1
- *
- * and
- *
- *  CLKID_SYSCLKO           Clock ID 91: SYSCLK_O
  *
  ************************************************************************/
 
-int lp313x_ncrndx(enum lpc313x_domainid_e dmnid)
+int lp313x_bcrndx(enum lpc313x_domainid_e dmnid)
 {
   switch (dmnid)
     {

arch/arm/src/lpc313x/lpc313x_boot.c

@@ -46,6 +46,9 @@
 #include "arm.h"
 #include "up_internal.h"
 #include "up_arch.h"
+
+#include "lpc313x_syscreg.h"
+#include "lpc313x_cgudrvr.h"
 #include "lpc313x_internal.h"
 
 /************************************************************************************
@@ -237,7 +240,24 @@ void up_boot(void)
   up_copyvectorblock();
 #endif /* 0 */
 
-  /* Perform chip common initialization (might do nothing) */
+  /* Reset all clocks */
+
+  lpc313x_resetclks();
+
+  /* Initialize the PLLs */
+
+  lpc313x_hp1pllconfig();
+  lpc313x_hp0pllconfig();
+  
+  /* Initialize clocking to settings provided by board-specific logic */
+
+  lpc313x_clkinit(&g_boardclks);   
+
+  /* Map first 4KB of ARM space to ISRAM area */
+
+  putreg32(LPC313X_INTSRAM0_PSECTION, LPC313X_SYSCREG_ARM926SHADOWPTR);
+
+  /* Perform common, low-level chip initialization (might do nothing) */
 
   lpc313x_lowsetup();
 

arch/arm/src/lpc313x/lpc313x_cgu.h

@@ -1238,6 +1238,9 @@
 #define CGU_FDC17_RESET                  (1 << 1)  /* Bit 1:  Reset fractional divider */
 #define CGU_FDC17_RUN                    (1 << 0)  /* Bit 0:  Enable fractional divider */
 
+#define CGU_FDC_FIELDWIDTH               8         /* MSUB and MADD fields are 8-bits in width */
+#define CGU_FDC17_FIELDWIDTH             13        /* Exept for FDC17 which is 13-bits in width */
+
 /* Dynamic Fractional Divider registers DYNFDC0 to DYNFDC6, addresses 0x13004578 to 0x13004590 */
 
 #define CGU_DYNFDC_STOPAUTORST           (1 << 19) /* Bit 19: Disable auto reset of fractional divider */

arch/arm/src/lpc313x/lpc313x_cgudrvr.h

@@ -528,10 +528,20 @@ struct lpc313x_pllconfig_s
  * Public Data
  ************************************************************************/
 
-/* This array provides the programmed frequency of every input source */
+/* This array is managed by the chip-specific logic and provides the
+ * programmed frequency of every input source
+ */
 
 EXTERN uint32_t g_boardfreqin[CGU_NFREQIN];
 
+/* This instance of the lpc313x_clkinit_s structure provides the initial,
+ * default clock configuration for the board.  Every board must provide
+ * an implementation of g_boardclks.  This rather complex structure is
+ * used by the boot-up logic to configure initial lpc313x clocking.
+ */
+
+EXTERN const struct lpc313x_clkinit_s g_boardclks;
+
 /************************************************************************
  * Inline Functions
  ************************************************************************/

arch/arm/src/lpc313x/lpc313x_fdivinit.c

@@ -0,0 +1,204 @@
+/****************************************************************************
+ * arch/arm/src/lpc313x/lpc313x_fdivinit.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <arch/board/board.h>
+
+#include "lpc313x_cgu.h"
+#include "lpc313x_cgudrvr.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc313x_bitwidth
+ *
+ * Description:
+ *   Find the bit width of a msub or madd value.  This will be use to
+ *   extend the msub or madd values.  To minimize power consumption, the
+ *   lpc313x user manual recommends that madd and msub be shifted right
+ *   to have as many trailing zero's as possible.  This function detmines
+ *   the pre-shifted with of one of the msub or madd values.
+ *
+ * EXAMPLE:
+ *
+ *  Say an input frequency of 13 MHz is given while a frequency of 12
+ *  MHz is required. In this case we want a frequency
+ *
+ *    f’ = 12/13 × f
+ *
+ *  So n = 12 and m = 13. This then gives
+ *
+ *    madd = m - n = 13 - 12 = 1
+ *    msub = -n = -12
+ *
+ * In order to minimize power consumption madd and msub must be as
+ * large as possible. The limit of their values is determined by the
+ * madd/msub bit width. In this case msub is the largest value,
+ * in order to express -12, five bits are required. However since msub is
+ * always negative the fractional divider does not need the sign bit, leaving
+ * 4 bits. If madd/msub bit width has been set to say 8 bits, it is allowed
+ * to shift 4 bits, giving:
+ *
+ *   msub’ = -(12<<4)= -12 × 24 = -12 × 16 = -192
+ *   madd’ = 1<<4 = 24 = 16
+ *
+ ****************************************************************************/
+
+static inline unsigned int
+lpc313x_bitwidth(unsigned int value, unsigned int fdwid)
+{
+  unsigned int width = 0;
+  int bit;
+
+  /* Examine bits from the most significant down */
+
+  for (bit = fdwid-1; bit >= 0; bit--)
+    {
+      /* Is this bit set?  If so, then the width of the value is 0 to bit,
+       * or bit+1.
+       */
+    
+      if ((value & (1 << bit)) != 0)
+        {
+          width = bit + 1;
+          break;
+        }
+    }
+  return width;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+/****************************************************************************
+ * Name: lpc313x_fdivinit
+ *
+ * Description:
+ *   Enable and configure (or disable) a fractional divider.
+ *
+ ****************************************************************************/
+
+uint32_t lpc313x_fdivinit(int fdcndx,
+                          const struct lpc313x_fdivconfig_s *fdiv, bool enable)
+{
+  uint32_t     regaddr;
+  uint32_t     regval;
+  unsigned int fdshift;
+  unsigned int fdwid;
+  unsigned int fdmask;
+  unsigned int maddshift;
+  unsigned int msubshift;
+  int          madd;
+  int          msub;
+
+  /* Calculating the (unshifted) divider values.To minimize power
+   * consumption, the lpc313x user manual recommends that madd and msub
+   * be shifted right to have as many trailing zero's as possible.
+   */
+ 
+  madd = fdiv->m - fdiv->n;
+  msub = -fdiv->n;
+
+  /* Determine the width of the madd and msub fields in the fractional divider
+   * register.  They are all 8-bits in width except for fractional divider 17.
+   */
+
+  fdwid     = CGU_FDC_FIELDWIDTH;
+  maddshift = CGU_FDC_MADD_SHIFT;
+  msubshift = CGU_FDC_MSUB_SHIFT;
+
+  if (fdcndx == 17)
+    {
+      /* For fractional divider 17, the msub/madd field width is 13 */
+
+      fdwid     = CGU_FDC17_FIELDWIDTH;
+      maddshift = CGU_FDC17_MADD_SHIFT;
+      msubshift = CGU_FDC17_MSUB_SHIFT;
+    }
+
+  /* Find maximum bit width of madd & msub.  Here we calculate the width of the OR
+   * of the two values.  The width of the OR will be the width of the wider value 
+   */
+
+  fdshift = fdwid - lpc313x_bitwidth((unsigned int)madd | (unsigned int)fdiv->n, fdwid);
+
+  /* Calculate the fractional divider register values */
+
+  fdmask = (1 << fdwid) - 1;
+  madd   = (madd << fdshift) & fdmask;
+  msub   = (msub << fdshift) & fdmask;
+  regval = (madd << maddshift) | (msub << msubshift);
+  
+  /* Check if 50% duty cycle is needed for this divider */
+
+  if (fdiv->stretch)
+    {
+      regval |= CGU_FDC_STRETCH;
+    }
+
+  /* Check if we should enable the divider immediately */
+
+  if (enable)
+    {
+      regval |= CGU_FDC_RUN;
+    }
+
+  /* Finally configure the divider */
+
+  regaddr = LPC313X_CGU_FDC(fdcndx);
+  putreg32(regval, regaddr);
+  return regval;
+}

configs/ea3131/src/up_clkinit.c

@@ -234,13 +234,16 @@
  * Public Data
  ****************************************************************************/
 
-/* Default clock configuration for the EA3131 board
+/* Default clock configuration for the EA3131 board.  Every board must
+ * provide an implementation of g_boardclks.  This rather complex structure
+ * is used by the boot-up logic to configure initial lpc313x clocking.
  *
- * FFAST:           12MHz
+ *   FFAST:           12MHz
- * MASTER PLL Freq: 180MHz;
+ *   MASTER PLL Freq: 180MHz;
- * AUDIOPLL Freq:   1024Fs, Fs = 44.1kHz
+ *   AUDIOPLL Freq:   1024Fs, Fs = 44.1kHz
  *
  * Domain                   Input             Subdomain         Divider Ratio
+ * ------------------------ ----------------- ----------------- -------------
  * 0 - DOMAIN_SYS           MASTER PLL(HPLL1) DOMAIN0_DIV0      1/2
  *                                            DOMAIN0_DIV1      1
  *                                            DOMAIN0_DIV2      1/2
@@ -281,7 +284,7 @@
  * 11 - DOMAIN_SYSCLKO      FFAST             -                 -
  */
 
-const struct lpc313x_clkinit_s g_cgu_default_clks =
+const struct lpc313x_clkinit_s g_boardclks =
 {
   /* Domain 0 (DOMAINID_SYS), Clocks 0 - 29, Fraction dividers 0-6 */