Updated Nucleo-F401RE configuration

configs/nucleo-f401re/README.txt

@@ -27,14 +27,14 @@ Contents
   - GNU Toolchain Options
   - IDEs
   - NuttX EABI "buildroot" Toolchain
-  - NuttX OABI "buildroot" Toolchain
   - NXFLAT Toolchain
   - Hardware
     - Button
     - LED
-    - USARTS and Serial Consoles
+    - USARTs and Serial Consoles
   - LQFP64
-  - DFU and JTAG
+  - mbed
+  - Shields
   - Configurations
 
 Development Environment
@@ -232,27 +232,7 @@ NuttX EABI "buildroot" Toolchain
   NOTE:  Unfortunately, the 4.6.3 EABI toolchain is not compatible with the
   the NXFLAT tools.  See the top-level TODO file (under "Binary loaders") for
   more information about this problem. If you plan to use NXFLAT, please do not
-  use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain.
+  use the GCC 4.6.3 EABI toolchain; instead use the GCC 4.3.3 EABI toolchain.
-  See instructions below.
-
-NuttX OABI "buildroot" Toolchain
-================================
-
-  The older, OABI buildroot toolchain is also available.  To use the OABI
-  toolchain:
-
-  1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3
-     configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI
-     configuration such as cortexm3-defconfig-4.3.3
-
-  2. Modify the Make.defs file to use the OABI conventions:
-
-    +CROSSDEV = arm-nuttx-elf-
-    +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
-    +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections
-    -CROSSDEV = arm-nuttx-eabi-
-    -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
-    -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
 
 NXFLAT Toolchain
 ================
@@ -287,60 +267,22 @@ NXFLAT Toolchain
   8. Edit setenv.h, if necessary, so that the PATH variable includes
      the path to the newly builtNXFLAT binaries.
 
-DFU and JTAG
+mbed
-============
+====
 
-  Enabling Support for the DFU Bootloader
+  The Nucleo-F401RE includes boot loader from mbed:
-  --------------------------------------
-  The linker files in these projects can be configured to indicate that you
-  will be loading code using STMicro built-in USB Device Firmware Upgrade (DFU)
-  loader or via some JTAG emulator.  You can specify the DFU bootloader by
-  adding the following line:
 
-    CONFIG_STM32_DFU=y
+    https://mbed.org/platforms/ST-Nucleo-F401RE/
+    https://mbed.org/handbook/Homepage
 
-  to your .config file. Most of the configurations in this directory are set
+  Using the mbed loader:
-  up to use the DFU loader.
 
-  If CONFIG_STM32_DFU is defined, the code will not be positioned at the beginning
+  1. Connect the Nucleo-F401RE to the host PC using the USB connector.
-  of FLASH (0x08000000) but will be offset to 0x08005000.  This offset is needed
+  2. A new file system will appear called NUCLEO; open it with Windows
-  to make space for the DFU loader and 0x08005000 is where the DFU loader expects
+     Explorer (assuming that you are using Windows).
-  to find new applications at boot time.  If you need to change that origin for some
+  3. Drag and drop nuttx.bin into the MBED window.  This will load the
-  other bootloader, you will need to edit the file(s) ld.script.dfu for the
+     nuttx.bin binary into the Nucleo-F401RE.  The NUCLEO window will
-  configuration.
+     close then re-open and the Nucleo-F401RE will be running the new code.
-
-  For Linux or Mac:
-  ----------------
-
-  While on Linux or Mac,
-
-  $ lsusb
-  Bus 003 Device 061: ID 0483:374b STMicroelectronics
-
-  $ st-flash write nuttx.bin 0x08000000
-
-  Enabling JTAG
-  -------------
-  If you are not using the DFU, then you will probably also need to enable
-  JTAG support.  By default, all JTAG support is disabled but there NuttX
-  configuration options to enable JTAG in various different ways.
-
-  These configurations effect the setting of the SWJ_CFG[2:0] bits in the AFIO
-  MAPR register.  These bits are used to configure the SWJ and trace alternate function I/Os.
-  The SWJ (SerialWire JTAG) supports JTAG or SWD access to the Cortex debug port.
-  The default state in this port is for all JTAG support to be disable.
-
-  CONFIG_STM32_JTAG_FULL_ENABLE - sets SWJ_CFG[2:0] to 000 which enables full
-    SWJ (JTAG-DP + SW-DP)
-
-  CONFIG_STM32_JTAG_NOJNTRST_ENABLE - sets SWJ_CFG[2:0] to 001 which enable
-    full SWJ (JTAG-DP + SW-DP) but without JNTRST.
-
-  CONFIG_STM32_JTAG_SW_ENABLE - sets SWJ_CFG[2:0] to 010 which would set JTAG-DP
-    disabled and SW-DP enabled
-
-  The default setting (none of the above defined) is SWJ_CFG[2:0] set to 100
-  which disable JTAG-DP and SW-DP.
 
 Hardware
 ========
@@ -399,16 +341,44 @@ Hardware
 Serial Consoles
 ===============
 
+  USART1
+  ------
+    RXD: PA11  CN10 pin 14
+         PB7   CN7 pin 21
+    TXD: PA10  CN9 pin 3, CN10 pin 33
+         PB6   CN5 pin 3, CN10 pin 17
+
   USART2
   -----
-  If you have a 3.3 V TTL to RS-232 convertor then this is the most convenient
+    RXD: PA3   CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37
+         PD6
+    TXD: PA2   CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35
+         PD5
+
+  If you have a 3.3 V TTL to RS-232 converter then this is the most convenient
   serial console to use.  UART2 is the default in all of these
   configurations.
 
-    USART2 RX  PA3   JP1 pin 4
+       Nucleo CN9  STM32F401RE
-    USART2 TX  PA2   JP1 pin 3
+       ----------- ------------
-    GND              JP1 pin 2
+       Pin 1  PA3  USART2_RX
-    V3.3             JP2 pin 1
+       Pin 2  PA2  USART2_TX
+
+  Solder Bridges.  This configuration requires:
+
+  - SB62 and SB63 Closed: PA2 and PA3 on STM32 MCU are connected to D1 and D0
+    (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho connector CN10
+    as USART signals.  Thus SB13 and SB14 should be OFF.
+
+  - SB13 and SB14 Open:  PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+    disconnected to PA3 and PA2 on STM32 MCU.
+
+  USART6
+  ------
+   RXD: PC7    CN5 pin2, CN10 pin 19
+        PA12   CN10, pin 12
+   TXD: PC6    CN10, pin 4
+        PA11   CN10, pin 14
 
   Virtual COM Port
   ----------------
@@ -416,6 +386,49 @@ Serial Consoles
   option may be more convenient for long term development, but was
   painful to use during board bring-up.
 
+  Solder Bridges.  This configuration requires:
+
+  - SB62 and SB63 Open: PA2 and PA3 on STM32 MCU are disconnected to D1
+    and D0 (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho
+    connector CN10.
+
+  - SB13 and SB14 Closed:  PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+    connected to PA3 and PA2 on STM32 MCU to have USART communication
+    between them. Thus SB61,SB62 and SB63 should be OFF.
+
+  Default
+  -------
+  As shipped, SB62 and SB63 are open and SB13 and SB14 closed, so the
+  virtual COM port is enabled.
+
+Shields
+=======
+
+  1. RS-232 from Cutedigi.com.  Supports a single RS-232 connected via
+
+       Nucleo CN9  STM32F401RE  Cutedigi
+       ----------- ------------ --------
+       Pin 1  PA3  USART2_RX    RXD
+       Pin 2  PA2  USART2_TX    TXD
+
+     Support for this shield is enabled by selecting:
+
+       CONFIG_STM32_USART2=y
+       CONFIG_USART2_ISUART=y
+       CONFIG_USART2_SERIAL_CONSOLE=y
+       CONFIG_USART2_RXBUFSIZE=256
+       CONFIG_USART2_TXBUFSIZE=256
+       CONFIG_USART2_BAUD=115200
+       CONFIG_USART2_BITS=8
+       CONFIG_USART2_PARITY=0
+       CONFIG_USART2_2STOP=0
+
+  2. CC3000 Wireless shield
+
+     Support this shield is enabled by configuring the CC3000 networking:
+
+       CONFIG_WL_CC3000
+
 Configurations
 ==============
 

configs/nucleo-f401re/include/board.h

@@ -194,7 +194,8 @@
 
 #define DMAMAP_SDIO DMAMAP_SDIO_1
 
-// need to VERIFY fwb
+/* Need to VERIFY fwb */
+
 #define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1
 #define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1
 #define DMACHAN_SPI2_RX DMAMAP_SPI2_RX
@@ -202,29 +203,37 @@
 
 /* Alternate function pin selections ************************************************/
 
-/* UARTs */
+/* USART1:
+ *   RXD: PA11  CN10 pin 14
+ *        PB7   CN7 pin 21
+ *   TXD: PA10  CN9 pin 3, CN10 pin 33
+ *        PB6   CN5 pin 3, CN10 pin 17
+ */
 
-#define GPIO_USART1_RX   GPIO_USART1_RX_1    /* PA_10 */
+#define GPIO_USART1_RX   GPIO_USART1_RX_1    /* PA10 */
-#define GPIO_USART1_TX   GPIO_USART1_TX_2    /* PB_6  */
+#define GPIO_USART1_TX   GPIO_USART1_TX_2    /* PA9  */
 
-#define GPIO_USART2_RX   GPIO_USART2_RX_1    /* PA_3 */
+/* USART2:
-#define GPIO_USART2_TX   GPIO_USART2_TX_1    /* PA_2 */
+ *   RXD: PA3   CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37
+ *        PD6
+ *   TXD: PA2   CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35
+ *        PD5
+ */
+
+#define GPIO_USART2_RX   GPIO_USART2_RX_1    /* PA3 */
+#define GPIO_USART2_TX   GPIO_USART2_TX_1    /* PA2 */
 #define GPIO_USART2_RTS  GPIO_USART2_RTS_2
 #define GPIO_USART2_CTS  GPIO_USART2_CTS_2
 
-#define GPIO_USART3_RX   GPIO_USART3_RX_3
+/* USART6:
-#define GPIO_USART3_TX   GPIO_USART3_TX_3
+ *  RXD: PC7    CN5 pin2, CN10 pin 19
-#define GPIO_USART2_RTS  GPIO_USART2_RTS_2
+ *       PA12   CN10, pin 12
-#define GPIO_USART2_CTS  GPIO_USART2_CTS_2
+ *  TXD: PC6    CN10, pin 4
+ *       PA11   CN10, pin 14
+ */
 
-#define GPIO_UART4_RX    GPIO_UART4_RX_1
+#define GPIO_USART6_RX   GPIO_USART6_RX_1    /* PC7 */
-#define GPIO_UART4_TX    GPIO_UART4_TX_1
+#define GPIO_USART6_TX   GPIO_USART6_TX_1    /* PC6 */
-
-#define GPIO_USART6_RX   GPIO_USART6_RX_1
-#define GPIO_USART6_TX   GPIO_USART6_TX_1
-
-#define GPIO_UART7_RX    GPIO_UART7_RX_1
-#define GPIO_UART7_TX    GPIO_UART7_TX_1
 
 /* UART8 has no alternate pin config */
 

configs/nucleo-f401re/nsh/setenv.sh

@@ -58,6 +58,6 @@ export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_Code
 #export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
 
 # Add the path to the toolchain to the PATH varialble
-export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+#export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
 
 echo "PATH : ${PATH}"

configs/nucleo-f401re/src/Makefile

@@ -42,6 +42,10 @@ AOBJS = $(ASRCS:.S=$(OBJEXT))
 
 CSRCS = stm32_boot.c stm32_spi.c
 
+ifeq ($(CONFIG_HAVE_CXX),y)
+CSRCS += stm32_cxxinitialize.c
+endif
+
 ifeq ($(CONFIG_ARCH_LEDS),y)
 CSRCS += stm32_autoleds.c
 else
@@ -54,16 +58,15 @@ endif
 
 ifeq ($(CONFIG_WL_CC3000),y)
 CSRCS += stm32_wireless.c
+ifeq ($(CONFIG_CC3000_PROBES),)
+CSRCS += stm32_io.c
+endif
 endif
 
 ifeq ($(CONFIG_NSH_LIBRARY),y)
 CSRCS += stm32_nsh.c
 endif
 
-ifeq ($(CONFIG_CC3000_PROBES),)
-CSRCS += stm32_io.c
-endif
-
 COBJS = $(CSRCS:.c=$(OBJEXT))
 
 SRCS = $(ASRCS) $(CSRCS)

configs/nucleo-f401re/src/nucleo-f401re.h

@@ -1,6 +1,37 @@
 /************************************************************************************
  * configs/nucleo-f401re/src/nucleo-f401re.h
  *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Authors: Frank Bennett
+ *            Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
  ************************************************************************************/
 
 #ifndef __CONFIGS_NUCLEO_F401RE_SRC_NUCLEO_F401RE_H
@@ -14,6 +45,16 @@
 #include <nuttx/compiler.h>
 #include <stdint.h>
 
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+
+#define HAVE_MMCSD 1
+#if !defined(CONFIG_STM32_SDIO) || !defined(CONFIG_MMCSD) || !defined(CONFIG_MMCSD_SDIO)
+#  undef HAVE_MMCSD
+#endif
+
 /* LED.  User LD2: the green LED is a user LED connected to Arduino signal D13
  * corresponding to MCU I/O PA5 (pin 21) or PB13 (pin 34) depending on the STM32
  * target.
@@ -22,7 +63,9 @@
  * - When the I/O is LOW, the LED is off.
  */
 
-#define GPIO_LD2      (GPIO_PORTA | GPIO_PIN5 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
+#define GPIO_LD2 \
+  (GPIO_PORTA | GPIO_PIN5 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \
+   GPIO_SPEED_50MHz)
 
 /* Buttons
  *
@@ -34,7 +77,8 @@
 #define MAX_IRQBUTTON   BUTTON_USER
 #define NUM_IRQBUTTONS  1
 
-#define GPIO_BTN_USER   (GPIO_INPUT |GPIO_FLOAT |GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
+#define GPIO_BTN_USER \
+  (GPIO_INPUT |GPIO_FLOAT |GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
 
 /* The shield uses the following pins:
  *
@@ -57,10 +101,10 @@
  *
  */
 
-#define GPIO_WIFI_INT (GPIO_PORTB | GPIO_PIN3  | GPIO_INPUT        | GPIO_PULLUP | GPIO_EXTI)
+#ifdef CONFIG_WL_CC3000
-#define GPIO_WIFI_EN  (GPIO_PORTB | GPIO_PIN4  | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
+#  define GPIO_WIFI_INT (GPIO_PORTB | GPIO_PIN3  | GPIO_INPUT        | GPIO_PULLUP | GPIO_EXTI)
-#define GPIO_WIFI_CS  (GPIO_PORTB | GPIO_PIN6  | GPIO_OUTPUT_SET   | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
+#  define GPIO_WIFI_EN  (GPIO_PORTB | GPIO_PIN4  | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
-
+#  define GPIO_WIFI_CS  (GPIO_PORTB | GPIO_PIN6  | GPIO_OUTPUT_SET   | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
 #  define GPIO_D14    (GPIO_PORTB | GPIO_PIN9  | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
 #  define GPIO_D15    (GPIO_PORTB | GPIO_PIN8  | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
 #  define GPIO_D0     (GPIO_PORTA | GPIO_PIN3  | GPIO_INPUT        | GPIO_PULLUP )
@@ -71,6 +115,7 @@
 #  define GPIO_A1     (GPIO_PORTA | GPIO_PIN1  | GPIO_OUTPUT_SET   | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SPEED_50MHz)
 #  define GPIO_A2     (GPIO_PORTA | GPIO_PIN4  | GPIO_INPUT        | GPIO_PULLUP )
 #  define GPIO_A3     (GPIO_PORTB | GPIO_PIN0  | GPIO_INPUT        | GPIO_PULLUP )
+#endif
 
 /* SPI1 off */
 
@@ -80,17 +125,27 @@
 
 /* SPI1 chip selects off */
 
-#define GPIO_SPI_CS_WIFI_OFF \
+#ifdef CONFIG_WL_CC3000
+#  define GPIO_SPI_CS_WIFI_OFF \
     (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTB|GPIO_PIN6)
-#define GPIO_SPI_CS_SD_CARD_OFF \
+#endif
+
+#ifdef HAVE_MMCSD
+#  define GPIO_SPI_CS_SD_CARD_OFF \
     (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz|GPIO_PORTB|GPIO_PIN5)
+#endif
 
 /* SPI chip selects */
 
-#define GPIO_SPI_CS_WIFI \
+#ifdef CONFIG_WL_CC3000
+#  define GPIO_SPI_CS_WIFI \
     (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN6)
-#define GPIO_SPI_CS_SD_CARD \
+#endif
+
+#ifdef HAVE_MMCSD
+#  define GPIO_SPI_CS_SD_CARD \
     (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN5)
+#endif
 
 /* Devices on the onboard bus.
  *
@@ -105,12 +160,32 @@
  * GPIO0-1 are for probing WIFI status
  */
 
-#define GPIO_GPIO0_INPUT        (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN8)
+#ifdef CONFIG_WL_CC3000
-#define GPIO_GPIO1_INPUT        (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN9)
+#  define GPIO_GPIO0_INPUT \
-#define GPIO_GPIO0_OUTPUT \
+    (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN8)
+#  define GPIO_GPIO1_INPUT \
+    (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN9)
+#  define GPIO_GPIO0_OUTPUT \
     (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8)
-#define GPIO_GPIO1_OUTPUT \
+#  define GPIO_GPIO1_OUTPUT \
     (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9)
+#endif
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/* Global driver instances */
+
+#ifdef CONFIG_STM32_SPI1
+extern struct spi_dev_s *g_spi1;
+#endif
+#ifdef CONFIG_STM32_SPI2
+extern struct spi_dev_s *g_spi2;
+#endif
+#ifdef HAVE_MMCSD
+extern struct sdio_dev_s *g_sdio;
+#endif
 
 /************************************************************************************
  * Public Functions

configs/nucleo-f401re/src/stm32_cxxinitialize.c

@@ -0,0 +1,154 @@
+/************************************************************************************
+ * configs/nucleo-f401re/src/stm32_cxxinitialize.c
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include <nuttx/arch.h>
+
+#include <arch/stm32/chip.h>
+#include "chip.h"
+
+#if defined(CONFIG_HAVE_CXX) && defined(CONFIG_HAVE_CXXINITIALIZE)
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+/* Debug ****************************************************************************/
+/* Non-standard debug that may be enabled just for testing the static constructors */
+
+#ifndef CONFIG_DEBUG
+#  undef CONFIG_DEBUG_CXX
+#endif
+
+#ifdef CONFIG_DEBUG_CXX
+#  define cxxdbg              dbg
+#  define cxxlldbg            lldbg
+#  ifdef CONFIG_DEBUG_VERBOSE
+#    define cxxvdbg           vdbg
+#    define cxxllvdbg         llvdbg
+#  else
+#    define cxxvdbg(x...)
+#    define cxxllvdbg(x...)
+#  endif
+#else
+#  define cxxdbg(x...)
+#  define cxxlldbg(x...)
+#  define cxxvdbg(x...)
+#  define cxxllvdbg(x...)
+#endif
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+/* This type defines one entry in initialization array */
+
+typedef void (*initializer_t)(void);
+
+/************************************************************************************
+ * External references
+ ************************************************************************************/
+/* _sinit and _einit are symbols exported by the linker script that mark the
+ * beginning and the end of the C++ initialization section.
+ */
+
+extern initializer_t _sinit;
+extern initializer_t _einit;
+
+/* _stext and _etext are symbols exported by the linker script that mark the
+ * beginning and the end of text.
+ */
+
+extern uint32_t _stext;
+extern uint32_t _etext;
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: up_cxxinitialize
+ *
+ * Description:
+ *   If C++ and C++ static constructors are supported, then this function
+ *   must be provided by board-specific logic in order to perform
+ *   initialization of the static C++ class instances.
+ *
+ *   This function should then be called in the application-specific
+ *   user_start logic in order to perform the C++ initialization.  NOTE
+ *   that no component of the core NuttX RTOS logic is involved; This
+ *   function defintion only provides the 'contract' between application
+ *   specific C++ code and platform-specific toolchain support
+ *
+ ***************************************************************************/
+
+void up_cxxinitialize(void)
+{
+  initializer_t *initp;
+
+  cxxdbg("_sinit: %p _einit: %p _stext: %p _etext: %p\n",
+         &_sinit, &_einit, &_stext, &_etext);
+
+  /* Visit each entry in the initialzation table */
+
+  for (initp = &_sinit; initp != &_einit; initp++)
+    {
+      initializer_t initializer = *initp;
+      cxxdbg("initp: %p initializer: %p\n", initp, initializer);
+
+      /* Make sure that the address is non-NULL and lies in the text region
+       * defined by the linker script.  Some toolchains may put NULL values
+       * or counts in the initialization table
+       */
+
+      if ((void*)initializer > (void*)&_stext && (void*)initializer < (void*)&_etext)
+        {
+          cxxdbg("Calling %p\n", initializer);
+          initializer();
+        }
+    }
+}
+
+#endif /* CONFIG_HAVE_CXX && CONFIG_HAVE_CXXINITIALIZE */
+

configs/nucleo-f401re/src/stm32_nsh.c

@@ -39,35 +39,26 @@
 
 #include <nuttx/config.h>
 
-#include <stdbool.h>
 #include <stdio.h>
-#include <math.h>
 #include <debug.h>
 #include <errno.h>
 
 #include <nuttx/arch.h>
-#include <nuttx/spi/spi.h>
 #include <nuttx/sdio.h>
 #include <nuttx/mmcsd.h>
-#include <nuttx/gran.h>
 
 #include <stm32.h>
 #include <stm32_uart.h>
 
 #include <arch/board/board.h>
 
+#include "nucleo-f401re.h"
+
 /****************************************************************************
  * Pre-Processor Definitions
  ****************************************************************************/
-
 /* Configuration ************************************************************/
 
-#ifdef CONFIG_FAT_DMAMEMORY
-#  if !defined(CONFIG_GRAN) || !defined(CONFIG_FAT_DMAMEMORY)
-#    error microSD DMA support requires CONFIG_GRAN
-#  endif
-#endif
-
 /* Debug ********************************************************************/
 
 #ifdef CONFIG_CPP_HAVE_VARARGS
@@ -88,47 +79,10 @@
  * Private Data
  ****************************************************************************/
 
-#ifdef CONFIG_FAT_DMAMEMORY
-static GRAN_HANDLE dma_allocator;
-
-/* The DMA heap size constrains the total number of things that can be
- * ready to do DMA at a time.
- *
- * For example, FAT DMA depends on one sector-sized buffer per file system plus
- * one sector-sized buffer per file.
- *
- * We use a fundamental alignment / granule size of 64B; this is sufficient
- * to guarantee alignment for the largest STM32 DMA burst (16 beats x 32bits).
- */
-
-static uint8_t g_dma_heap[8192] __attribute__((aligned(64)));
-#endif
-
-static struct spi_dev_s *spi1;
-static struct sdio_dev_s *sdio;
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
 
-#ifdef CONFIG_FAT_DMAMEMORY
-static void dma_alloc_init(void)
-{
-  dma_allocator =
-    gran_initialize(g_dma_heap,
-                    sizeof(g_dma_heap),
-                    7,  /* 128B granule - must be > alignment (XXX bug?) */
-                    6); /* 64B alignment */
-
-  if (dma_allocator == NULL)
-    {
-      message("[boot] DMA allocator setup FAILED");
-    }
-}
-#else
-# define dma_alloc_init()
-#endif
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -141,9 +95,11 @@ static void dma_alloc_init(void)
  *
  ****************************************************************************/
 
+#ifdef CONFIG_WL_CC3000
 void up_netinitialize(void)
 {
 }
+#endif
 
 /****************************************************************************
  * Name: nsh_archinitialize
@@ -155,7 +111,7 @@ void up_netinitialize(void)
 
 int nsh_archinitialize(void)
 {
-#ifdef CONFIG_MMCSD
+#ifdef HAVE_MMCSD
   int ret;
 #endif
 
@@ -165,20 +121,11 @@ int nsh_archinitialize(void)
   cpuload_initialize_once();
 #endif
 
-  /* Configure SPI-based devices */
+#ifdef HAVE_MMCSD
-
-  spi1 = up_spiinitialize(1);
-  if (!spi1)
-    {
-      message("[boot] FAILED to initialize SPI port 1\n");
-      return -ENODEV;
-    }
-
-#ifdef CONFIG_MMCSD
   /* First, get an instance of the SDIO interface */
 
-  sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO);
+  g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO);
-  if (!sdio)
+  if (!g_sdio)
     {
       message("[boot] Failed to initialize SDIO slot %d\n",
               CONFIG_NSH_MMCSDSLOTNO);
@@ -187,7 +134,7 @@ int nsh_archinitialize(void)
 
   /* Now bind the SDIO interface to the MMC/SD driver */
 
-  ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio);
+  ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio);
   if (ret != OK)
     {
       message("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
@@ -198,7 +145,7 @@ int nsh_archinitialize(void)
    * card detect GPIO.
    */
 
-  sdio_mediachange(sdio, true);
+  sdio_mediachange(g_sdio, true);
 
   message("[boot] Initialized SDIO\n");
 #endif

configs/nucleo-f401re/src/stm32_spi.c

@@ -77,6 +77,18 @@
 #  define spivdbg(x...)
 #endif
 
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+/* Global driver instances */
+
+#ifdef CONFIG_STM32_SPI1
+struct spi_dev_s *g_spi1;
+#endif
+#ifdef CONFIG_STM32_SPI2
+struct spi_dev_s *g_spi2;
+#endif
+
 /************************************************************************************
  * Public Functions
  ************************************************************************************/
@@ -92,11 +104,29 @@
 void weak_function stm32_spiinitialize(void)
 {
 #ifdef CONFIG_STM32_SPI1
+  /* Configure SPI-based devices */
+
+  g_spi1 = up_spiinitialize(1);
+  if (!g_spi1)
+    {
+      message("[boot] FAILED to initialize SPI port 1\n");
+      return -ENODEV;
+    }
+
+#ifdef CONFIG_WL_CC3000
   stm32_configgpio(GPIO_SPI_CS_WIFI);
+#endif
+
+#ifdef HAVE_MMCSD
   stm32_configgpio(GPIO_SPI_CS_SD_CARD);
 #endif
+#endif
 
 #ifdef CONFIG_STM32_SPI2
+  /* Configure SPI-based devices */
+
+  g_spi2 = up_spiinitialize(2);
+
   /* Setup CS, EN & IRQ line IOs */
 
 #ifdef CONFIG_WL_CC3000
@@ -137,22 +167,19 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sele
 {
   spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 
-  switch (devid)
+#ifdef CONFIG_WL_CC3000
+  if (devid == SPIDEV_WIRELESS)
     {
-    case SPIDEV_WIRELESS:
-      /* Making sure the other peripherals are not selected */
-
       stm32_gpiowrite(GPIO_SPI_CS_WIFI, !selected);
-      stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, true);
-      break;
-
-    case SPIDEV_MMCSD:
-      /* Making sure the other peripherals are not selected */
-
-      stm32_gpiowrite(GPIO_SPI_CS_WIFI, true);
-      stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected);
-      break;
     }
+  else
+#endif
+#ifdef HAVE_MMCSD
+  if (devid == SPIDEV_MMCSD)
+    {
+      stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected);
+    }
+#endif
 }
 
 uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
@@ -166,7 +193,7 @@ void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sele
 {
   spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 
-#if defined(CONFIG_WL_CC3000)
+#ifdef CONFIG_WL_CC3000
   if (devid == SPIDEV_WIRELESS)
     {
       stm32_gpiowrite(GPIO_WIFI_CS, !selected);