From 35f830b19a6aa89db65329eaf96eba7c73c36b66 Mon Sep 17 00:00:00 2001 From: Lucas Saavedra Vaz Date: Tue, 7 Mar 2023 21:58:05 -0300 Subject: [PATCH] boards: Add CoreMark config to ESP boards --- .../esp32c3-devkit/configs/coremark/defconfig | 33 +++++++++++++++ .../esp32-devkitc/configs/coremark/defconfig | 29 +++----------- .../configs/coremark/defconfig | 37 +++++++++++++++++ .../esp32s3-devkit/configs/coremark/defconfig | 40 +++++++++++++++++++ 4 files changed, 116 insertions(+), 23 deletions(-) create mode 100644 boards/risc-v/esp32c3/esp32c3-devkit/configs/coremark/defconfig create mode 100644 boards/xtensa/esp32s2/esp32s2-saola-1/configs/coremark/defconfig create mode 100644 boards/xtensa/esp32s3/esp32s3-devkit/configs/coremark/defconfig diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/coremark/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/coremark/defconfig new file mode 100644 index 00000000000..bddc8c8a837 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/coremark/defconfig @@ -0,0 +1,33 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_BENCHMARK_COREMARK=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_OPTLEVEL="-O3" +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="coremark_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/coremark/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/coremark/defconfig index 0baef39026f..b642f9895d2 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/coremark/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/coremark/defconfig @@ -6,8 +6,7 @@ # modifications. # # CONFIG_ARCH_LEDS is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NDEBUG is not set CONFIG_ARCH="xtensa" CONFIG_ARCH_BOARD="esp32-devkitc" CONFIG_ARCH_BOARD_COMMON=y @@ -21,39 +20,23 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BENCHMARK_COREMARK=y CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_OPTLEVEL="-O3" CONFIG_ESP32_UART0=y -CONFIG_EXAMPLES_HELLO=y CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 -CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_ENTRYPOINT="coremark_main" CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=4 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_READLINE=y +CONFIG_MM_REGIONS=3 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 -CONFIG_READLINE_CMD_HISTORY=y CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y CONFIG_SMP=y CONFIG_SMP_NCPUS=2 -CONFIG_SPI=y -CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_SYSTEM=y -CONFIG_SYSTEM_TASKSET=y -CONFIG_TESTING_OSTEST=y -CONFIG_TESTING_SMP=y CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/coremark/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/coremark/defconfig new file mode 100644 index 00000000000..905648cbaef --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/coremark/defconfig @@ -0,0 +1,37 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NDEBUG is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32s2-saola-1" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y +CONFIG_ARCH_CHIP="esp32s2" +CONFIG_ARCH_CHIP_ESP32S2=y +CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_SETJMP_H=y +CONFIG_ARCH_XTENSA=y +CONFIG_BENCHMARK_COREMARK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_OPTLEVEL="-O3" +CONFIG_ESP32S2_UART0=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="coremark_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/coremark/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/coremark/defconfig new file mode 100644 index 00000000000..907f398bd40 --- /dev/null +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/coremark/defconfig @@ -0,0 +1,40 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NDEBUG is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32s3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32s3" +CONFIG_ARCH_CHIP_ESP32S3=y +CONFIG_ARCH_CHIP_ESP32S3WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_SETJMP_H=y +CONFIG_ARCH_XTENSA=y +CONFIG_BENCHMARK_COREMARK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_OPTLEVEL="-O3" +CONFIG_ESP32S3_UART0=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="coremark_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SMP=y +CONFIG_SMP_NCPUS=2 +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_UART0_SERIAL_CONSOLE=y