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Nucleo-F401RE: With these changes and the changes from previous commits, the basic Nucleo-F401RE NSH configuration is working.
This commit is contained in:
Gregory Nutt
@@ -342,6 +342,18 @@ Serial Consoles
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TXD: PA10 CN9 pin 3, CN10 pin 33
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PB6 CN5 pin 3, CN10 pin 17
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NOTE: You may need to edit the include/board.h to select different USART1
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pin selections.
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TTL to RS-232 converter connection:
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Nucleo CN10 STM32F401RE
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----------- ------------
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Pin 21 PA9 USART2_RX
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Pin 33 PA10 USART2_TX
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Pin 20 GND
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Pin 8 U5V
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To configure USART1 as the console:
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CONFIG_STM32_USART1=y
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@@ -363,9 +375,9 @@ Serial Consoles
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TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35
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PD5
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If you have a 3.3 V TTL to RS-232 converter then this is the most convenient
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serial console to use. UART2 is the default in all of these
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configurations.
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UART2 is the default in all of these configurations.
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TTL to RS-232 converter connection:
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Nucleo CN9 STM32F401RE
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----------- ------------
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@@ -462,8 +474,46 @@ Shields
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Configurations
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==============
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Composite: The composite is a super set of all the functions in nsh,
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usbserial, usbmsc. (usbnsh has not been rung out).
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nsh:
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---
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Configures the NuttShell (nsh) located at apps/examples/nsh. The
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Configuration enables the serial interfaces on UART2. Support for
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builtin applications is enabled, but in the base configuration no
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builtin applications are selected (see NOTES below).
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NOTES:
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1. This configuration uses the mconf-based configuration tool. To
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change this configuration using that tool, you should:
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a. Build and install the kconfig-mconf tool. See nuttx/README.txt
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and misc/tools/
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b. Execute 'make menuconfig' in nuttx/ in order to start the
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reconfiguration process.
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2. By default, this configuration uses the CodeSourcery toolchain
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for Linux. That can easily be reconfigured, of course.
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CONFIG_HOST_LINUX=y : Builds under Linux
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CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery for Linux
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3. Although the default console is USART2 (which would correspond to
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the Virtual COM port) I have done all testing with the console
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device configured for USART1 (see instruction above under "Serial
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Consoles). I have been using a TTL-to-RS-232 converted connected
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as shown below:
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Nucleo CN10 STM32F401RE
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----------- ------------
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Pin 21 PA9 USART2_RX
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Pin 33 PA10 USART2_TX
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Pin 20 GND
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Pin 8 U5V
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cc3000:
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------
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This configuration adds support for the CC3000 Shield.
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Build it with
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@@ -475,28 +525,6 @@ Configurations
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$ make qconfig
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N.B. Memory is tight, both Flash and RAM are taxed. If you enable
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debugging you will need to add -Os following the line -g in the line:
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ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
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ARCHOPTIMIZATION = -g
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in the top level Make.degs or the code will not fit.
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Stack space has been hand optimized using the stack coloring by enabling
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"Stack usage debug hooks" (CONFIG_DEBUG_STACK) in Build Setup-> Debug
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Options. I have selected values that have 8-16 bytes of headroom with
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network debugging on. If you enable more debugging and get a hard fault
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or any weirdness like commands hanging. Then the Idle, main or Interrupt
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stack my be too small. Stop the target and have a look a memory for a
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blown stack: No DEADBEEF at the lowest address of a given stack.
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Given the RAM memory constraints it is not possible to be running the
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network and USB CDC/ACM and MSC at the same time. But on the bright
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side, you can export the FLASH memory to the PC. Write files on the
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Flash. Reboot and mount the FAT FS and run network code that will have
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access the files.
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You can use the scripts/cdc-acm.inf file to install the windows
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composite device.
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@@ -228,14 +228,19 @@
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/* Alternate function pin selections ************************************************/
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/* USART1:
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* RXD: PA11 CN10 pin 14
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* RXD: PA10 CN9 pin 3, CN10 pin 33
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* PB7 CN7 pin 21
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* TXD: PA10 CN9 pin 3, CN10 pin 33
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* TXD: PA9 CN5 pin 1, CN10 pin 21
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* PB6 CN5 pin 3, CN10 pin 17
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*/
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#define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
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#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PA9 */
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#if 1
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# define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
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# define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
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#else
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# define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
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# define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
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#endif
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/* USART2:
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* RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37
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@@ -259,24 +264,11 @@
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#define GPIO_USART6_RX GPIO_USART6_RX_1 /* PC7 */
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#define GPIO_USART6_TX GPIO_USART6_TX_1 /* PC6 */
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/* UART8 has no alternate pin config */
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/* UART RX DMA configurations */
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#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2
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#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
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/* CAN
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*
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* CAN1 is routed to the onboard transceiver.
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* CAN2 is routed to the expansion connector.
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*/
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#define GPIO_CAN1_RX GPIO_CAN1_RX_3
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#define GPIO_CAN1_TX GPIO_CAN1_TX_3
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#define GPIO_CAN2_RX GPIO_CAN2_RX_1
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#define GPIO_CAN2_TX GPIO_CAN2_TX_2
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/* I2C
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*
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* The optional _GPIO configurations allow the I2C driver to manually
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