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stm32h7 rcc: Sync h7x7xx and h7x3xx. Changes are relevant to both

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This commit is contained in:
Anthony Merlino
2021-05-15 18:00:52 -04:00
committed by Brennan Ashton
parent 6b5a4cbfd3
commit 35553147ba
2 changed files with 45 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
+19 -1
View File
@@ -247,11 +247,17 @@ static inline void rcc_enableahb2(void)
regval = getreg32(STM32_RCC_AHB2ENR); regval = getreg32(STM32_RCC_AHB2ENR);
#ifdef CONFIG_STM32H7_SDMMC2 #ifdef CONFIG_STM32H7_SDMMC2
/* SDMMC clock enable */ /* SDMMC2 clock enable */
regval |= RCC_AHB2ENR_SDMMC2EN; regval |= RCC_AHB2ENR_SDMMC2EN;
#endif #endif
#ifdef CONFIG_STM32H7_RNG
/* Random number generator clock enable */
regval |= RCC_AHB2ENR_RNGEN;
#endif
putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */
} }
@@ -473,6 +479,18 @@ static inline void rcc_enableapb2(void)
regval |= RCC_APB2ENR_SPI5EN; regval |= RCC_APB2ENR_SPI5EN;
#endif #endif
#ifdef CONFIG_STM32H7_USART1
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN;
#endif
#ifdef CONFIG_STM32H7_USART6
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART6EN;
#endif
putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
} }
arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
+26 -10
View File
@@ -246,7 +246,17 @@ static inline void rcc_enableahb2(void)
regval = getreg32(STM32_RCC_AHB2ENR); regval = getreg32(STM32_RCC_AHB2ENR);
/* TODO: ... */ #ifdef CONFIG_STM32H7_SDMMC2
/* SDMMC2 clock enable */
regval |= RCC_AHB2ENR_SDMMC2EN;
#endif
#ifdef CONFIG_STM32H7_RNG
/* Random number generator clock enable */
regval |= RCC_AHB2ENR_RNGEN;
#endif
putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */
} }
@@ -469,12 +479,6 @@ static inline void rcc_enableapb2(void)
regval |= RCC_APB2ENR_SPI5EN; regval |= RCC_APB2ENR_SPI5EN;
#endif #endif
#ifdef CONFIG_STM32H7_SDMMC2
/* SDMMC2 clock enable */
regval |= RCC_APB2ENR_SDMMC2EN;
#endif
#ifdef CONFIG_STM32H7_USART1 #ifdef CONFIG_STM32H7_USART1
/* USART1 clock enable */ /* USART1 clock enable */
@@ -826,8 +830,6 @@ void stm32_stdclockconfig(void)
regval |= STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_LDOESCUEN; regval |= STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_LDOESCUEN;
putreg32(regval, STM32_PWR_CR3); putreg32(regval, STM32_PWR_CR3);
#if 0
/* Set the voltage output scale */ /* Set the voltage output scale */
regval = getreg32(STM32_PWR_D3CR); regval = getreg32(STM32_PWR_D3CR);
@@ -839,6 +841,12 @@ void stm32_stdclockconfig(void)
{ {
} }
/* See Reference manual Section 5.4.1, System supply startup */
while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0)
{
}
/* Over-drive is needed if /* Over-drive is needed if
* - Voltage output scale 1 mode is selected and SYSCLK frequency is * - Voltage output scale 1 mode is selected and SYSCLK frequency is
* over 400 MHz. * over 400 MHz.
@@ -863,7 +871,6 @@ void stm32_stdclockconfig(void)
{ {
} }
} }
#endif
/* Configure FLASH wait states */ /* Configure FLASH wait states */
@@ -952,6 +959,15 @@ void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_D3CCIPR); putreg32(regval, STM32_RCC_D3CCIPR);
#endif #endif
/* Configure FDCAN source clock */
#if defined(STM32_RCC_D2CCIP1R_FDCANSEL)
regval = getreg32(STM32_RCC_D2CCIP1R);
regval &= ~RCC_D2CCIP1R_FDCANSEL_MASK;
regval |= STM32_RCC_D2CCIP1R_FDCANSEL;
putreg32(regval, STM32_RCC_D2CCIP1R);
#endif
#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK) #if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK)
/* Low speed internal clock source LSI */ /* Low speed internal clock source LSI */