diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/Kconfig b/boards/arm/lpc17xx_40xx/lx_cpu/Kconfig new file mode 100644 index 00000000000..bb2f256fd95 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/Kconfig @@ -0,0 +1,32 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_LX_CPU + +choice + prompt "LX_CPU ode and boot memory selection" + default LX_CPU_BOOT_APP + depends on ARCH_BOARD_LX_CPU + ---help--- + Select where NuttX code/text is stored and how it is started. + Select "Code in internal FLASH - no loader used" (LX_CPU_BOOT_FLASH_BOOT) + if the code should be placed directly in start of the internal + FLASH memory and start directly after MCU reset. If there is + bool loader then NuttX can be placed into internal FLASH after + the loader - "Code in internal FLASH - loader used" (LX_CPU_BOOT_FLASH_APP) + or it can be loaded into extarnal SDRAM and start from there. + +config LX_CPU_BOOT_FLASH_APP + bool "Code in internal FLASH - loader used" + +config LX_CPU_BOOT_FLASH_BOOT + bool "Code in internal FLASH - no loader used" + +config LX_CPU_BOOT_SDRAM + bool "Code in external SDRAM" + +endchoice # LX_CPU ode and boot memory selection + +endif diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/README.txt b/boards/arm/lpc17xx_40xx/lx_cpu/README.txt new file mode 100644 index 00000000000..11924a59acd --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/README.txt @@ -0,0 +1,378 @@ +README.txt +========== + + This README file discusses the port of NuttX to the PiKRON LX_CPU board: + See http://pikron.com/pages/products/cpu_boards/lx_cpu.html. This board features the + NXP LPC4088 MCU + +CONTENTS +======== + + o LEDs + o Serial Console + o ETHERNET + o Using OpenOCD with the Olimex ARM-USB-OCD + o Loading Code with the ISP Board + o Configuration + +LEDs +==== + + The LX_CPU base board has two user LEDs + + LED1 : Connected to P1[29] RED + LED2 : Connected to P0[16] GREEN + + If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + any way using the defitions provided in the board.h header file. + + If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on the + WaveShare Open1788K. The following definitions describe how NuttX controls + the LEDs: + LED1 LED2 + LED_STARTED OFF OFF + LED_HEAPALLOCATE ON OFF + LED_IRQSENABLED OFF ON + LED_STACKCREATED ON ON + LED_INIRQ + LED_SIGNAL + LED_ASSERTION + LED_PANIC + LED_IDLE + +Serial Console +============== + + By Default, UART0 is used as the serial console in all configurations. This + may be connected to your computer via an external RS-232 driver or via the + WaveShare USB ISP/VCOM module. + + As an option, UART1 can also be used for the serial console. You might want, + to do this, for example, if you use UART0 for the ISP function and you want + to use a different UART for console output. UART1 can be configured as the + serial console by changing the configuration as follows: + + System Type: + CONFIG_LPC17_UART0=n : Disable UART0 if it is no longer used + CONFIG_LPC17_UART1=y : Enable UART1 + + Drivers: + CONFIG_UART1_SERIAL_CONSOLE=y : Setup up the UART1 configuration + CONFIG_UART1_RXBUFSIZE=256 + CONFIG_UART1_TXBUFSIZE=256 + CONFIG_UART1_BAUD=115200 + CONFIG_UART1_BITS=8 + CONFIG_UART1_PARITY=0 + CONFIG_UART1_2STOP=0 + + In this configuration using UART1, it is necessary to disable LED support + on the board. That is because UART1 RXD is set for pin p0.16, but so is + LED2. If you do not disable LED support then no incoming serial data will + be recevied. + + Common Board Options + CONFIG_ARCH_LEDS=n : Disable LED support + + You should also remove the LED2 jumper so that the RXD input does not + attempt to drive LED2 as well (However, this does not seem to interfere with + data receipt). + + NOTE: If you intend to use LEDs with UART1, then you might want to + redesign some ofthe LED logic in the src/ subdirectory so that it does not + attempt to use LED2. + +ETHERNET +======== + + On chip ethernet MAC with external 10/100M PHY DP83848I. + The LX_CPU board is populated with integrated connector + module (ICM) socket suitable for direct connection to + the standard ETHERNET infrastructure. + + Config + CONFIG_LPC17_ETHERNET=y + CONFIG_LPC17_PHY_AUTONEG=y + CONFIG_ETH0_PHY_DP83848C=y + + +Using OpenOCD with the Olimex ARM-USB-OCD +========================================= + + Building OpenOCD under Cygwin: + + Refer to configs/olimex-lpc1766stk/README.txt + + Installing OpenOCD in Ubuntu Linux: + + sudo apt-get install openocd + + Helper Scripts. + + I have been using the Olimex ARM-USB-OCD debugger. OpenOCD + requires a configuration file. I keep the one I used last here: + + boards/arm/lpc17xx_40xx/lx_cpu/tools/lx_cpu.cfg + + However, the "correct" configuration script to use with OpenOCD may + change as the features of OpenOCD evolve. So you should at least + compare that lx_cpu.cfg file with configuration files in + /usr/share/openocd/scripts. As of this writing, the configuration + files of interest were: + + /usr/local/share/openocd/scripts/interface/openocd-usb.cfg + This is the configuration file for the Olimex ARM-USB-OCD + debugger. Select a different file if you are using some + other debugger supported by OpenOCD. + + /usr/local/share/openocd/scripts/board/? + I don't see a board configuration file for the WaveShare + LX_CPU board. + + /usr/local/share/openocd/scripts/target/lpc1788.cfg + This is the configuration file for the LPC1788 target. + It just sets up a few parameters then sources lpc17xx.cfg + + /usr/local/share/openocd/scripts/target/lpc17xx.cfg + This is the generic LPC configuration for the LPC17xx + family. It is included by lpc1788.cfg. + + NOTE: These files could also be located under /usr/share in some + installations. They could be most anywhwere if you are using a + windows version of OpenOCD. + + boards/arm/lpc17xx_40xx/lx_cpu/tools/lx_cpu.cfg + This is simply openocd-usb.cfg, lpc1788.cfg, and lpc17xx.cfg + concatenated into one file for convenience. Don't use it + unless you have to. + + There is also a script on the tools/ directory that I use to start + the OpenOCD daemon on my system called oocd.sh. That script will + probably require some modifications to work in another environment: + + - Possibly the value of OPENOCD_PATH and TARGET_PATH + - It assumes that the correct script to use is the one at + boards/arm/lpc17xx_40xx/lx_cpu/tools/lx_cpu.cfg + + Starting OpenOCD + + Then you should be able to start the OpenOCD daemon as follows. This + assumes that you have already CD'ed to the NuttX build directory: + + . ./setenv.sh + oocd.sh $PWD + + The setenv.sh script is a convenience script that you may choose to + use or not. It simply sets up the PATH variable so that you can + automatically find oocd.sh. You could also do: + + boards/arm/lpc17xx_40xx/lx_cpu/tools/oocd.sh $PWD + + Connecting GDB + + Once the OpenOCD daemon has been started, you can connect to it via + GDB using the following GDB command: + + arm-nuttx-elf-gdb + (gdb) target remote localhost:3333 + + NOTE: The name of your GDB program may differ. For example, with the + CodeSourcery toolchain, the ARM GDB would be called arm-none-eabi-gdb. + + OpenOCD will support several special 'monitor' sub-commands. You can + use the 'monitor' (or simply 'mon') command to invoke these sub- + commands. These GDB commands will send comments to the OpenOCD monitor. + Here are a couple that you will need to use: + + (gdb) monitor reset + (gdb) monitor halt + + NOTES: + + 1. The MCU must be halted using 'monitor halt' prior to loading code. + + 2. 'monitor reset' will restart the processor after loading code. + + 3. The 'monitor' command can be abbreviated as just 'mon'. + + After starting GDB, you can load the NuttX ELF file like this: + + (gdb) mon halt + (gdb) load nuttx + + NOTES: + + 1. NuttX should have been built so that it has debugging symbols + (by setting CONFIG_DEBUG_SYMBOLS=y in the .config file). + + 2. The MCU must be halted prior to loading code. + + 3. I find that there are often undetected write failures when using + the Olimex ARM-USB-OCD debugber and that if you start the program + with a bad FLASH failure, it will lock up OpenOCD. I usually + oad nuttx twice, restarting OpenOCD in between in order to assure + good FLASH contents: + + (gdb) mon halt + (gdb) load nuttx + (gdb) mon reset + + Exit GDB, kill the OpenOCD server, recycle power on the board, + restart the OpenOCD server and GDB, then: + + (gdb) mon halt + (gdb) load nuttx + (gdb) mon reset + + Other debuggers may not have these issues and such drastic steps may + not be necessary. + +Loading Code with the ISP Board +=============================== + + Use can also load code onto the board using the WaveShare and the UART0 + ISP/VCOM board. I use the FlashMagic program for Windows available here: + http://www.flashmagictool.com/ . It is so easy to use that no further + explanation should be necessary: Just select the LPC1788, the ISP COM + port, and the NuttX .hex file and program it. + +CONFIGURATION +============= + + nsh + --- + Configures the NuttShell (nsh) located at examples/nsh. The + Configuration enables only the serial NSH interface. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository./README.txt. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Uses the older, OABI, buildroot toolchain. But that is easily + reconfigured: + + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain + CONFIG_ARMV7M_OABI_TOOLCHAIN=y : Older, OABI toolchain + + 3. This NSH has support for built-in applications enabled, however, + no built-in configurations are built in the defulat configuration. + + 4. This configuration has DMA-based SD card support enabled by + default. That support can be disabled as follow: + + CONFIG_LPC17_GPDMA=n : No DMA + CONFIG_ARCH_DMA=n + CONFIG_LPC17_SDCARD=n : No SD card driver + CONFIG_SDIO_DMA=n : No SD card DMA + CONFIG_MMCSD=n : No MMC/SD driver support + CONFIG_FS_FAT=n : No FAT file system support + + 5. This configuration has been used for verifying SDRAM by modifying + the configuration in the following ways: + + CONFIG_LPC17_EMC=y : Enable the EMC + CONFIG_LPC17_EXTDRAM=y : Configure external DRAM + CONFIG_LPC17_EXTDRAMSIZE=67108864 : DRAM size 2x256/8 = 64MB + CONFIG_SYSTEM_RAMTEST=y : Enable the RAM test built-in + + In this configuration, the SDRAM is not added to heap and so is + not excessible to the applications. So the RAM test can be + freely executed against the SRAM memory beginning at address + 0xa000:0000 (CS0). + + 6. This configuration has been used for verifying the touchscreen on + on the 4.3" LCD module. + + a) As of this writing, this touchscreen is still not functional. + Rommel Marcelo has tracked this problem down to noise on the + PENIRQ interrupt. There are so many false interrupts that + the NuttX interrupt-driven touchscreen driver cannot be used. + Other compatible LCDs, however, may not have this issue. + + b) You can enable the touchscreen by modifying the configuration + in the following ways: + + Drivers: + CONFIG_INPUT=y : Enable support for input devices + CONFIG_INPUT_ADS7843E=y : Enable support for the XPT2048 + CONFIG_ADS7843E_SPIDEV=1 : Use SSP1 for communication + CONFIG_SPI=y : Enable SPI support + CONFIG_SPI_EXCHANGE=n : exchange() method is not supported + + System Type: + CONFIG_GPIO_IRQ=y : GPIO interrupt support + CONFIG_LPC17_SSP1=y : Enable support for SSP1 + + RTOS Features: + CONFIG_DISABLE_SIGNALS=n : Signals are required + + Library Support: + CONFIG_SCHED_WORKQUEUE=y : Work queue support required + + Applicaton Configuration: + CONFIG_EXAMPLES_TOUCHSCREEN=y : Enable the touchscreen built-int test + + Defaults should be okay for related touchscreen settings. Touchscreen + debug output can be enabled with: + + Build Setup: + CONFIG_DEBUG=y : Enable debug features + CONFIG_DEBUG_VERBOSE=y : Enable verbose debug output + CONFIG_DEBUG_INPUT=y : Enable debug output from input devices + + c) You will also have to disable SD card support to use this test. The + SD card detect (CD) signal is on P0[13]. This signal is shared. It + is also used for MOSI1 and USB_UP_LED. The CD pin may be disconnected. + There is a jumper on board that enables the CD pin. OR, you can simply + remove the SD module so that it does not drive the CD pin. + + Drivers: + CONFIG_MMCSD=n : No MMC/SD driver support + + System Type: + CONFIG_LPC17_GPDMA=n : No DMA + CONFIG_LPC17_SDCARD=n : No SD card driver + CONFIG_SDIO_DMA=n : No SD card DMA + CONFIG_ARCH_DMA=n + + File Systems: + CONFIG_FS_FAT=n : No FAT file system support + + For touchscreen debug output: + + Build Setup: + CONFIG_DEBUG=y + CONFIG_DEBUG_VERBOSE=y + CONFIG_DEBUG_INPUT=y + + 7. The button test (apps/examples/buttons) can be built-in by adding + the following options. See apps/examples/README.txt for further + information about the button test. + + System Type: + CONFIG_GPIO_IRQ=y + + Board Selection: + CONFIG_ARCH_BUTTONS=y + CONFIG_ARCH_IRQBUTTONS=y + + Application Configuration: + CONFIG_EXAMPLES_BUTTONS=y + CONFIG_EXAMPLES_BUTTONS_MIN=0 + CONFIG_EXAMPLES_BUTTONS_MAX=7 + CONFIG_EXAMPLES_IRQBUTTONS_MIN=1 + CONFIG_EXAMPLES_IRQBUTTONS_MAX=7 + CONFIG_EXAMPLES_BUTTONS_NAME0="USER1" + CONFIG_EXAMPLES_BUTTONS_NAME1="USER2" + CONFIG_EXAMPLES_BUTTONS_NAME2="USER3" + CONFIG_EXAMPLES_BUTTONS_NAME3="JOYSTICK_A" + CONFIG_EXAMPLES_BUTTONS_NAME4="JOYSTICK_B" + CONFIG_EXAMPLES_BUTTONS_NAME5="JOYSTICK_C" + CONFIG_EXAMPLES_BUTTONS_NAME6="JOYSTICK_D" + CONFIG_EXAMPLES_BUTTONS_NAME7="JOYSTICK_CTR" diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/lx_cpu/configs/nsh/defconfig new file mode 100644 index 00000000000..284438068a0 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/configs/nsh/defconfig @@ -0,0 +1,1669 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_MACOS is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +# CONFIG_BUILD_LOADABLE is not set +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +# CONFIG_RAW_BINARY is not set +# CONFIG_UBOOT_UIMAGE is not set +# CONFIG_DFU_BINARY is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +CONFIG_DEBUG_FEATURES=y + +# +# Debug SYSLOG Output Controls +# +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_WARN=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_ASSERTIONS=y + +# +# Subsystem Debug Options +# +# CONFIG_DEBUG_BINFMT is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_GRAPHICS is not set +# CONFIG_DEBUG_LIB is not set +# CONFIG_DEBUG_MM is not set +# CONFIG_DEBUG_NET is not set +# CONFIG_DEBUG_POWER is not set +# CONFIG_DEBUG_SCHED is not set + +# +# OS Function Debug Options +# +# CONFIG_DEBUG_DMA is not set +# CONFIG_DEBUG_IRQ is not set + +# +# Driver Debug Options +# +# CONFIG_DEBUG_LEDS is not set +# CONFIG_DEBUG_CAN is not set +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_MEMCARD is not set +# CONFIG_DEBUG_TIMER is not set +# CONFIG_DEBUG_USB is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +# CONFIG_ARCH_OR1K is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_AM335X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_IMXRT is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LC823450 is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +CONFIG_ARCH_CHIP_LPC17XX=y +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_LPC54XX is not set +# CONFIG_ARCH_CHIP_MAX326XX is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_CHIP_NRF52 is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD2X is not set +# CONFIG_ARCH_CHIP_SAML2X is not set +# CONFIG_ARCH_CHIP_SAMD5X is not set +# CONFIG_ARCH_CHIP_SAME5X is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STM32F0 is not set +# CONFIG_ARCH_CHIP_STM32L0 is not set +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32H7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_XMC4 is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM1136J is not set +# CONFIG_ARCH_ARM1156T2 is not set +# CONFIG_ARCH_ARM1176JZ is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM23 is not set +CONFIG_ARCH_CORTEXM3=y +# CONFIG_ARCH_CORTEXM33 is not set +# CONFIG_ARCH_CORTEXM4 is not set +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEXR5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="lpc17xx" +# CONFIG_ARCH_HAVE_FPU is not set +# CONFIG_ARCH_HAVE_DPFPU is not set +CONFIG_ARCH_HAVE_LAZYFPU=y +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set +CONFIG_ARCH_HAVE_HARDFAULT_DEBUG=y +# CONFIG_DEBUG_HARDFAULT_ALERT is not set +# CONFIG_DEBUG_HARDFAULT_INFO is not set +CONFIG_ARCH_HAVE_MEMFAULT_DEBUG=y +# CONFIG_ARM_SEMIHOSTING_SYSLOG is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_LAZYFPU is not set +# CONFIG_ARMV7M_USEBASEPRI is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +# CONFIG_ARMV7M_TOOLCHAIN_CLANGL is not set +# CONFIG_ARMV7M_TARGET2_PREL is not set +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set + +# +# LPC17xx Configuration Options +# +# CONFIG_ARCH_CHIP_LPC1751 is not set +# CONFIG_ARCH_CHIP_LPC1752 is not set +# CONFIG_ARCH_CHIP_LPC1754 is not set +# CONFIG_ARCH_CHIP_LPC1756 is not set +# CONFIG_ARCH_CHIP_LPC1758 is not set +# CONFIG_ARCH_CHIP_LPC1759 is not set +# CONFIG_ARCH_CHIP_LPC1764 is not set +# CONFIG_ARCH_CHIP_LPC1765 is not set +# CONFIG_ARCH_CHIP_LPC1766 is not set +# CONFIG_ARCH_CHIP_LPC1767 is not set +# CONFIG_ARCH_CHIP_LPC1768 is not set +# CONFIG_ARCH_CHIP_LPC1769 is not set +# CONFIG_ARCH_CHIP_LPC1773 is not set +# CONFIG_ARCH_CHIP_LPC1774 is not set +# CONFIG_ARCH_CHIP_LPC1776 is not set +# CONFIG_ARCH_CHIP_LPC1777 is not set +# CONFIG_ARCH_CHIP_LPC1778 is not set +# CONFIG_ARCH_CHIP_LPC1785 is not set +# CONFIG_ARCH_CHIP_LPC1786 is not set +# CONFIG_ARCH_CHIP_LPC1787 is not set +CONFIG_ARCH_CHIP_LPC1788=y +CONFIG_ARCH_FAMILY_LPC178X=y + +# +# LPC17xx Peripheral Support +# +CONFIG_LPC17_MAINOSC=y +CONFIG_LPC17_PLL0=y +CONFIG_LPC17_PLL1=y +CONFIG_LPC17_EMC=y +CONFIG_LPC17_ETHERNET=y +# CONFIG_LPC17_LCD is not set +# CONFIG_LPC17_USBHOST is not set +# CONFIG_LPC17_USBDEV is not set +CONFIG_LPC17_SDCARD=y +CONFIG_LPC17_UART0=y +CONFIG_LPC17_UART1=y +# CONFIG_LPC17_UART2 is not set +# CONFIG_LPC17_UART3 is not set +# CONFIG_LPC17_UART4 is not set +# CONFIG_LPC17_CAN1 is not set +CONFIG_LPC17_CAN2=y +CONFIG_LPC17_SSP0=y +CONFIG_LPC17_SSP1=y +# CONFIG_LPC17_SSP2 is not set +# CONFIG_LPC17_I2C0 is not set +# CONFIG_LPC17_I2C1 is not set +# CONFIG_LPC17_I2C2 is not set +# CONFIG_LPC17_I2S is not set +# CONFIG_LPC17_TMR0 is not set +# CONFIG_LPC17_TMR1 is not set +# CONFIG_LPC17_TMR2 is not set +# CONFIG_LPC17_TMR3 is not set +# CONFIG_LPC17_RIT is not set +# CONFIG_LPC17_PWM0 is not set +# CONFIG_LPC17_PWM1 is not set +# CONFIG_LPC17_QEI is not set +# CONFIG_LPC17_RTC is not set +# CONFIG_LPC17_WDT is not set +# CONFIG_LPC17_ADC is not set +# CONFIG_LPC17_DAC is not set +CONFIG_LPC17_GPDMA=y +# CONFIG_LPC17_CRC is not set +CONFIG_LPC17_FLASH=y +# CONFIG_LPC17_EEPROM is not set +# CONFIG_LPC17_PROGMEM is not set + +# +# External Memory Configuration +# +CONFIG_LPC17_HAVE_EXTNAND=y +CONFIG_LPC17_HAVE_EXTNOR=y +CONFIG_LPC17_HAVE_EXTDRAM=y +CONFIG_LPC17_HAVE_EXTSRAM0=y +# CONFIG_LPC17_EXTNAND is not set +# CONFIG_LPC17_EXTNOR is not set +CONFIG_LPC17_EXTDRAM=y +CONFIG_LPC17_EXTDRAMSIZE=33554432 +# CONFIG_LPC17_SDRAM_8BIT is not set +# CONFIG_LPC17_SDRAM_16BIT is not set +CONFIG_LPC17_SDRAM_32BIT=y +CONFIG_LPC17_EXTDRAMHEAP=y +# CONFIG_LPC17_EXTSRAM0 is not set + +# +# Serial driver options +# +# CONFIG_LPC17_UART1_RINGINDICATOR is not set + +# +# CAN driver options +# +CONFIG_LPC17_CAN2_BAUD=1000000 +CONFIG_LPC17_CAN2_DIVISOR=4 +CONFIG_LPC17_CAN_TSEG1=6 +CONFIG_LPC17_CAN_TSEG2=4 +CONFIG_LPC17_CAN_SAM=y +# CONFIG_LPC17_GPIOIRQ is not set + +# +# SDCARD Configuration +# +CONFIG_LPC17_SDCARD_DMA=y +# CONFIG_LPC17_SDCARD_WIDTH_D1_ONLY is not set + +# +# Ethernet driver options +# +CONFIG_LPC17_PHY_AUTONEG=y +CONFIG_LPC17_EMACRAM_SIZE=16384 +CONFIG_LPC17_ETH_NTXDESC=10 +CONFIG_LPC17_ETH_NRXDESC=10 +# CONFIG_LPC17_NET_WOL is not set +# CONFIG_LPC17_ETH_HASH is not set +CONFIG_LPC17_MULTICAST=y +# CONFIG_ARCH_TOOLCHAIN_IAR is not set +CONFIG_ARCH_TOOLCHAIN_GNU=y +# CONFIG_ARCH_GNU_NO_WEAKFUNCTIONS is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +CONFIG_ARCH_HAVE_IRQTRIGGER=y +CONFIG_ARCH_DMA=y +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +# CONFIG_ARCH_HAVE_PROGMEM is not set +CONFIG_ARCH_HAVE_RESET=y +CONFIG_ARCH_HAVE_FETCHADD=y +# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set +# CONFIG_ARCH_HAVE_GARBAGE is not set +# CONFIG_ARCH_GLOBAL_IRQDISABLE is not set +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set +# CONFIG_ARCH_MINIMAL_VECTORTABLE is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=11934 + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x10000000 +CONFIG_RAM_SIZE=65536 +CONFIG_ARCH_HAVE_SDRAM=y +CONFIG_BOOT_SDRAM_DATA=y + +# +# Board Selection +# +CONFIG_ARCH_BOARD_LX_CPU=y +# CONFIG_ARCH_BOARD_OPEN1788 is not set +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="lx_cpu" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y + +# +# Board-Specific Options +# +CONFIG_LX_CPU_BOOT_FLASH_APP=y +# CONFIG_LX_CPU_BOOT_FLASH_BOOT is not set +# CONFIG_LX_CPU_BOOT_SDRAM is not set +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_FINALINIT is not set +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_APP_SYMTAB is not set +# CONFIG_BOARDCTL_USBDEVCTRL is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=3 +CONFIG_START_DAY=4 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_SPINLOCK is not set +# CONFIG_IRQCHAIN is not set +# CONFIG_IRQCOUNT is not set +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_PRIORITY=100 +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +CONFIG_NPTHREAD_KEYS=4 +# CONFIG_PTHREAD_MUTEX_TYPES is not set +CONFIG_PTHREAD_MUTEX_ROBUST=y +# CONFIG_PTHREAD_MUTEX_UNSAFE is not set +# CONFIG_PTHREAD_MUTEX_BOTH is not set +# CONFIG_PTHREAD_CLEANUP is not set +# CONFIG_CANCELLATION_POINTS is not set + +# +# Performance Monitoring +# +# CONFIG_SCHED_SUSPENDSCHEDULER is not set +# CONFIG_SCHED_RESUMESCHEDULER is not set +# CONFIG_SCHED_IRQMONITOR is not set +# CONFIG_SCHED_CRITMONITOR is not set +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +# CONFIG_SDCLONE_DISABLE is not set +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Configuration +# +# CONFIG_SIG_EVTHREAD is not set +# CONFIG_SIG_DEFAULT is not set + +# +# Signal Numbers +# + +# +# Standard Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALRM=3 + +# +# Non-standard Signal Numbers +# +CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPNTHREADS=1 +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +# CONFIG_WQUEUE_NOTIFIER is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +CONFIG_CAN=y +# CONFIG_CAN_EXTID is not set +# CONFIG_ARCH_HAVE_CAN_ERRORS is not set +# CONFIG_CAN_FD is not set +CONFIG_CAN_FIFOSIZE=8 +CONFIG_CAN_NPENDINGRTR=4 +# CONFIG_CAN_TXREADY is not set +# CONFIG_CAN_LOOPBACK is not set +CONFIG_CAN_NPOLLWAITERS=2 + +# +# CAN Bus Controllers: +# +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set +# CONFIG_SPI is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_DRIVERS_AUDIO is not set +# CONFIG_FB_CMAP is not set +# CONFIG_FB_TRANSPARENCY is not set +# CONFIG_DRIVERS_VIDEO is not set +CONFIG_BCH=y +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set + +# +# Character/Segment LCD Devices +# +# CONFIG_SLCD is not set + +# +# Other LCD-related Devices +# +# CONFIG_LCD_OTHER is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_LEDS_APA102 is not set +# CONFIG_LEDS_MAX7219 is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +CONFIG_ARCH_HAVE_SDIO=y +# CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE is not set +# CONFIG_ARCH_HAVE_SDIO_PREFLIGHT is not set +# CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT is not set +CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +# CONFIG_MMCSD_MULTIBLOCK_DISABLE is not set +CONFIG_MMCSD_MMCSUPPORT=y +CONFIG_MMCSD_HAVE_CARDDETECT=y +CONFIG_MMCSD_HAVE_WRITEPROTECT=y +CONFIG_SDIO_DMA=y +CONFIG_MMCSD_SDIO=y +# CONFIG_SDIO_MUXBUS is not set +# CONFIG_SDIO_WIDTH_D1_ONLY is not set +# CONFIG_SDIO_BLOCKSETUP is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +CONFIG_NETDEVICES=y + +# +# General Ethernet MAC Driver Options +# +CONFIG_NETDEV_LOOPBACK=y +CONFIG_NETDEV_TELNET=y +CONFIG_TELNET_RXBUFFER_SIZE=256 +CONFIG_TELNET_TXBUFFER_SIZE=256 +# CONFIG_TELNET_CHARACTER_MODE is not set +# CONFIG_TELNET_SUPPORT_NAWS is not set +CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y +# CONFIG_NET_DUMPPACKET is not set + +# +# External Ethernet MAC Device Support +# +# CONFIG_NET_DM90x0 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ENCX24J600 is not set +# CONFIG_NET_SLIP is not set +# CONFIG_NET_FTMAC100 is not set +# CONFIG_NET_LAN91C111 is not set + +# +# External Ethernet PHY Device Support +# +# CONFIG_ARCH_PHY_INTERRUPT is not set +# CONFIG_ETH0_PHY_NONE is not set +# CONFIG_ETH0_PHY_AM79C874 is not set +# CONFIG_ETH0_PHY_KS8721 is not set +# CONFIG_ETH0_PHY_KSZ8041 is not set +# CONFIG_ETH0_PHY_KSZ8051 is not set +# CONFIG_ETH0_PHY_KSZ8061 is not set +# CONFIG_ETH0_PHY_KSZ8081 is not set +# CONFIG_ETH0_PHY_KSZ90x1 is not set +CONFIG_ETH0_PHY_DP83848C=y +# CONFIG_ETH0_PHY_LAN8720 is not set +# CONFIG_ETH0_PHY_LAN8740 is not set +# CONFIG_ETH0_PHY_LAN8740A is not set +# CONFIG_ETH0_PHY_LAN8742A is not set +# CONFIG_ETH0_PHY_DM9161 is not set +# CONFIG_ETH1_PHY_NONE is not set +# CONFIG_ETH1_PHY_AM79C874 is not set +# CONFIG_ETH1_PHY_KS8721 is not set +# CONFIG_ETH1_PHY_KSZ8041 is not set +# CONFIG_ETH1_PHY_KSZ8051 is not set +# CONFIG_ETH1_PHY_KSZ8081 is not set +# CONFIG_ETH1_PHY_KSZ90x1 is not set +CONFIG_ETH1_PHY_DP83848C=y +# CONFIG_ETH1_PHY_LAN8720 is not set +# CONFIG_ETH1_PHY_DM9161 is not set +CONFIG_NETDEV_PHY_DEBUG=y +CONFIG_PIPES=y +CONFIG_DEV_PIPE_MAXSIZE=1024 +CONFIG_DEV_PIPE_SIZE=1024 +CONFIG_DEV_FIFO_SIZE=1024 +# CONFIG_PM is not set +# CONFIG_DRIVERS_POWERLED is not set +# CONFIG_DRIVERS_SMPS is not set +# CONFIG_DRIVERS_MOTOR is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_SERIAL_TIOCSERGSTRUCT is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +# CONFIG_SERIAL_TERMIOS is not set +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_UART1_SERIAL_CONSOLE is not set +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set +# CONFIG_UART_SERIALDRIVER is not set +CONFIG_UART0_SERIALDRIVER=y +CONFIG_UART1_SERIALDRIVER=y +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_UART0_DMA is not set + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=115200 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_UART1_IFLOWCONTROL is not set +# CONFIG_UART1_OFLOWCONTROL is not set +# CONFIG_UART1_DMA is not set +# CONFIG_LPUART_SERIALDRIVER is not set +# CONFIG_LPUART0_SERIALDRIVER is not set +# CONFIG_LPUART1_SERIALDRIVER is not set +# CONFIG_LPUART2_SERIALDRIVER is not set +# CONFIG_LPUART3_SERIALDRIVER is not set +# CONFIG_LPUART4_SERIALDRIVER is not set +# CONFIG_LPUART5_SERIALDRIVER is not set +# CONFIG_LPUART6_SERIALDRIVER is not set +# CONFIG_LPUART7_SERIALDRIVER is not set +# CONFIG_LPUART8_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_USART9_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_PSEUDOTERM is not set +CONFIG_USBDEV=y + +# +# USB Device Controller Driver Options +# +# CONFIG_USBDEV_ISOCHRONOUS is not set +# CONFIG_USBDEV_DUALSPEED is not set +CONFIG_USBDEV_SELFPOWERED=y +# CONFIG_USBDEV_BUSPOWERED is not set +CONFIG_USBDEV_MAXPOWER=100 +# CONFIG_USBDEV_DMA is not set +# CONFIG_ARCH_USBDEV_STALLQUEUE is not set +# CONFIG_USBDEV_TRACE is not set + +# +# USB Device Class Driver Options +# +# CONFIG_USBDEV_COMPOSITE is not set +# CONFIG_PL2303 is not set +# CONFIG_CDCACM is not set +# CONFIG_USBMSC is not set +# CONFIG_RNDIS is not set +# CONFIG_DFU is not set +# CONFIG_NET_CDCECM is not set +# CONFIG_USBHOST is not set +# CONFIG_USBMISC is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set +# CONFIG_1WIRE is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +CONFIG_SYSLOG_WRITE=y +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_BUFFER is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +# CONFIG_SYSLOG_PREFIX is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +CONFIG_ARCH_HAVE_NET=y +CONFIG_ARCH_HAVE_PHY=y +CONFIG_NET_WRITE_BUFFERS=y +CONFIG_NET_READAHEAD=y +# CONFIG_NET_MCASTGROUP is not set +CONFIG_NET=y +# CONFIG_NET_PROMISCUOUS is not set + +# +# Driver buffer configuration +# +CONFIG_NET_ETH_PKTSIZE=590 +CONFIG_NET_GUARDSIZE=2 + +# +# Link layer support +# +CONFIG_NET_ETHERNET=y +CONFIG_NET_LOOPBACK=y +# CONFIG_NET_TUN is not set +# CONFIG_NET_USRSOCK is not set +# CONFIG_NETDEV_LATEINIT is not set + +# +# Network Device Operations +# +CONFIG_NETDEV_IOCTL=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_IFINDEX=y + +# +# Internet Protocol Selection +# +CONFIG_NET_IPv4=y +# CONFIG_NET_IPv6 is not set +# CONFIG_NET_IPFORWARD is not set + +# +# Socket Support +# +CONFIG_NSOCKET_DESCRIPTORS=8 +CONFIG_NET_NACTIVESOCKETS=16 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCPPROTO_OPTIONS=y +CONFIG_NET_UDPPROTO_OPTIONS=y +CONFIG_NET_SOLINGER=y + +# +# Raw Socket Support +# +CONFIG_NET_PKT=y +CONFIG_NET_PKT_CONNS=1 + +# +# Unix Domain Socket Support +# +# CONFIG_NET_LOCAL is not set + +# +# TCP/IP Networking +# +CONFIG_NET_TCP=y +# CONFIG_NET_TCP_NO_STACK is not set +CONFIG_NET_TCP_KEEPALIVE=y +# CONFIG_NET_TCPURGDATA is not set +CONFIG_NET_TCP_CONNS=8 +CONFIG_NET_MAX_LISTENPORTS=20 +CONFIG_NET_TCP_READAHEAD=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_TCP_NWRBCHAINS=8 +# CONFIG_NET_TCP_WRBUFFER_DEBUG is not set +CONFIG_NET_TCP_RECVDELAY=0 +CONFIG_NET_TCPBACKLOG=y +CONFIG_NET_TCPBACKLOG_CONNS=8 +# CONFIG_NET_SENDFILE is not set + +# +# UDP Networking +# +CONFIG_NET_UDP=y +# CONFIG_NET_UDP_NO_STACK is not set +CONFIG_NET_UDP_BINDTODEVICE=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NET_UDP_CONNS=8 +CONFIG_NET_BROADCAST=y +CONFIG_NET_UDP_READAHEAD=y +# CONFIG_UDP_READAHEAD_NOTIFIER is not set +# CONFIG_NET_UDP_WRITE_BUFFERS is not set + +# +# Bluetooth socket support +# + +# +# IEEE 802.15.4 socket support +# + +# +# ICMP Networking Support +# +CONFIG_NET_ICMP=y +# CONFIG_NET_ICMP_NO_STACK is not set +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_ICMP_NCONNS=4 +# CONFIG_NET_IGMP is not set + +# +# ARP Configuration +# +CONFIG_NET_ARP=y +CONFIG_NET_ARPTAB_SIZE=16 +CONFIG_NET_ARP_MAXAGE=120 +# CONFIG_NET_ARP_IPIN is not set +# CONFIG_NET_ARP_SEND is not set + +# +# User-space networking stack API +# +# CONFIG_NET_ARCH_INCR32 is not set +# CONFIG_NET_ARCH_CHKSUM is not set +# CONFIG_NET_STATISTICS is not set +# CONFIG_NET_HAVE_STAR is not set + +# +# Network Topologies +# + +# +# Routing Table Configuration +# +CONFIG_NET_ROUTE=y +CONFIG_ROUTE_IPv4_RAMROUTE=y +# CONFIG_ROUTE_IPv4_ROMROUTE is not set +# CONFIG_ROUTE_IPv4_FILEROUTE is not set +CONFIG_ROUTE_MAX_IPv4_RAMROUTES=4 + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_PSEUDOFS_SOFTLINKS is not set +CONFIG_FS_READABLE=y +CONFIG_FS_WRITABLE=y +CONFIG_FS_NAMED_SEMAPHORES=y +CONFIG_FS_NAMED_SEMPATH="/var/lock" +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set + +# +# Partition Table +# +# CONFIG_PTABLE_PARTITION is not set +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +# CONFIG_FAT_LFN_ALIAS_HASH is not set +CONFIG_FAT_LFN_ALIAS_TRAILCHARS=0 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_FORCE_INDIRECT is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FAT_DIRECT_RETRY is not set +CONFIG_NFS=y +# CONFIG_NFS_STATISTICS is not set +# CONFIG_FS_NXFFS is not set +CONFIG_FS_ROMFS=y +# CONFIG_FS_CROMFS is not set +CONFIG_FS_TMPFS=y +CONFIG_FS_TMPFS_BLOCKSIZE=512 +CONFIG_FS_TMPFS_DIRECTORY_ALLOCGUARD=64 +CONFIG_FS_TMPFS_DIRECTORY_FREEGUARD=128 +CONFIG_FS_TMPFS_FILE_ALLOCGUARD=512 +CONFIG_FS_TMPFS_FILE_FREEGUARD=1024 +# CONFIG_FS_SMARTFS is not set +CONFIG_FS_BINFS=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set +# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_PROCFS_EXCLUDE_NET is not set +# CONFIG_FS_PROCFS_EXCLUDE_ROUTE is not set +# CONFIG_FS_SPIFFS is not set +CONFIG_FS_UNIONFS=y +# CONFIG_FS_USERFS is not set +# CONFIG_FS_HOSTFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set +# CONFIG_NXFONTS is not set + +# +# Font Cache Pixel Depths +# +# CONFIG_NXFONTS_DISABLE_1BPP is not set +# CONFIG_NXFONTS_DISABLE_2BPP is not set +# CONFIG_NXFONTS_DISABLE_4BPP is not set +# CONFIG_NXFONTS_DISABLE_8BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_24BPP is not set +# CONFIG_NXFONTS_DISABLE_32BPP is not set +CONFIG_NXFONTS_PACKEDMSFIRST=y +# CONFIG_NXGLIB is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=3 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set +# CONFIG_MM_FILL_ALLOCATIONS is not set + +# +# Common I/O Buffer Support +# +CONFIG_MM_IOB=y +CONFIG_IOB_NBUFFERS=36 +CONFIG_IOB_BUFSIZE=196 +CONFIG_IOB_NCHAINS=8 +CONFIG_IOB_THROTTLE=8 +# CONFIG_IOB_NOTIFIER is not set +# CONFIG_IOB_DEBUG is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# +# CONFIG_WIRELESS is not set + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +CONFIG_BINFMT_LOADABLE=y +CONFIG_PIC=y +CONFIG_NXFLAT=y +# CONFIG_NXFLAT_DUMPBUFFER is not set +CONFIG_ELF=y +CONFIG_ELF_ALIGN_LOG2=2 +CONFIG_ELF_STACKSIZE=2048 +CONFIG_ELF_BUFFERSIZE=128 +CONFIG_ELF_BUFFERINCR=32 +# CONFIG_ELF_DUMPBUFFER is not set +CONFIG_BUILTIN=y +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# + +# +# Standard C I/O +# +# CONFIG_STDIO_DISABLE_BUFFERING is not set +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_SCANSET is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_MEMCPY_VIK is not set +# CONFIG_LIBM is not set + +# +# Architecture-Specific Support +# +CONFIG_ARCH_LOWPUTC=y +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_LIBC_ARCH_MEMCPY is not set +# CONFIG_LIBC_ARCH_MEMCMP is not set +# CONFIG_LIBC_ARCH_MEMMOVE is not set +# CONFIG_LIBC_ARCH_MEMSET is not set +# CONFIG_LIBC_ARCH_STRCHR is not set +# CONFIG_LIBC_ARCH_STRCMP is not set +# CONFIG_LIBC_ARCH_STRCPY is not set +# CONFIG_LIBC_ARCH_STRNCPY is not set +# CONFIG_LIBC_ARCH_STRLEN is not set +# CONFIG_LIBC_ARCH_STRNLEN is not set +CONFIG_LIBC_ARCH_ELF=y +# CONFIG_ARMV7M_MEMCPY is not set + +# +# stdlib Options +# +CONFIG_LIB_RAND_ORDER=1 +CONFIG_LIB_HOMEDIR="/" +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 + +# +# Program Execution Options +# +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +CONFIG_LIB_HOSTNAME="" + +# +# errno Decode Support +# +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set + +# +# memcpy/memset Options +# +# CONFIG_MEMSET_OPTSPEED is not set +# CONFIG_LIBC_DLLFCN is not set +# CONFIG_LIBC_MODLIB is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set +# CONFIG_LIBC_LZF is not set + +# +# Time/Time Zone Support +# +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_ARCH_HAVE_TLS=y + +# +# Thread Local Storage (TLS) +# +# CONFIG_TLS is not set + +# +# Network-Related Options +# +# CONFIG_LIBC_IPv6_ADDRCONV is not set +CONFIG_LIBC_NETDB=y + +# +# NETDB Support +# +# CONFIG_LIBC_GAISTRERROR is not set +# CONFIG_NETDB_HOSTFILE is not set +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=8 +CONFIG_NETDB_DNSCLIENT_NAMESIZE=32 +CONFIG_NETDB_DNSCLIENT_LIFESEC=3600 +CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=96 +CONFIG_NETDB_DNSCLIENT_MAXIP=1 +CONFIG_NETDB_DNSCLIENT_RECV_TIMEOUT=30 +CONFIG_NETDB_DNSCLIENT_RETRIES=3 +# CONFIG_NETDB_RESOLVCONF is not set +CONFIG_NETDB_DNSSERVER_NOADDR=y +# CONFIG_NETDB_DNSSERVER_IPv4 is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_ENVPATH is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set +# CONFIG_LIBDSP is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=2048 + +# +# CAN Utilities +# +CONFIG_CANUTILS_CANLIB=y +# CONFIG_CANUTILS_LIBOBD2 is not set + +# +# Examples +# +# CONFIG_EXAMPLES_ADXL372_TEST is not set +# CONFIG_EXAMPLES_APA102 is not set +# CONFIG_EXAMPLES_BATTERY is not set +# CONFIG_EXAMPLES_BRIDGE is not set +# CONFIG_EXAMPLES_CALIB_UDELAY is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CPUHOG is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_DHTXX is not set +# CONFIG_EXAMPLES_DISCOVER is not set +# CONFIG_EXAMPLES_DSPTEST is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_GPS is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_INA219 is not set +# CONFIG_EXAMPLES_INA226 is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_LSM330SPI_TEST is not set +# CONFIG_EXAMPLES_LVGLDEMO is not set +# CONFIG_EXAMPLES_MAX31855 is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MLX90614 is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NETLOOP is not set +# CONFIG_EXAMPLES_NETPKT is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXDEMO is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_OBD2 is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_PDCURSES is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POPEN is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_POWERLED is not set +# CONFIG_EXAMPLES_POWERMONITOR is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMPS is not set +# CONFIG_EXAMPLES_STAT is not set +# CONFIG_EXAMPLES_SYSTEM is not set +# CONFIG_EXAMPLES_TCPBLASTER is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDPBLASTER is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UNIONFS is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USERFS is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_XBC_TEST is not set +# CONFIG_EXAMPLES_XMLRPC is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set +CONFIG_FSUTILS_MKFATFS=y +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_GRAPHICS_FT80X is not set +# CONFIG_GRAPHICS_LVGL is not set + +# +# NxWidgets/NxWM +# + +# +# NxWidgets +# + +# +# NxWM +# + +# +# Unit Tests +# +# CONFIG_GRAPHICS_PDCURSES is not set +# CONFIG_TIFF is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +CONFIG_NETUTILS_DHCPC=y +# CONFIG_NETUTILS_DHCPD is not set +# CONFIG_NETUTILS_DISCOVER is not set +# CONFIG_NETUTILS_ESP8266 is not set +CONFIG_NETUTILS_FTPC=y +# CONFIG_DEBUG_FTPC is not set +CONFIG_FTP_TMPDIR="/tmp" +# CONFIG_FTPC_DISABLE_EPRT is not set +# CONFIG_FTPC_DISABLE_EPSV is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +CONFIG_NETUTILS_NETLIB=y +CONFIG_NETUTILS_NTPCLIENT=y +CONFIG_NETUTILS_NTPCLIENT_SERVER="pool.ntp.org" +CONFIG_NETUTILS_NTPCLIENT_PORTNO=123 +CONFIG_NETUTILS_NTPCLIENT_STACKSIZE=2048 +CONFIG_NETUTILS_NTPCLIENT_SERVERPRIO=100 +CONFIG_NETUTILS_NTPCLIENT_POLLDELAYSEC=60 +CONFIG_NETUTILS_NTPCLIENT_SIGWAKEUP=18 +CONFIG_NETUTILS_PING=y +# CONFIG_NETUTILS_PPPD is not set +# CONFIG_NETUTILS_SMTP is not set +CONFIG_NETUTILS_TELNETC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +# CONFIG_NETUTILS_THTTPD is not set +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)" +CONFIG_WEBCLIENT_TIMEOUT=10 +# CONFIG_NETUTILS_WEBSERVER is not set +# CONFIG_NETUTILS_XMLRPC is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_PROMPT_STRING="nsh> " +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=80 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_QUOTE=y +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=7 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_ARP is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_ENV is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_EXPORT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_IFUPDOWN is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSFMOUNT is not set +# CONFIG_NSH_DISABLE_NSLOOKUP is not set +# CONFIG_NSH_DISABLE_PRINTF is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_ROUTE is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_TELNETD is not set +# CONFIG_NSH_DISABLE_TRUNCATE is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 + +# +# Configure Command Options +# +# CONFIG_NSH_VARS is not set +# CONFIG_NSH_CMDOPT_DD_STATS is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_PROC_MOUNTPOINT="/proc" +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_ROMFSETC is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y + +# +# USB Device Trace Support +# +# CONFIG_NSH_USBDEV_TRACE is not set +CONFIG_NSH_ARCHINIT=y + +# +# Networking Configuration +# +CONFIG_NSH_NETINIT=y +# CONFIG_NSH_NETLOCAL is not set +# CONFIG_NSH_NETINIT_THREAD is not set +# CONFIG_NSH_NETINIT_DEBUG is not set + +# +# IP Address Configuration +# +CONFIG_NSH_DHCPC=y + +# +# IPv4 Addresses +# +CONFIG_NSH_DRIPADDR=0x0a000001 +CONFIG_NSH_NETMASK=0xffffff00 +CONFIG_NSH_DNS=y +CONFIG_NSH_DNSIPADDR=0xa0000001 +CONFIG_NSH_NOMAC=y +CONFIG_NSH_SWMAC=y +CONFIG_NSH_MACADDR=0x00e0deadbeef + +# +# Telnet Configuration +# +CONFIG_NSH_TELNET=y +CONFIG_NSH_TELNETD_PORT=23 +CONFIG_NSH_TELNETD_DAEMONPRIO=100 +CONFIG_NSH_TELNETD_DAEMONSTACKSIZE=2048 +CONFIG_NSH_TELNETD_CLIENTPRIO=100 +CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=2048 +CONFIG_NSH_IOBUFFER_SIZE=512 +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set +# CONFIG_NSH_TELNET_LOGIN is not set + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_DHCPC_RENEW_PRIORITY=100 +CONFIG_DHCPC_RENEW_STACKSIZE=2048 +# CONFIG_SYSTEM_EMBEDLOG is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +CONFIG_SYSTEM_MDIO=y +# CONFIG_SYSTEM_NETDB is not set +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_PRIORITY=100 +CONFIG_SYSTEM_NSH_STACKSIZE=2048 +CONFIG_SYSTEM_NTPC=y +CONFIG_SYSTEM_NTPC_PRIORITY=100 +CONFIG_SYSTEM_NTPC_STACKSIZE=2048 +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_PING_PRIORITY=100 +CONFIG_SYSTEM_PING_STACKSIZE=2048 +CONFIG_SYSTEM_POPEN=y +CONFIG_SYSTEM_POPEN_STACKSIZE=2048 +CONFIG_SYSTEM_POPEN_PRIORITY=100 +CONFIG_SYSTEM_RAMTEST=y +CONFIG_SYSTEM_RAMTEST_PRIORITY=100 +CONFIG_SYSTEM_RAMTEST_STACKSIZE=1024 +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +CONFIG_SYSTEM_SETLOGMASK=y +CONFIG_SYSTEM_SETLOGMASK_PRIORITY=100 +CONFIG_SYSTEM_SET_LOGMASK_STACKSIZE=2048 +# CONFIG_SYSTEM_SUDOKU is not set +CONFIG_SYSTEM_SYSTEM=y +CONFIG_SYSTEM_SYSTEM_STACKSIZE=2048 +CONFIG_SYSTEM_SYSTEM_PRIORITY=100 +CONFIG_SYSTEM_TEE=y +CONFIG_SYSTEM_TEE_STACKSIZE=1536 +CONFIG_SYSTEM_TEE_PRIORITY=100 +# CONFIG_SYSTEM_TELNET_CHATD is not set +CONFIG_SYSTEM_TELNET_CLIENT=y +CONFIG_SYSTEM_TELNET_CLIENT_STACKSIZE=2048 +CONFIG_SYSTEM_TELNET_CLIENT_PRIORITY=100 +# CONFIG_SYSTEM_TERMCURSES is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set + +# +# Testing +# +# CONFIG_TESTING_FSTEST is not set +# CONFIG_TESTING_NXFFS is not set +# CONFIG_TESTING_OSTEST is not set +# CONFIG_TESTING_SMART is not set +# CONFIG_TESTING_SMART_TEST is not set +# CONFIG_TESTING_UNITY is not set + +# +# Wireless Libraries and NSH Add-Ons +# + +# +# Bluetooth applications +# +# CONFIG_BTSAK is not set + +# +# IEEE 802.15.4 applications +# +# CONFIG_IEEE802154_LIBMAC is not set +# CONFIG_IEEE802154_LIBUTILS is not set +# CONFIG_IEEE802154_I8SAK is not set diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/include/board.h b/boards/arm/lpc17xx_40xx/lx_cpu/include/board.h new file mode 100644 index 00000000000..a37cdf39cc2 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/include/board.h @@ -0,0 +1,469 @@ +/************************************************************************************ + * boards/arm/lpc17xx_40xx/lx_cpu/include/board.h + * include/arch/board/board.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __BOARDS_ARM_LX_CPU_INCLUDE_BOARD_H +#define __BOARDS_ARM_LX_CPU_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC17_40_GPIOIRQ) +# include +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Clocking *************************************************************************/ +/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here + * because the including C file may not have that file in its include path. + */ + +#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */ +#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */ +#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency */ +#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */ +#define BOARD_WDTOSC_FREQUENCY (500000) /* WDT oscillator frequency */ + +/* This is the clock setup we configure for: + * + * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source + * PLL0CLK = (12 * SYSCLK) / 1 = 144MHz -> PLL0 multipler=12, pre-divider=1 + * CCLCK = 72MHz -> CCLK divider = 2 + */ + +#define LPC17_40_CCLK 72000000 /* 72Mhz */ +#define BOARD_PCLKDIV 2 /* Peripheral clock = LPC17_40_CCLK/2 */ +#define BOARD_PCLK_FREQUENCY (LPC17_40_CCLK * BOARD_CCLKSEL_DIVIDER / BOARD_PCLKDIV) + +/* Select the main oscillator as the frequency source. SYSCLK is then the frequency + * of the main oscillator. + * + * If BOARD_XTAL_FREQUENCY > 15000000, then the SCS OSCRS bit (bit 4) should also + * be set in the BOARD_SCS_VALUE. + */ + +#undef CONFIG_LPC17_40_MAINOSC +#define CONFIG_LPC17_40_MAINOSC 1 +#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN + +/* Select the main oscillator and CCLK divider. The output of the divider is CCLK. + * The input to the divider (PLLCLK) will be determined by the PLL output. + */ + +#define BOARD_CCLKSEL_DIVIDER 2 +#define BOARD_CCLKSEL_VALUE (BOARD_CCLKSEL_DIVIDER | SYSCON_CCLKSEL_CCLKSEL) + +/* PLL0. PLL0 is used to generate the CPU clock (PLLCLK). + * + * Source clock: Main oscillator + * PLL0 Multiplier value (M): 12 + * PLL0 Pre-divider value (P): 1 + * + * PLL0CLK = (M * SYSCLK) = 144MHz + */ + +#undef CONFIG_LPC17_40_PLL0 +#define CONFIG_LPC17_40_PLL0 1 +#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN + +#define BOARD_PLL0CFG_MSEL 12 +#define BOARD_PLL0CFG_PSEL 1 +#define BOARD_PLL0CFG_VALUE \ + (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \ + ((BOARD_PLL0CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT)) + +/* PLL1 : PLL1 is used to generate clock for the USB */ + +#undef CONFIG_LPC17_40_PLL1 +#define BOARD_PLL1CFG_MSEL 4 +#define BOARD_PLL1CFG_PSEL 2 +#define BOARD_PLL1CFG_VALUE \ + (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \ + ((BOARD_PLL1CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT)) + +#ifdef CONFIG_LPC17_40_EMC +/* EMC clock selection. + * + * The EMC clock should not be driven above 80MHz. As a result the EMC + * uses the CPU clock divided by two. + */ + +# define BOARD_EMCCLKSEL_DIVIDER 1 +# define BOARD_EMCCLKSEL_VALUE SYSCON_EMCCLKSEL_CCLK_DIV1 +# define LPC17_40_EMCCLK (LPC17_40_CCLK / BOARD_EMCCLKSEL_DIVIDER) + +# define BOARD_EMC_FPGA_SETUP + +# define BOARD_XC_PROGRAM_PIN (GPIO_PORT0 | GPIO_PIN8 | GPIO_OUTPUT | GPIO_VALUE_ONE) +# define BOARD_XC_DONE_PIN (GPIO_PORT0 | GPIO_PIN9 | GPIO_INPUT | GPIO_PULLUP) +# define BOARD_XC_INIT_PIN (GPIO_PORT0 | GPIO_PIN18 | GPIO_OUTPUT | GPIO_PULLUP | GPIO_OPEN_DRAIN) +# define BOARD_XC_SUSPEND_PIN (GPIO_PORT0 | GPIO_PIN20 | GPIO_OUTPUT | GPIO_VALUE_ONE) +# define BOARD_XC_RDWR_PIN (GPIO_PORT4 | GPIO_PIN16 | GPIO_OUTPUT | GPIO_VALUE_ZERO) + +#endif + +#if defined(CONFIG_LPC17_40_USBHOST) || (CONFIG_LPC17_40_USBDEV) +/* USB divider. The output of the PLL is used as the USB clock + * + * USBCLK = PLL1CLK = (SYSCLK * 4) = 48MHz + */ + +# define BOARD_USBCLKSEL_DIVIDER 1 +# define BOARD_USBCLKSEL_VALUE (SYSCON_USBCLKSEL_USBDIV_DIV1 | \ + SYSCON_USBCLKSEL_USBSEL_PLL0) +#endif + +#define GPIO_USB_DP GPIO_USB1DP +#define GPIO_USB_DM GPIO_USB1DM + +#define GPIO_USB_CONNECT GPIO_USB1_CONNECT + +#define GPIO_USB_OVRCR GPIO_USB2_OVRCR + +#define GPIO_USB_PPWR GPIO_USB_PPWR2 + +#define GPIO_USB_PWRD (GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN10) + +/* +#define GPIO_USB_PPWR +#define GPIO_USB_PWRD +#define GPIO_USB_OVRCR +*/ + +/* FLASH Configuration */ + +#undef CONFIG_LPC17_40_FLASH +#define CONFIG_LPC17_40_FLASH 1 + +/* Flash access use 4 CPU clocks - Safe for 72 MHz */ + +#define BOARD_FLASHCFG_VALUE SYSCON_FLASHCFG_TIM_3 + +/* Ethernet configuration */ + +#define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV20 + +#define GPIO_ENET_CRS (GPIO_ENET_CRSDV) +#define GPIO_ENET_MDC GPIO_ENET_MDC_1 +#define GPIO_ENET_MDIO GPIO_ENET_MDIO_1 + +/* CAN bus configuration */ + +#define GPIO_CAN2_RD GPIO_CAN2_RD_1 +#define GPIO_CAN2_TD GPIO_CAN2_TD_1 + +#ifdef CONFIG_LPC17_40_SDCARD +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. + * SDCARD_CLOCK=PCLK/(2*(SDCARD_CLKDIV+1)) + */ + +# define SDCARD_CLKDIV_INIT 74 /* 400Khz */ +# define SDCARD_INIT_CLKDIV (SDCARD_CLKDIV_INIT) + +# define SDCARD_NORMAL_CLKDIV 1 /* DMA ON: SDCARD_CLOCK=15MHz */ +#define SDCARD_SLOW_CLKDIV 14 /* DMA OFF: SDCARD_CLOCK=2MHz */ + +# ifdef CONFIG_SDIO_DMA +# define SDCARD_MMCXFR_CLKDIV (SDCARD_NORMAL_CLKDIV) +# else +# define SDCARD_MMCXFR_CLKDIV (SDCARD_SLOW_CLKDIV) +# endif + +# ifdef CONFIG_SDIO_DMA +# define SDCARD_SDXFR_CLKDIV (SDCARD_NORMAL_CLKDIV) +# else +# define SDCARD_SDXFR_CLKDIV (SDCARD_SLOW_CLKDIV) +# endif +#endif + +/* Set EMC delay values: + * + * CMDDLY: Programmable delay value for EMC outputs in command delayed + * mode. The delay amount is roughly CMDDLY * 250 picoseconds. + * FBCLKDLY: Programmable delay value for the feedback clock that controls + * input data sampling. The delay amount is roughly (FBCLKDLY+1) * 250 + * picoseconds. + * CLKOUT0DLY: Programmable delay value for the CLKOUT0 output. This would + * typically be used in clock delayed mode. The delay amount is roughly + * (CLKOUT0DLY+1) * 250 picoseconds. + * CLKOUT1DLY: Programmable delay value for the CLKOUT1 output. This would + * typically be used in clock delayed mode. The delay amount is roughly + * (CLKOUT1DLY+1) * 250 picoseconds. + * + * Optimal for NOR: {1,1,1,1} + * Needed for NAND and SDRAM: {17,1,2,1} + */ + +#ifdef CONFIG_LPC17_40_EMC +#if defined(CONFIG_LPC17_40_EXTNAND) || defined(CONFIG_LPC17_40_EXTDRAM) +# define BOARD_CMDDLY 16 +# define BOARD_FBCLKDLY 16 +# define BOARD_CLKOUT0DLY 1 +# define BOARD_CLKOUT1DLY 1 +#else +# define BOARD_CMDDLY 1 +# define BOARD_FBCLKDLY 1 +# define BOARD_CLKOUT0DLY 1 +# define BOARD_CLKOUT1DLY 1 +#endif +#endif + +#define BOARD_NADDR 16 +#define BOARD_NDATA 32 + +//#define BOARD_EMC_CONFIG_BY_LOADER 1 + +/* LED definitions ******************************************************************/ +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + * + * LED1 -- Connected to P1[29] RED + * LED2 -- Connected to P0[16] GREEN + * + * These LEDs are connecte to ground so a high output value will illuminate them. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the four LEDs + * on the WaveShare Open1788K. The following definitions describe how NuttX + * controls the LEDs: + */ + /* LED1 LED2 LED3 LED4 */ +#define LED_STARTED 0 /* OFF OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* ON OFF OFF OFF */ +#define LED_IRQSENABLED 2 /* OFF ON OFF OFF */ +#define LED_STACKCREATED 3 /* ON ON OFF OFF */ +#define LED_INIRQ 4 /* LED3 glows, on while in interrupt */ +#define LED_SIGNAL 4 /* LED3 glows, on while in signal handler */ +#define LED_ASSERTION 4 /* LED3 glows, on while in assertion */ +#define LED_PANIC 4 /* LED3 Flashes at 2Hz */ +#define LED_IDLE 5 /* LED4 glows: ON while active * + * OFF while sleeping */ + +/* Button definitions ***************************************************************/ +/* The LX_CPU supports several buttons. All must be pulled up by the LX_CPU. + * When closed, the pins will be pulled to ground. So the buttons will read "1" + * when open and "0" when closed. All except USER1 are capable of generating + * interrupts. + * + * USER1 -- Connected to P4[26] + * USER2 -- Connected to P2[22] + * USER3 -- Connected to P0[10] + * + * And a Joystick + * + * JOY_A -- Connected to P2[25] + * JOY_B -- Connected to P2[26] + * JOY_C -- Connected to P2[23] + * JOY_D -- Connected to P2[19] + * JOY_CTR -- Connected to P0[14] (shared with SSP1 SSEL) + * + * For the interrupting buttons, interrupts are generated on both edges (press and + * release). + */ + + +#define BOARD_BUTTON_USER1 0 +#define BOARD_BUTTON_USER2 1 +#define BOARD_BUTTON_USER3 2 + +#define BOARD_JOYSTICK_A 3 +#define BOARD_JOYSTICK_B 4 +#define BOARD_JOYSTICK_C 5 +#define BOARD_JOYSTICK_D 6 +#define BOARD_JOYSTICK_CTR 7 + +#define NUM_BUTTONS 8 + +#define BOARD_BUTTON_USER1_BIT (1 << BOARD_BUTTON_USER1) +#define BOARD_BUTTON_USER2_BIT (1 << BOARD_BUTTON_USER2) +#define BOARD_BUTTON_USER3_BIT (1 << BOARD_BUTTON_USER3) + +#define BOARD_JOYSTICK_A_BIT (1 << BOARD_JOYSTICK_A) +#define BOARD_JOYSTICK_B_BIT (1 << BOARD_JOYSTICK_B) +#define BOARD_JOYSTICK_C_BIT (1 << BOARD_JOYSTICK_C) +#define BOARD_JOYSTICK_D_BIT (1 << BOARD_JOYSTICK_D) +#define BOARD_JOYSTICK_CTR_BIT (1 << BOARD_JOYSTICK_CTR) + +/* Alternate pin selections *********************************************************/ + +/* UART0: + * + * TX --- Connected to P0[2] + * RX --- Connected to P0[3] + */ + +#define GPIO_UART0_TXD GPIO_UART0_TXD_2 +#define GPIO_UART0_RXD GPIO_UART0_RXD_2 + +/* UART1: + * + * All pin options are controlled by older briges on the bottom of the board. There + * are the default settings on my board as it came out of the box: + * + * RTS --- Connected to P0[22] + * DSR --- Connected to P0[19] + * CTS --- Connected to P0[17] + * TXD --- Connected to P0[15] + * RXD --- Connected to P0[16] (Shared with LED2) + */ + +#define GPIO_UART1_RTS GPIO_UART1_RTS_2 +#define GPIO_UART1_DSR GPIO_UART1_DSR_1 +#define GPIO_UART1_CTS GPIO_UART1_CTS_1 +#define GPIO_UART1_TXD GPIO_UART1_TXD_1 +#define GPIO_UART1_RXD GPIO_UART1_RXD_1 + +/* MCI-SDIO: + * + * D0 --- Connected to P1[6] + * D1 --- Connected to P2[11] + * D2 --- Connected to P2[12] + * D3 --- Connected to P2[13] + * CLK --- Connected to P1[2] + * CMD --- Connected to P1[3] + */ + +#define GPIO_SD_DAT0 GPIO_SD_DAT0_2 +#define GPIO_SD_DAT1 GPIO_SD_DAT1_2 +#define GPIO_SD_DAT2 GPIO_SD_DAT2_2 +#define GPIO_SD_DAT3 GPIO_SD_DAT3_2 +#define GPIO_SD_CLK GPIO_SD_CLK_2 +#define GPIO_SD_CMD GPIO_SD_CMD_2 + +/* LCD R: + * + * VD0 --- Connected to P0[4] + * VD1 --- Connected to P0[5] + * VD2 --- Connected to P4[28] + * VD3 --- Connected to P4[29] + * VD4 --- Connected to P2[6] + * VD5 --- Connected to P2[7] + * VD6 --- Connected to P2[8] + * VD7 --- Connected to P2[9] + */ + +#define GPIO_LCD_VD0 GPIO_LCD_VD0_1 +#define GPIO_LCD_VD1 GPIO_LCD_VD1_1 +#define GPIO_LCD_VD2 GPIO_LCD_VD2_2 +#define GPIO_LCD_VD3 GPIO_LCD_VD3_3 +#define GPIO_LCD_VD4 GPIO_LCD_VD4_1 +#define GPIO_LCD_VD5 GPIO_LCD_VD5_1 +#define GPIO_LCD_VD6 GPIO_LCD_VD6_2 +#define GPIO_LCD_VD7 GPIO_LCD_VD7_2 + +/* LCD G: + * + * VD8 --- Connected to P0[6] + * VD9 --- Connected to P0[7] + * VD10 --- Connected to P1[20] + * VD11 --- Connected to P1[21] + * VD12 --- Connected to P1[22] + * VD13 --- Connected to P1[23] + * VD14 --- Connected to P1[24] + * VD15 --- Connected to P1[25] + */ + +#define GPIO_LCD_VD8 GPIO_LCD_VD8_1 +#define GPIO_LCD_VD9 GPIO_LCD_VD9_1 +#define GPIO_LCD_VD10 GPIO_LCD_VD10_1 +#define GPIO_LCD_VD11 GPIO_LCD_VD11_1 +#define GPIO_LCD_VD12 GPIO_LCD_VD12_1 +#define GPIO_LCD_VD13 GPIO_LCD_VD13_1 +#define GPIO_LCD_VD14 GPIO_LCD_VD14_1 +#define GPIO_LCD_VD15 GPIO_LCD_VD15_1 + +/* LCD B: + * + * VD16 --- Connected to P0[8] + * VD17 --- Connected to P0[9] + * VD18 --- Connected to P2[12] + * VD19 --- Connected to P2[13] + * VD20 --- Connected to P1[26] + * VD21 --- Connected to P1[27] + * VD22 --- Connected to P1[28] + * VD23 --- Connected to P1[29] + * + * DCLK --- Connected to P2[2] + * LP --- Connected to P2[5] + * FP --- Connected to P2[3] + * ENAB_M --- Connected to P2[4] + * PWR --- Connected to P2[0] + */ + +#define GPIO_SSP0_SCK GPIO_SSP0_SCK_3 +#define GPIO_SSP0_MISO GPIO_SSP0_MISO_2 +#define GPIO_SSP0_MOSI GPIO_SSP0_MOSI_4 + +/* XPT2046 Touchscreen: + * +/* -------------- -------------------- ------------ -------------------------------- + * XTPT2046 Module Module LX_CPU LED + * Signal Connector Connector + * -------------- -------------------- ------------ --------------------------------- + * Pin 11 PENIRQ\ PENIRQ (pulled high) PORT3 Pin 1 P2.15 PENIRQ + * Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP LED) + * Pin 13 BUSY BUSY (pulled high) PORT3 Pin 9 P2.14 BUSY + * Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device up LED and SD CD pin) + * Pin 15 CS\ SSEL (pulled high) PORT3 Pin 6 P1.8 GPIO (Also RMII_CRS_DV) + * Pin 16 DCLK SCK PORT3 Pin 5 P1.19 SCK1 + * -------------- -------------------- ------------ --------------------------------- + */ + + +#define GPIO_SSP1_MISO GPIO_SSP1_MISO_3 +#define GPIO_SSP1_MOSI GPIO_SSP1_MOSI_2 +#define GPIO_SSP1_SCK GPIO_SSP1_SCK_2 + +#endif /* __BOARDS_ARM_LX_CPU_INCLUDE_BOARD_H */ diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/scripts/Make.defs b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/Make.defs new file mode 100644 index 00000000000..eacec41e189 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/Make.defs @@ -0,0 +1,153 @@ +############################################################################ +# boards/arm/lpc17xx_40xx/lx_cpu/nsh/Make.defs +# +# Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}$(DELIM)arch$(DELIM)arm$(DELIM)src$(DELIM)armv7-m$(DELIM)Toolchain.defs + +# Setup for the kind of memory that we are executing from + +ifeq ($(CONFIG_LX_CPU_BOOT_FLASH_APP),y) + LDSCRIPT = link-flash-app.ld +endif +ifeq ($(CONFIG_LX_CPU_BOOT_FLASH_BOOT),y) + LDSCRIPT = link-flash-boot.ld +endif +ifeq ($(CONFIG_LX_CPU_BOOT_SDRAM),y) + LDSCRIPT = link-sdram.ld +endif + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)$(DELIM)tools$(DELIM)copydir.sh + DIRUNLINK = $(TOPDIR)$(DELIM)tools$(DELIM)unlink.sh + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include}" -isystem "${shell cygpath -w $(TOPDIR)$(DELIM)include$(DELIM)cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)$(DELIM)boards$(DELIM)$(CONFIG_ARCH)$(DELIM)$(CONFIG_ARCH_CHIP)$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)$(DELIM)include -isystem $(TOPDIR)$(DELIM)include$(DELIM)cxx + ARCHSCRIPT = -T$(TOPDIR)$(DELIM)boards$(DELIM)$(CONFIG_ARCH)$(DELIM)$(CONFIG_ARCH_CHIP)$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +# NXFLAT module definitions + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) -mlong-calls # --target1-abs +CXXELFFLAGS = $(CXXFLAGS) -mlong-calls # --target1-abs + +LDELFFLAGS = -r -e main +ifeq ($(WINTOOL),y) + LDELFFLAGS += -T "${shell cygpath -w $(TOPDIR)$(DELIM)boards$(DELIM)$(CONFIG_ARCH)$(DELIM)$(CONFIG_ARCH_CHIP)$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)gnu-elf.ld}" +else + LDELFFLAGS += -T $(TOPDIR)$(DELIM)boards$(DELIM)$(CONFIG_ARCH)$(DELIM)$(CONFIG_ARCH_CHIP)$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)gnu-elf.ld +endif + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +# File extensions + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +# Linker flags + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +# Host tools + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/scripts/gnu-elf.ld b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/gnu-elf.ld new file mode 100644 index 00000000000..2e9357ec495 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/gnu-elf.ld @@ -0,0 +1,139 @@ +/**************************************************************************** + * configs/stm32f4discovery/scripts/gnu-elf.ld + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +SECTIONS +{ + .text 0x00000000 : + { + _stext = . ; + *(.text) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.glue_7) + *(.glue_7t) + *(.jcr) + + /* C++ support: The .init and .fini sections contain specific logic + * to manage static constructors and destructors. + */ + + *(.gnu.linkonce.t.*) + *(.init) /* Old ABI */ + *(.fini) /* Old ABI */ + _etext = . ; + } + + .ARM.extab : + { + *(.ARM.extab*) + } + + .ARM.exidx : + { + *(.ARM.exidx*) + } + + .rodata : + { + _srodata = . ; + *(.rodata) + *(.rodata1) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = . ; + } + + .data : + { + _sdata = . ; + *(.data) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + _edata = . ; + } + + /* C++ support. For each global and static local C++ object, + * GCC creates a small subroutine to construct the object. Pointers + * to these routines (not the routines themselves) are stored as + * simple, linear arrays in the .ctors section of the object file. + * Similarly, pointers to global/static destructor routines are + * stored in .dtors. + */ + + .ctors : + { + _sctors = . ; + *(.ctors) /* Old ABI: Unallocated */ + *(.init_array) /* New ABI: Allocated */ + _edtors = . ; + } + + .dtors : + { + _sdtors = . ; + *(.dtors) /* Old ABI: Unallocated */ + *(.fini_array) /* New ABI: Allocated */ + _edtors = . ; + } + + .bss : + { + _sbss = . ; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b*) + *(COMMON) + _ebss = . ; + } + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/scripts/kernel-space.ld b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/kernel-space.ld new file mode 100644 index 00000000000..a07cfc5f5ab --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/kernel-space.ld @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/lpc17xx_40xx/lx_cpu/scripts/kernel-space.ld + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + . = ALIGN(4); + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + . = ALIGN(4); + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + . = ALIGN(4); + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-flash-app.ld b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-flash-app.ld new file mode 100644 index 00000000000..c97b0b219c4 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-flash-app.ld @@ -0,0 +1,134 @@ +/**************************************************************************** + * boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-flash-app.ld + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC1788 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 96Kb of total SRAM: 64Kb of SRAM in the CPU block beginning at address + * 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8Kb at addresses + * 0x20000000 bank0 first and 8kb at 0x20002000 at bank0 second. And 16Kb + * at 0x20004000 on bank1. + * + * Here we assume that .data and .bss will all fit into the 64Kb CPU SRAM + * address range. + */ + +MEMORY +{ + FLASHBOOT (rx) : ORIGIN = 0x00000000, LENGTH = 0x00007000 + KEYVAL (rx) : ORIGIN = 0x00007000, LENGTH = 0x00002000 + FLASH (rx) : ORIGIN = 0x00009000, LENGTH = 0x00077000 + SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K + AHBRAM8_B0A(rwx): ORIGIN = 0x20000000, LENGTH = 8K + AHBRAM8_B0B(rwx): ORIGIN = 0x20002000, LENGTH = 8K + AHBRAM16(rwx): ORIGIN = 0x20004000, LENGTH = 16K + /* External SDRAM - 32MB for LX_CPU */ + SDRAM (rwx) : ORIGIN = 0xA0000000, LENGTH = 32M +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > FLASH + + . = ALIGN(4); + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > FLASH + + .ARM.extab : { + *(.ARM.extab*) + } > FLASH + + . = ALIGN(4); + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > FLASH + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + . = ALIGN(4); + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > SRAM AT > FLASH + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > SRAM + + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-flash-boot.ld b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-flash-boot.ld new file mode 100644 index 00000000000..e43c7c08835 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-flash-boot.ld @@ -0,0 +1,132 @@ +/**************************************************************************** + * boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-flash-boot.ld + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC1788 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 96Kb of total SRAM: 64Kb of SRAM in the CPU block beginning at address + * 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8Kb at addresses + * 0x20000000 bank0 first and 8kb at 0x20002000 at bank0 second. And 16Kb + * at 0x20004000 on bank1. + * + * Here we assume that .data and .bss will all fit into the 64Kb CPU SRAM + * address range. + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K + SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K + AHBRAM8_B0A(rwx): ORIGIN = 0x20000000, LENGTH = 8K + AHBRAM8_B0B(rwx): ORIGIN = 0x20002000, LENGTH = 8K + AHBRAM16(rwx): ORIGIN = 0x20004000, LENGTH = 16K + /* External SDRAM - 32MB for LX_CPU */ + SDRAM (rwx) : ORIGIN = 0xA0000000, LENGTH = 32M +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > FLASH + + . = ALIGN(4); + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > FLASH + + .ARM.extab : { + *(.ARM.extab*) + } > FLASH + + . = ALIGN(4); + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > FLASH + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + . = ALIGN(4); + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > SRAM AT > FLASH + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > SRAM + + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-sdram.ld b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-sdram.ld new file mode 100644 index 00000000000..50631920320 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-sdram.ld @@ -0,0 +1,132 @@ +/**************************************************************************** + * boards/arm/lpc17xx_40xx/lx_cpu/scripts/link-sdram.ld + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC1788 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 96Kb of total SRAM: 64Kb of SRAM in the CPU block beginning at address + * 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8Kb at addresses + * 0x20000000 bank0 first and 8kb at 0x20002000 at bank0 second. And 16Kb + * at 0x20004000 on bank1. + * + * Here we assume that .data and .bss will all fit into the 64Kb CPU SRAM + * address range. + */ + +MEMORY +{ + FLASHBOOT (rx) : ORIGIN = 0x00000000, LENGTH = 0x00007000 + KEYVAL (rx) : ORIGIN = 0x00007000, LENGTH = 0x00002000 + FLASH (rx) : ORIGIN = 0x00009000, LENGTH = 0x00077000 + SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K + AHBRAM8_B0A(rwx): ORIGIN = 0x20000000, LENGTH = 8K + AHBRAM8_B0B(rwx): ORIGIN = 0x20002000, LENGTH = 8K + AHBRAM16(rwx): ORIGIN = 0x20004000, LENGTH = 16K + /* External SDRAM - 32MB for LX_CPU */ + SDRAM (rwx) : ORIGIN = 0xA0000000, LENGTH = 32M + +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > SDRAM + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > SDRAM + + .ARM.extab : { + *(.ARM.extab*) + } > SDRAM + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > SDRAM + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > SRAM AT > SDRAM + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > SRAM + + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/scripts/memory.ld b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/memory.ld new file mode 100644 index 00000000000..d04ffb60577 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/memory.ld @@ -0,0 +1,98 @@ +/**************************************************************************** + * boards/arm/lpc17xx_40xx/lx_cpu/scripts/memory.ld + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC1788 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 96KB of total SRAM: 64KB of SRAM in the CPU block beginning at address + * 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8KB at addresses + * 0x20000000 bank0 first and 8KB at 0x20002000 at bank0 second. And 16KB + * at 0x20004000 on bank1. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 64KB of + * FLASH and 4KB of SRAM. That, of course, can be optimized as needed (See + * also boards/arm/lpc17xx_40xx/lx_cpu/scripts/kernel-space.ld). + * + * Alignment of the user space FLASH partition is a critical factor: The + * user space FLASH partition will be spanned with a single region of size + * 2**n bytes. The alignment of the user-space region must be the same. As + * a consequence, as the user-space increases in size, the alignmment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 256KB at it would have to be positioned at + * 0x00400000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 64KB CPU SRAM region is as follows: + * + * 0x10000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x10000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x10000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * ------- ---- Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * 0x10000 8000: Beginning of user heap. Can vary with other settings. + * 0x10001 0000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 256Kb FLASH */ + + kflash (rx) : ORIGIN = 0x00000000, LENGTH = 64K + uflash (rx) : ORIGIN = 0x00010000, LENGTH = 64K + xflash (rx) : ORIGIN = 0x00010000, LENGTH = 384K + + /* 64Kb of SRAM in the CPU block */ + + ksram (rwx) : ORIGIN = 0x10000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x10001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x10001000, LENGTH = 56K + + /* Other peripheral memory (free, nothing is linked here) */ + + ahbram8_b0a(rwx) : ORIGIN = 0x20000000, LENGTH = 8K + ahbram8_b0b(rwx) : ORIGIN = 0x20002000, LENGTH = 8K + ahbram16(rwx) : ORIGIN = 0x20004000, LENGTH = 16K +} diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/scripts/user-space.ld b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/user-space.ld new file mode 100644 index 00000000000..c7f16c1f5ce --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/scripts/user-space.ld @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/lpc17xx_40xx/lx_cpu/scripts/user-space.ld + * + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + . = ALIGN(4); + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + . = ALIGN(4); + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + . = ALIGN(4); + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/.gitignore b/boards/arm/lpc17xx_40xx/lx_cpu/src/.gitignore new file mode 100644 index 00000000000..726d936e1e3 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/Makefile b/boards/arm/lpc17xx_40xx/lx_cpu/src/Makefile new file mode 100644 index 00000000000..a60945aeb65 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/Makefile @@ -0,0 +1,71 @@ +############################################################################ +# boards/arm/lpc17xx_40xx/lx_cpu/src/Makefile +# +# Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = lpc17_40_boardinitialize.c lpc17_40_bringup.c lpc17_40_ssp.c + +ifeq ($(CONFIG_LPC17_40_EMC),y) +ifeq ($(CONFIG_LPC17_40_EXTDRAM),y) + CSRCS += lpc17_40_sdraminitialize.c +endif + + CSRCS += lpc17_40_fpgainitialize.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) + CSRCS += lpc17_40_appinit.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) + CSRCS += lpc17_40_composite.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) + CSRCS += lpc17_40_autoleds.c +else + CSRCS += lpc17_40_userleds.c +endif + +ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += lpc17_40_reset.c +endif + +ifeq ($(CONFIG_CAN),y) +CSRCS += lpc17_40_can.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_appinit.c b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_appinit.c new file mode 100644 index 00000000000..395dc70f2c0 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_appinit.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_appinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "lx_cpu.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return lx_cpu_bringup(); +#endif +} diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_autoleds.c b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_autoleds.c new file mode 100644 index 00000000000..38801f95d6a --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_autoleds.c @@ -0,0 +1,239 @@ +/**************************************************************************** + * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_autoleds.c + * + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc17_40_gpio.h" +#include "lx_cpu.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + * + * LED1 -- Connected to P1[29] + * LED2 -- Connected to P0[16] + * + * These LEDs are connected to ground so a high output value will illuminate them. + * + * If CONFIG_ARCH_LEDs is defined, then NuttX will control the four LEDs + * on the WaveShare Open1788K. The following definitions describe how NuttX + * controls the LEDs: + * + * LED1 LED2 LED3 LED4 + * LED_STARTED 0 OFF OFF OFF OFF + * LED_HEAPALLOCATE 1 ON OFF OFF OFF + * LED_IRQSENABLED 2 OFF ON OFF OFF + * LED_STACKCREATED 3 ON ON OFF OFF + * LED_INIRQ 4 LED3 glows, on while in interrupt + * LED_SIGNAL 4 LED3 glows, on while in signal handler + * LED_ASSERTION 4 LED3 glows, on while in assertion + * LED_PANIC 4 LED3 Flashes at 2Hz + * LED_IDLE 5 LED glows, ON while sleeping + */ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define LX_CPU_LED1 (1 << 0) +#define LX_CPU_LED2 (1 << 1) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((0) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((LX_CPU_LED1|LX_CPU_LED2) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((LX_CPU_LED1|LX_CPU_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((LX_CPU_LED1) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((LX_CPU_LED2) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((LX_CPU_LED1|LX_CPU_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((LX_CPU_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((LX_CPU_LED1) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((LX_CPU_LED1) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((LX_CPU_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((LX_CPU_LED1|LX_CPU_LED2) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((LX_CPU_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((LX_CPU_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_EVENT_ON_SETBITS ((0) << ON_SETBITS_SHIFT) +#define LED_EVENT_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_EVENT_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_EVENT_OFF_CLRBITS ((0) << OFF_CLRBITS_SHIFT) + +#define LED_IDLE_ON_SETBITS ((0) << ON_SETBITS_SHIFT) +#define LED_IDLE_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_IDLE_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_IDLE_OFF_CLRBITS ((0) << OFF_CLRBITS_SHIFT) + +/* Dump GPIO registers */ + +#ifdef CONFIG_DEBUG_LEDS_INFO +# define led_dumpgpio(m) lpc17_40_dumpgpio(???, m) +#else +# define led_dumpgpio(m) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_EVENT_ON_SETBITS | LED_EVENT_ON_CLRBITS | + LED_EVENT_OFF_SETBITS | LED_EVENT_OFF_CLRBITS), + + (LED_IDLE_ON_SETBITS | LED_IDLE_ON_CLRBITS | + LED_IDLE_OFF_SETBITS | LED_IDLE_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & LX_CPU_LED1) != 0) + { + lpc17_40_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & LX_CPU_LED2) != 0) + { + lpc17_40_gpiowrite(GPIO_LED2, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & LX_CPU_LED1) != 0) + { + lpc17_40_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & LX_CPU_LED2) != 0) + { + lpc17_40_gpiowrite(GPIO_LED2, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + lpc17_40_configgpio(GPIO_LED1); + lpc17_40_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_boardinitialize.c b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_boardinitialize.c new file mode 100644 index 00000000000..f396507ae11 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_boardinitialize.c @@ -0,0 +1,135 @@ +/************************************************************************************ + * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_boardinitialize.c + * + * Copyright (C) 2013, 2015, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc17_40_emc.h" + +#include "lx_cpu.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_40_boardinitialize + * + * Description: + * All LPC17xx architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void lpc17_40_boardinitialize(void) +{ + /* Initialize the EMC, and SDRAM */ + +#ifndef BOARD_EMC_CONFIG_BY_LOADER + +#ifdef CONFIG_LPC17_40_EMC + lpc17_40_emcinitialize(); + + lx_cpu_fpga_initialize(); + +#ifdef CONFIG_LPC17_40_EXTDRAM + lx_cpu_sdram_initialize(); +#endif + +#endif + +#endif /*BOARD_EMC_CONFIG_BY_LOADER*/ + +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) || \ + defined(CONFIG_LPC17_40_SSP2) + /* Configure SSP chip selects if 1) at least one SSP is enabled, and 2) + * the weak function lx_cpu_sspdev_initialize() has been brought into + * the link. + */ + + if (lx_cpu_sspdev_initialize) + { + lx_cpu_sspdev_initialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board-specific initialization */ + + (void)lx_cpu_bringup(); +} +#endif diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_bringup.c b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_bringup.c new file mode 100644 index 00000000000..a368c66524a --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_bringup.c @@ -0,0 +1,423 @@ +/**************************************************************************** + * config/lx_cpu/src/lpc17_40_bringup.c + * + * Copyright (C) 2013, 2016-2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "lpc17_40_gpio.h" +#include "lpc17_40_sdcard.h" +#include "lpc17_40_usbhost.h" +#include "lx_cpu.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#define NSH_HAVE_MMCSD 1 +#define NSH_HAVE_USBHOST 1 +#define NSH_HAVE_USBHDEV 1 + +#undef NSH_HAVE_MMCSD_CD +#undef NSH_HAVE_MMCSD_CDINT + +/* MMC/SD support */ + +#if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && !defined(CONFIG_MMCD_SDIO) +# undef NSH_HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef NSH_HAVE_MMCSD +#endif + +/* MMC/SD support requires that an SPI support is enabled and an SPI port is selected */ + +#ifdef NSH_HAVE_MMCSD +# if !defined(CONFIG_NSH_MMCSDSLOTNO) +# warning "Assuming slot MMC/SD slot 0" +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#endif + +#ifdef NSH_HAVE_MMCSD +# if !defined(CONFIG_NSH_MMCSDMINOR) +# warning "Assuming /dev/mmcsd0" +# define CONFIG_NSH_MMCSDMINOR 0 +# endif +#endif + +/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It is also + * used for MOSI1 and USB_UP_LED. The CD pin may be disconnected. There is a jumper + * on board that enables the CD pin. + */ + +#ifdef NSH_HAVE_MMCSD +# ifdef CONFIG_MMCSD_HAVE_CARDDETECT +# define NSH_HAVE_MMCSD_CD 1 +# ifdef CONFIG_LPC17_40_GPIOIRQ +# define NSH_HAVE_MMCSD_CDINT 1 +# endif +# endif +#endif + +#if defined(NSH_HAVE_MMCSD_CD) && \ + (defined(CONFIG_LPC17_40_SSP1) || defined(CONFIG_LPC17_40_USBDEV)) +# warning "Use of SD Card Detect pin conflicts with SSP1 and/or USB device" +#endif + +/* USB Host */ + +#ifndef CONFIG_USBHOST +# undef NSH_HAVE_USBHOST +#endif + +#ifndef CONFIG_LPC17_40_USBHOST +# undef NSH_HAVE_USBHOST +#endif + +#ifdef NSH_HAVE_USBHOST +# ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +# endif +# ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +# endif +#endif + +/* USB Device */ + +#ifndef CONFIG_USBDEV +# undef NSH_HAVE_USBDEV +#endif + +#ifndef CONFIG_LPC17_40_USBDEV +# undef NSH_HAVE_USBDEV +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef NSH_HAVE_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif +#ifdef NSH_HAVE_MMCSD +static FAR struct sdio_dev_s *g_sdiodev; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_USBHOST +static int nsh_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + syslog(LOG_INFO, "nsh_waiter: Running\n"); + for (;;) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + syslog(LOG_INFO, "nsh_waiter: %s\n", + hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + (void)CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Name: nsh_cdinterrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_MMCSD_CDINT +static int nsh_cdinterrupt(int irq, FAR void *context, FAR void *arg) +{ + static bool inserted = 0xff; /* Impossible value */ + bool present; + + present = !lpc17_40_gpioread(GPIO_SD_CD); + if (present != inserted) + { + sdio_mediachange(g_sdiodev, present); + inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: nsh_sdinitialize + * + * Description: + * Initialize SPI-based microSD. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_MMCSD +static int nsh_sdinitialize(void) +{ + int ret; + +#ifdef NSH_HAVE_MMCSD_CD + /* Configure the SD card detect GPIO */ + + lpc17_40_configgpio(GPIO_SD_CD); + +#ifdef NSH_HAVE_MMCSD_CDINT + /* Attach an interrupt handler to get notifications when a card is + * inserted or deleted. + */ + + (void)irq_attach(LPC17_40_IRQ_P0p13, nsh_cdinterrupt, NULL); + up_enable_irq(LPC17_40_IRQ_P0p13); + +#endif +#endif + + /* First, get an instance of the SDIO interface */ + + g_sdiodev = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_sdiodev) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdiodev); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + /* Check if there is a card in the slot and inform the SDCARD driver. If + * we do not support the card detect, then let's assume that there is + * one. + */ + +#ifdef NSH_HAVE_MMCSD_CD + sdio_mediachange(g_sdiodev, !lpc17_40_gpioread(GPIO_SD_CD)); +#else + sdio_mediachange(g_sdiodev, true); +#endif + return OK; +} +#else +# define nsh_sdinitialize() (OK) +#endif + +/**************************************************************************** + * Name: nsh_usbhostinitialize + * + * Description: + * Initialize SPI-based microSD. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_USBHOST +static int nsh_usbhostinitialize(void) +{ + int pid; + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + syslog(LOG_INFO, "Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB host Mass Storage Class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + syslog(LOG_INFO, "Initialize USB host\n"); + g_usbconn = lpc17_40_usbhost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + syslog(LOG_INFO, "Start nsh_waiter\n"); + + pid = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + (main_t)nsh_waiter, (FAR char * const *)NULL); + return pid < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#else +# define nsh_usbhostinitialize() (OK) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lx_cpu_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library via boardctl() + * + ****************************************************************************/ + +int lx_cpu_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system at the default location, /proc */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs: %d\n", ret); + } +#endif + + /* Initialize SPI-based microSD */ + + ret = nsh_sdinitialize(); + if (ret == OK) + { + /* Initialize USB host */ + + ret = nsh_usbhostinitialize(); + } + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = lx_cpu_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: lx_xpu_can_setup failed: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_can.c b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_can.c new file mode 100644 index 00000000000..09b68f6daf2 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_can.c @@ -0,0 +1,137 @@ +/************************************************************************************ + * boards/zkit-arm-1769/src/lpc17_40_can.c + * + * Copyright (C) 2013 Zilogic Systems. All rights reserved. + * Author: Raashid Muhammed + * + * Based on boards/olimex-lpc1766stk/src/lpc17_40_can.c + * + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" + +#include "lpc17_40_can.h" +#include "lx_cpu.h" + +#ifdef CONFIG_CAN + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ + +#define CAN_PORT1 1 +#define CAN_PORT2 2 + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: zkit_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ************************************************************************************/ + +int lx_cpu_can_setup(void) +{ +#if defined(CONFIG_LPC17_40_CAN1) || defined(CONFIG_LPC17_40_CAN2) + struct can_dev_s *can; + int ret; + +#ifdef CONFIG_LPC17_40_CAN1 + /* Call lpc17_40_caninitialize() to get an instance of the CAN1 interface */ + + can = lpc17_40_caninitialize(CAN_PORT1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN1 interface\n"); + return -ENODEV; + } + + /* Register the CAN1 driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: CAN1 register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_LPC17_40_CAN2 + /* Call lpc17_40_caninitialize() to get an instance of the CAN2 interface */ + + can = lpc17_40_caninitialize(CAN_PORT2); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN2 interface\n"); + return -ENODEV; + } + + /* Register the CAN2 driver at "/dev/can1" */ + +#ifndef CONFIG_LPC17_40_CAN1 + ret = can_register("/dev/can0", can); +#else + ret = can_register("/dev/can1", can); +#endif + if (ret < 0) + { + canerr("ERROR: CAN2 register failed: %d\n", ret); + return ret; + } +#endif + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_composite.c b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_composite.c new file mode 100644 index 00000000000..8ee206f72f9 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_composite.c @@ -0,0 +1,148 @@ +/***************************************************************************** + * boards/pnev5180b/src/lpc17_40_composite.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Michael Jung + * + * Configure and register CDC-ACM and CDC-ECM + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) + +/***************************************************************************** + * Public Functions + *****************************************************************************/ + +/***************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + *****************************************************************************/ + +int board_composite_initialize(int port) +{ + syslog(LOG_INFO, "board_composite_initialize(port: %d)\n", port); + + return OK; +} + +/***************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + *****************************************************************************/ + +FAR void *board_composite_connect(int port, int configid) +{ + struct composite_devdesc_s dev[2]; + int ifnobase = 0; + int strbase = COMPOSITE_NSTRIDS; + + syslog(LOG_INFO, "board_composite_connect(port: %d, configid: %d)\n", + port, configid); + + /* Configure the CDC/ACM device */ + + /* Ask the cdcacm driver to fill in the constants we didn't + * know here. + */ + + cdcacm_get_composite_devdesc(&dev[0]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[0].classobject = cdcacm_classobject; + dev[0].uninitialize = cdcacm_uninitialize; + + /* Interfaces */ + + dev[0].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[0].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[0].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[0].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; + dev[0].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 5; + dev[0].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 2; + + /* Count up the base numbers */ + + ifnobase += dev[0].devinfo.ninterfaces; + strbase += dev[0].devinfo.nstrings; + + /* Configure the CDC/ECM device */ + + cdcecm_get_composite_devdesc(&dev[1]); + + dev[1].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[1].devinfo.strbase = strbase; /* Offset to String Numbers */ + dev[1].minor = 0; /* The minor interface number */ + dev[1].devinfo.epno[CDCECM_EP_INTIN_IDX] = 4; + dev[1].devinfo.epno[CDCECM_EP_BULKIN_IDX] = 11; + dev[1].devinfo.epno[CDCECM_EP_BULKOUT_IDX] = 8; + + return composite_initialize(2, dev); +} + +#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_fpgainitialize.c b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_fpgainitialize.c new file mode 100644 index 00000000000..caeb618ee91 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_fpgainitialize.c @@ -0,0 +1,92 @@ +/************************************************************************************ + * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_sdraminitialize.c + * arch/arm/src/board/lpc17_40_sdraminitialize.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "nuttx/signal.h" +#include "up_arch.h" +#include "lpc17_40_gpio.h" +#include "up_internal.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_emc.h" + +#include "lx_cpu.h" + +void lx_cpu_fpga_initialize(void) +{ + uint32_t regval; + /* Initialze EMC for FPGA */ + + lpc17_40_configgpio(BOARD_XC_PROGRAM_PIN); + lpc17_40_configgpio(BOARD_XC_DONE_PIN); + lpc17_40_configgpio(BOARD_XC_INIT_PIN); + lpc17_40_configgpio(BOARD_XC_SUSPEND_PIN); + lpc17_40_configgpio(BOARD_XC_RDWR_PIN); + + /* Settings: + * 32 bus width + * CS polarity: LOW (ATTENTION: Must match FPGA setup) + * Byte line state: Reads are only 32 bits + * Extended wait: off + * Buffer: disabled + * Write protection: disabled + */ + putreg32(0x00000002, LPC17_40_EMC_STATICCONFIG0); + + /* Delays - not measured at this point + * We're running on 72 MHz, FPGA bus is running on 50 MHz async. + * Read: 32 cycles + * Write: 33 cycles + * Turnaround: 2 cycles (cca. 28 ns) + */ + putreg32(0x1F, LPC17_40_EMC_STATICWAITRD0); + putreg32(0x1F, LPC17_40_EMC_STATICWAITWR0); + putreg32(0x01, LPC17_40_EMC_STATICWAITTURN0); + + /* Shift addresses by 2 (32-bit bus) */ + regval = getreg32(LPC17_40_SYSCON_SCS); + regval &= ~SYSCON_SCS_EMCSC; + putreg32(regval, LPC17_40_SYSCON_SCS); +} diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_nsh.c b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_nsh.c new file mode 100644 index 00000000000..f3309f9ec7f --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_nsh.c @@ -0,0 +1,391 @@ +/**************************************************************************** + * config/lx_cpu/src/lpc17_40_nsh.c + * arch/arm/src/board/lpc17_40_nsh.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "lpc17_40_gpio.h" +#include "lpc17_40_sdcard.h" +#include "lpc17_40_usbhost.h" +#include "lx_cpu.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#define NSH_HAVE_MMCSD 1 +#define NSH_HAVE_USBHOST 1 +#define NSH_HAVE_USBHDEV 1 + +#undef NSH_HAVE_MMCSD_CD +#undef NSH_HAVE_MMCSD_CDINT + +/* MMC/SD support */ + +#if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && !defined(CONFIG_MMCD_SDIO) +# undef NSH_HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef NSH_HAVE_MMCSD +#endif + +/* MMC/SD support requires that an SPI support is enabled and an SPI port is selected */ + +#ifdef NSH_HAVE_MMCSD +# if !defined(CONFIG_NSH_MMCSDSLOTNO) +# warning "Assuming slot MMC/SD slot 0" +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#endif + +#ifdef NSH_HAVE_MMCSD +# if !defined(CONFIG_NSH_MMCSDMINOR) +# warning "Assuming /dev/mmcsd0" +# define CONFIG_NSH_MMCSDMINOR 0 +# endif +#endif + +/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It is also + * used for MOSI1 and USB_UP_LED. The CD pin may be disconnected. There is a jumper + * on board that enables the CD pin. + */ + +#ifdef NSH_HAVE_MMCSD +# ifdef CONFIG_MMCSD_HAVECARDDETECT +# define NSH_HAVE_MMCSD_CD 1 +# ifdef CONFIG_GPIO_IRQ +# define NSH_HAVE_MMCSD_CDINT 1 +# endif +# endif +#endif + +#if defined(NSH_HAVE_MMCSD_CD) && \ + (defined(CONFIG_LPC17_40_SSP1) || defined(CONFIG_LPC17_40_USBDEV)) +# warning "Use of SD Card Detect pin conflicts with SSP1 and/or USB device" +#endif + +/* USB Host */ + +#ifndef CONFIG_USBHOST +# undef NSH_HAVE_USBHOST +#endif + +#ifndef CONFIG_LPC17_40_USBHOST +# undef NSH_HAVE_USBHOST +#endif + +#ifdef NSH_HAVE_USBHOST +# ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +# endif +# ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +# endif +#endif + +/* USB Device */ + +#ifndef CONFIG_USBDEV +# undef NSH_HAVE_USBDEV +#endif + +#ifndef CONFIG_LPC17_40_USBDEV +# undef NSH_HAVE_USBDEV +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef NSH_HAVE_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif +#ifdef NSH_HAVE_MMCSD +static FAR struct sdio_dev_s *g_sdiodev; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_USBHOST +static int nsh_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + syslog(LOG_INFO, "nsh_waiter: Running\n"); + for (;;) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + syslog(LOG_INFO, "nsh_waiter: %s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + (void)CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Name: nsh_cdinterrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_MMCSD_CDINT +static int nsh_cdinterrupt(int irq, FAR void *context) +{ + static bool inserted = 0xff; /* Impossible value */ + bool present; + + present = !lpc17_40_gpioread(GPIO_SD_CD); + if (present != inserted) + { + sdio_mediachange(g_sdiodev, present); + inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: nsh_sdinitialize + * + * Description: + * Initialize SPI-based microSD. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_MMCSD +static int nsh_sdinitialize(void) +{ + int ret; + +#ifdef NSH_HAVE_MMCSD_CD + /* Configure the SD card detect GPIO */ + + lpc17_40_configgpio(GPIO_SD_CD); + + /* Attach an interrupt handler to get notifications when a card is + * inserted or deleted. + */ + +#if NSH_HAVE_MMCSD_CDINT + + (void)irq_attach(LPC17_40_IRQ_P0p13, nsh_cdinterrupt); + up_enable_irq(LPC17_40_IRQ_P0p13); + +#endif +#endif + + /* First, get an instance of the SDIO interface */ + + g_sdiodev = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_sdiodev) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdiodev); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + /* Check if there is a card in the slot and inform the SDCARD driver. If + * we do not support the card detect, then let's assume that there is + * one. + */ + +#ifdef NSH_HAVE_MMCSD_CD + sdio_mediachange(g_sdiodev, !lpc17_40_gpioread(GPIO_SD_CD)); +#else + sdio_mediachange(g_sdiodev, true); +#endif + return OK; +} +#else +# define nsh_sdinitialize() (OK) +#endif + +/**************************************************************************** + * Name: nsh_usbhostinitialize + * + * Description: + * Initialize SPI-based microSD. + * + ****************************************************************************/ + +#ifdef NSH_HAVE_USBHOST +static int nsh_usbhostinitialize(void) +{ + int pid; + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + syslog(LOG_INFO, "Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB host Mass Storage Class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + syslog(LOG_INFO, "Initialize USB host\n"); + g_usbconn = lpc17_40_usbhost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + syslog(LOG_INFO, "Start nsh_waiter\n"); + + pid = task_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + (main_t)nsh_waiter, (FAR char * const *)NULL); + return pid < 0 ? -ENOEXEC : OK; + } + return -ENODEV; +} +#else +# define nsh_usbhostinitialize() (OK) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform architecture specific initialization for NSH. + * + * CONFIG_NSH_ARCHINIT=y : + * Called from the NSH library + * + * CONFIG_BOARD_INITIALIZE=y, CONFIG_NSH_LIBRARY=y, && + * CONFIG_NSH_ARCHINIT=n: + * Called from board_initialize(). + * + ****************************************************************************/ + +int board_app_initialize(void) +{ + int ret; + + /* Initialize SPI-based microSD */ + + ret = nsh_sdinitialize(); + if (ret == OK) + { + /* Initialize USB host */ + + ret = nsh_usbhostinitialize(); + } + + return ret; +} diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_reset.c b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_reset.c new file mode 100644 index 00000000000..668753a28e5 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_reset.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_reset.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Author: Philippe Coval + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + up_systemreset(); + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_sdraminitialize.c b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_sdraminitialize.c new file mode 100644 index 00000000000..598435101d8 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_sdraminitialize.c @@ -0,0 +1,552 @@ +/************************************************************************************ + * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_sdraminitialize.c + * arch/arm/src/board/lpc17_40_sdraminitialize.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "nuttx/signal.h" +#include "up_arch.h" +#include "up_internal.h" +#include "hardware/lpc17_40_syscon.h" +#include "lpc17_40_emc.h" + +#include "lx_cpu.h" + +#if defined(CONFIG_LPC17_40_EMC) && defined(CONFIG_LPC17_40_EXTDRAM) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* The core clock is LPC17_40_EMCCLK which may be either LPC17_40_CCLK* (undivided), or + * LPC17_40_CCLK / 2 as determined by settings in the board.h header file. + * + * For example: + * LPC17_40_CCLCK = 120,000,000 + * EMCCLKSEL -> LPC17_40_CCLK divided by 2 + * LPC17_40_EMCCLK = 60,000,000 + * LPC17_40_EMCCLK_MHZ = 60 (Rounded to an integer) + * EMC_NSPERCLK = 16.667 (Represented with 4 bits of fraction, 267) + * + * EMC_NS2CLK(63) = ((63 << 4) + 266) / 267 = 4 (actual 3.78) + * EMC_NS2CLK(20) = ((20 << 4) + 266) / 267 = 2 (actual 1.20) + */ + +#define LPC17_40_EMCCLK_MHZ ((LPC17_40_EMCCLK + 500000) / 1000000) +#define EMC_NSPERCLK_B4 (((1000 << 4) + (LPC17_40_EMCCLK_MHZ >> 1)) / LPC17_40_EMCCLK_MHZ) +#define EMC_NS2CLK(ns) (((ns << 4) + (EMC_NSPERCLK_B4 - 1)) / EMC_NSPERCLK_B4) +#define MDKCFG_RASVAL 2 +#define MDKCFG_CASVAL 2 + +/* Set up for 32-bit SDRAM at CS0 */ + +#ifdef CONFIG_LPC17_40_EXTDRAMSIZE +# define SDRAM_SIZE CONFIG_LPC17_40_EXTDRAMSIZE +#endif + +#ifdef CONFIG_LPC17_40_SDRAM_16BIT +# ifndef SDRAM_SIZE +# define SDRAM_SIZE 0x02000000 /* 256Mbit */ +# endif +#else /* if defined(CONFIG_LPC17_40_SDRAM_32BIT) */ +# undef CONFIG_LPC17_40_SDRAM_32BIT +# define CONFIG_LPC17_40_SDRAM_32BIT 1 +# ifndef SDRAM_SIZE +# define SDRAM_SIZE 0x04000000 /* 512Mbit */ +# endif +#endif + +#define SDRAM_BASE 0xa0000000 /* CS0 */ + + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static volatile uint32_t lx_cpu_ringosccount[2] = {0,0}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/***************************************************************************** + * Name: + * lx_cpu_running_from_sdram + * + * Descriptions: + * Check whether currently execution from SDRAM. + * + * Returned value: + * 1 running from SDRAM, otherwise 0 + * + ****************************************************************************/ + +static int lx_cpu_running_from_sdram(void) +{ + uint32_t extdram_bank_size = LPC17_40_EXTDRAM_CS3 - LPC17_40_EXTDRAM_CS2; + uint32_t extdram_end = LPC17_40_EXTDRAM_CS3 + extdram_bank_size; + + if (((uint32_t)lx_cpu_running_from_sdram >= LPC17_40_EXTDRAM_CS0) && + ((uint32_t)lx_cpu_running_from_sdram < extdram_end)) + return 1; + else + return 0; +} + +/* SDRAM code based on NXP application notes and emc_sdram.c example */ + +/***************************************************************************** + * Name: + * lx_cpu_sdram_test + * + * Descriptions: + * sdram test + * + * Returned value: + * 1 if test passed, otherwise 0 + * + ****************************************************************************/ +static uint32_t lx_cpu_sdram_test( void ) +{ + volatile uint32_t *wr_ptr; + volatile uint16_t *short_wr_ptr; + uint32_t data; + uint32_t i, j; + + wr_ptr = (uint32_t *)LPC17_40_EXTDRAM_CS0; + short_wr_ptr = (uint16_t *)wr_ptr; + + /* 16 bit write */ + for (i = 0; i < 64; i++) + { + for (j = 0; j < 0x100; j++) + { + *short_wr_ptr++ = (i + j); + *short_wr_ptr++ = (i + j) + 1; + } + } + + /* Verifying */ + wr_ptr = (uint32_t *)LPC17_40_EXTDRAM_CS0; + for (i = 0; i < 64; i++) + { + for (j = 0; j < 0x100; j++) + { + data = *wr_ptr; + if (data != (((((i + j) + 1) & 0xFFFF) << 16) | ((i + j) & 0xFFFF))) + { + return 0x0; + } + wr_ptr++; + } + } + return 0x1; +} + +/**************************************************************************** + * Name: find_cmddly + * + * Descriptions: + * find CMDDLY + * + * Returned value: + * 1 if test passed, otherwise 0 + * + ****************************************************************************/ +static uint32_t lx_cpu_sdram_find_cmddly(void) +{ + uint32_t cmddly, cmddlystart, cmddlyend, regval; + uint32_t ppass = 0x0, pass = 0x0; + + cmddly = 0x0; + cmddlystart = cmddlyend = 0xFF; + + while (cmddly < 32) + { + regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL); + regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK; + regval |= cmddly << SYSCON_EMCDLYCTL_CMDDLY_SHIFT; + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); + + if (lx_cpu_sdram_test() == 0x1) + { + /* Test passed */ + if (cmddlystart == 0xFF) + { + cmddlystart = cmddly; + } + ppass = 0x1; + } + else + { + /* Test failed */ + if (ppass == 1) + { + cmddlyend = cmddly; + pass = 0x1; + ppass = 0x0; + } + } + + /* Try next value */ + cmddly++; + } + + /* If the test passed, the we can use the average of the min and max + * values to get an optimal DQSIN delay + */ + if (pass == 0x1) + { + cmddly = (cmddlystart + cmddlyend) / 2; + } + else if (ppass == 0x1) + { + cmddly = (cmddlystart + 0x1F) / 2; + } + else + { + /* A working value couldn't be found, just pick something + * safe so the system doesn't become unstable + */ + cmddly = 0x10; + } + regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL); + regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK; + regval |= cmddly << SYSCON_EMCDLYCTL_CMDDLY_SHIFT; + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); + + return (pass | ppass); +} + +/**************************************************************************** + * Name: lx_cpu_sdram_find_fbclkdly + * + * Descriptions: + * find FBCLKDLY + * + * Returned value: + * 1 if test passed, otherwise 0 + * + ****************************************************************************/ +static uint32_t lx_cpu_sdram_find_fbclkdly(void) +{ + uint32_t fbclkdly, fbclkdlystart, fbclkdlyend, regval; + uint32_t ppass = 0x0, pass = 0x0; + + fbclkdly = 0x0; + fbclkdlystart = fbclkdlyend = 0xFF; + + while (fbclkdly < 32) + { + regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL); + regval &= ~SYSCON_EMCDLYCTL_FBCLKDLY_MASK; + regval |= fbclkdly << SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT; + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); + + if (lx_cpu_sdram_test() == 0x1) + { + /* Test passed */ + if (fbclkdlystart == 0xFF) + { + fbclkdlystart = fbclkdly; + } + ppass = 0x1; + } + else + { + /* Test failed */ + if (ppass == 1) + { + fbclkdlyend = fbclkdly; + pass = 0x1; + ppass = 0x0; + } + } + + /* Try next value */ + fbclkdly++; + } + + /* If the test passed, the we can use the average of the + * min and max values to get an optimal DQSIN delay + */ + if (pass == 0x1) + { + fbclkdly = (fbclkdlystart + fbclkdlyend) / 2; + } + else if (ppass == 0x1) + { + fbclkdly = (fbclkdlystart + 0x1F) / 2; + } + else + { + /* A working value couldn't be found, just pick something + * safe so the system doesn't become unstable + */ + fbclkdly = 0x10; + } + + regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL); + regval &= ~SYSCON_EMCDLYCTL_FBCLKDLY_MASK; + regval |= fbclkdly << SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT; + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); + + return (pass | ppass); +} + +/**************************************************************************** + * Name: lx_cpu_sdram_calibration + * + * Descriptions: + * Calibration + * + * Returned value: + * current ring osc count + * + ****************************************************************************/ +static uint32_t lx_cpu_sdram_calibration( void ) +{ + uint32_t regval, i; + uint32_t cnt = 0; + + for (i = 0; i < 10; i++) + { + regval = getreg32(LPC17_40_SYSCON_EMCCAL); + regval |= SYSCON_EMCCAL_START_MASK; + putreg32(regval, LPC17_40_SYSCON_EMCCAL); + + regval = getreg32(LPC17_40_SYSCON_EMCCAL); + while ((regval & SYSCON_EMCCAL_DONE_SHIFT) == 0) + { + regval = getreg32(LPC17_40_SYSCON_EMCCAL); + } + cnt += (regval & 0xFF); + } + return (cnt / 10); +} + +/**************************************************************************** + * Name: lx_cpu_sdram_adjust_timing + * + * Descriptions: + * Adjust timing + * + * Returned value: + * None + * + ****************************************************************************/ +static void lx_cpu_sdram_adjust_timing( void ) +{ + uint32_t regval, cmddly, fbclkdly; + + /* Current value */ + lx_cpu_ringosccount[1] = lx_cpu_sdram_calibration(); + + regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL); + + cmddly = regval & SYSCON_EMCDLYCTL_CMDDLY_MASK; + cmddly >>= SYSCON_EMCDLYCTL_CMDDLY_SHIFT; + cmddly = cmddly * lx_cpu_ringosccount[0] / lx_cpu_ringosccount[1]; + cmddly <<= SYSCON_EMCDLYCTL_CMDDLY_SHIFT; + cmddly &= SYSCON_EMCDLYCTL_CMDDLY_MASK; + + fbclkdly = regval & SYSCON_EMCDLYCTL_FBCLKDLY_MASK; + fbclkdly >>= SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT; + fbclkdly = fbclkdly * lx_cpu_ringosccount[0] / lx_cpu_ringosccount[1]; + fbclkdly <<= SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT; + fbclkdly &= SYSCON_EMCDLYCTL_FBCLKDLY_MASK; + + regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK | SYSCON_EMCDLYCTL_FBCLKDLY_MASK; + regval |= cmddly | fbclkdly; + + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: lpc17_40_setup_sdram + * + * Descriptions: + * Setup SDRAM + * + * Returned value: + * Return negative value if SDRAM Fails + * + ****************************************************************************/ + +void lx_cpu_sdram_initialize(void) +{ + uint32_t regval; + uint32_t dynctl; + uint32_t modeval; + volatile uint32_t delay; + + if (lx_cpu_running_from_sdram()) + return; + /* + * Memory MT48LC4M32B2P + * 4 Meg x 32 (1 Meg x 32 x 4 banks) + * Configuration 1 Meg x 32 x 4 banks + * Refresh count 4K + * Row addressing 4K 12-bit A[11:0] + * Bank addressing 4 2-bit BA[1:0] + * Column addressing 256 8-bit A[7:0] + */ + + + /* Reconfigure delays: + * + * CMDDLY: Programmable delay value for EMC outputs in command delayed + * mode. The delay amount is roughly CMDDLY * 250 picoseconds. + * FBCLKDLY: Programmable delay value for the feedback clock that controls + * input data sampling. The delay amount is roughly (FBCLKDLY+1) * 250 + * picoseconds. + * CLKOUT0DLY: Programmable delay value for the CLKOUT0 output. This would + * typically be used in clock delayed mode. The delay amount is roughly + * (CLKOUT0DLY+1) * 250 picoseconds. + * CLKOUT1DLY: Programmable delay value for the CLKOUT1 output. This would + * typically be used in clock delayed mode. The delay amount is roughly + * (CLKOUT1DLY+1) * 250 picoseconds. + */ + + regval = SYSCON_EMCDLYCTL_CMDDLY(32) | + SYSCON_EMCDLYCTL_FBCLKDLY(32) | + SYSCON_EMCDLYCTL_CLKOUT0DLY(1) | + SYSCON_EMCDLYCTL_CLKOUT1DLY(1); + putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); + putreg32(0, LPC17_40_EMC_CONFIG); + + + /* Timing for 72 MHz Bus */ + regval = MDKCFG_CASVAL << EMC_DYNAMICRASCAS_CAS_SHIFT; + regval |= MDKCFG_RASVAL << EMC_DYNAMICRASCAS_RAS_SHIFT; + putreg32(regval, LPC17_40_EMC_DYNAMICRASCAS0); /* 2 RAS, 2 CAS latency */ + putreg32(1, LPC17_40_EMC_DYNAMICREADCONFIG); /* Command delayed strategy, using EMCCLKDELAY */ + + /* EMC_NS2CLK(20) TRP = 20 nS */ + putreg32(1, LPC17_40_EMC_DYNAMICRP); /* ( n + 1 ) -> 2 clock cycles */ + + putreg32(3, LPC17_40_EMC_DYNAMICRAS); /* ( n + 1 ) -> 4 clock cycles */ + + putreg32(5, LPC17_40_EMC_DYNAMICSREX); /* ( n + 1 ) -> 6 clock cycles */ + + putreg32(2, LPC17_40_EMC_DYNAMICAPR); /* ( n + 1 ) -> 3 clock cycles */ + + /* EMC_NS2CLK(20) + 2 TRP + TDPL = 20ns + 2clk */ + putreg32(3, LPC17_40_EMC_DYNAMICDAL); /* ( n ) -> 3 clock cycles */ + + putreg32(1, LPC17_40_EMC_DYNAMICWR); /* ( n + 1 ) -> 2 clock cycles */ + + /* EMC_NS2CLK(63) */ + putreg32(4, LPC17_40_EMC_DYNAMICRC); /* ( n + 1 ) -> 5 clock cycles */ + + /* EMC_NS2CLK(63) */ + putreg32(4, LPC17_40_EMC_DYNAMICRFC); /* ( n + 1 ) -> 5 clock cycles */ + + putreg32(5, LPC17_40_EMC_DYNAMICXSR); /* ( n + 1 ) -> 6 clock cycles */ + + /* EMC_NS2CLK(63) */ + putreg32(1, LPC17_40_EMC_DYNAMICRRD); /* ( n + 1 ) -> 2 clock cycles */ + + putreg32(1, LPC17_40_EMC_STATICEXTENDEDWAIT); /* ( n + 1 ) -> 2 clock cycles */ + + dynctl = EMC_DYNAMICCONTROL_CE | EMC_DYNAMICCONTROL_CS; + up_mdelay(100); + regval = dynctl | EMC_DYNAMICCONTROL_I_NOP; + putreg32(regval, LPC17_40_EMC_DYNAMICCONTROL); /* Issue NOP command */ + up_mdelay(200); /* wait 200ms */ + regval = dynctl | EMC_DYNAMICCONTROL_I_PALL; + putreg32(regval, LPC17_40_EMC_DYNAMICCONTROL); /* Issue PAL command */ + putreg32(2, LPC17_40_EMC_DYNAMICREFRESH); /* ( n * 16 ) -> 32 clock cycles */ + for(delay = 0; delay < 0x80; delay++); /* wait 128 AHB clock cycles */ + + + /* Timing for 72MHz Bus */ + /* ( n * 16 ) -> 1120 clock cycles -> 15.556uS at 72MHz <= 15.625uS ( 64ms / 4096 row ) */ + + regval = 64000000 / (1 << 12); + regval -= 16; + regval >>= 4; + regval = regval * LPC17_40_EMCCLK_MHZ / 1000; + putreg32(regval, LPC17_40_EMC_DYNAMICREFRESH); + + regval = dynctl | EMC_DYNAMICCONTROL_I_MODE; + putreg32(regval, LPC17_40_EMC_DYNAMICCONTROL); /* Issue MODE command */ + + /* Timing for 48/60/72MHZ Bus */ + modeval = LPC17_40_EXTDRAM_CS0; + modeval |= 0x22 << (2 + 2 + 9); /* 4 burst, 2 CAS latency */ + regval = *(volatile uint32_t *)modeval; + putreg32(EMC_DYNAMICCONTROL_I_NORMAL, LPC17_40_EMC_DYNAMICCONTROL); /* Issue NORMAL command */ + + /* [re]enable buffers */ + /* 256MB, 8Mx32, 4 banks, row=12, column=9 */ + regval = EMC_DYNAMICCONFIG_MD_SDRAM; + regval |= 9 << EMC_DYNAMICCONFIG_AM0_SHIFT; + regval |= 1 * EMC_DYNAMICCONFIG_AM1; + regval |= EMC_DYNAMICCONFIG_B; + putreg32(regval, LPC17_40_EMC_DYNAMICCONFIG0); + + /* Nominal value */ + lx_cpu_ringosccount[0] = lx_cpu_sdram_calibration(); + + if (lx_cpu_sdram_find_cmddly() == 0x0) + { + return; /* fatal error */ + } + + if (lx_cpu_sdram_find_fbclkdly() == 0x0) + { + return; /* fatal error */ + } + + lx_cpu_sdram_adjust_timing(); + + return; +} + +#endif /* CONFIG_LPC17_40_EMC && CONFIG_LPC17_40_EXTDRAM */ diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_ssp.c b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_ssp.c new file mode 100644 index 00000000000..36601092123 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_ssp.c @@ -0,0 +1,179 @@ +/**************************************************************************** + * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_ssp.c + * arch/arm/src/board/lpc17_40_ssp.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "up_arch.h" +#include "chip.h" +#include "lpc17_40_gpio.h" +#include "lpc17_40_ssp.h" +#include "lx_cpu.h" + +#if defined(CONFIG_LPC17_40_SSP0) || defined(CONFIG_LPC17_40_SSP1) || \ + defined(CONFIG_LPC17_40_SSP2) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Dump GPIO registers */ + +#ifdef CONFIG_DEBUG_GPIO_INFO +# define ssp_dumpgpio(p,m) lpc17_40_dumpgpio(p,m) +#else +# define ssp_dumpgpio(p,m) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lx_cpu_sspdev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the LPC1766-STK. + * + ****************************************************************************/ + +void weak_function lx_cpu_sspdev_initialize(void) +{ + /* Configure the SSP0 chip select GPIOs. */ + +#ifdef CONFIG_LPC17_40_SSP0 +#endif + + /* Configure SSP1 chip select GPIOs. This includes the touchscreen on the + * the LCD module. + */ + +#ifdef CONFIG_LPC17_40_SSP1 + ssp_dumpgpio(GPIO_TC_CS, "BEFORE SSP1 Initialization"); + lpc17_40_configgpio(GPIO_TC_CS); + ssp_dumpgpio(GPIO_TC_CS, "AFTER SSP1 Initialization"); +#endif + + /* Configure the SSP2 chip select GPIOs. */ + +#ifdef CONFIG_LPC17_40_SSP2 +#endif +} + +/************************************************************************************ + * Name: lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status + * + * Description: + * The external functions, lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status + * must be provided by board-specific logic. They are implementations of the select + * and status methods of the SPI interface defined by struct spi_ops_s (see + * include/nuttx/spi/spi.h). All other methods (including lpc17_40_sspbus_initialize()) + * are provided by common LPC17xx logic. To use this common SPI logic on your + * board: + * + * 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP chip select + * pins. + * 2. Provide lpc17_40_ssp0/1/2select() and lpc17_40_ssp0/1/2status() functions + * in your board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 3. Add a calls to lpc17_40_sspbus_initialize() in your low level application + * initialization logic + * 4. The handle returned by lpc17_40_sspbus_initialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_40_SSP0 +void lpc17_40_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t lpc17_40_ssp0status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); + return 0; +} +#endif + +#ifdef CONFIG_LPC17_40_SSP1 +void lpc17_40_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + if (devid == SPIDEV_TOUCHSCREEN(0)) + { + /* Assert/de-assert the CS pin to the touchscreen */ + + ssp_dumpgpio(GPIO_TC_CS, "lpc17_40_ssp1select() Entry"); + lpc17_40_gpiowrite(GPIO_TC_CS, !selected); + ssp_dumpgpio(GPIO_TC_CS, "lpc17_40_ssp1select() Exit"); + } +} + +uint8_t lpc17_40_ssp1status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); + return 0; +} +#endif + +#ifdef CONFIG_LPC17_40_SSP2 +void lpc17_40_ssp2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t lpc17_40_ssp2status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); + return 0; +} +#endif + +#endif /* CONFIG_LPC17_40_SSP0 || CONFIG_LPC17_40_SSP1 || CONFIG_LPC17_40_SSP2 */ diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_userleds.c b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_userleds.c new file mode 100644 index 00000000000..d0daf2f2ecc --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_userleds.c @@ -0,0 +1,120 @@ +/**************************************************************************** + * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_userleds.c + * arch/arm/src/board/lpc17_40_userleds.c + * + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc17_40_gpio.h" +#include "lx_cpu.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Dump GPIO registers */ + +#ifdef CONFIG_DEBUG_LEDS_INFO +# define led_dumpgpio(m) lpc17_40_dumpgpio(???, m) +#else +# define led_dumpgpio(m) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + lpc17_40_configgpio(GPIO_LED1); + lpc17_40_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + lpc17_40_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + lpc17_40_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + lpc17_40_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/src/lx_cpu.h b/boards/arm/lpc17xx_40xx/lx_cpu/src/lx_cpu.h new file mode 100644 index 00000000000..ae363e7a89c --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/src/lx_cpu.h @@ -0,0 +1,178 @@ +/************************************************************************************ + * boards/arm/lpc17xx_40xx/lx_cpu/src/lx_cpu.h + * arch/arm/src/board/lx_cpu.n + * + * Copyright (C) 2013, 2017-2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef _CONFIGS_LX_CPU_SRC_LX_CPU_H +#define _CONFIGS_LX_CPU_SRC_LX_CPU_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* LX_CPU GPIO Pin Definitions ****************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + * + * LED1 -- Connected to P1[29] RED + * LED2 -- Connected to P0[16] GREEN + * + * These LEDs are connecte to ground so a high output value will illuminate them. + */ + +#define GPIO_LED1 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_LED2 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN16) + +/* SD Card **************************************************************************/ +/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It is also + * used for MOSI1 and USB_UP_LED. The CD pin may be disconnected. There is a jumper + * on board that enables the CD pin. + * + * The CD pin is interrupting: + */ + +#define GPIO_SD_CD (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN13) + +/* LCD ******************************************************************************/ +/* Backlight enable, P2[1]. Initial state is OFF (zero) */ + +#define GPIO_LCD_BL (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT2 | GPIO_PIN1) + +/* XPT2046 Touchscreen **************************************************************/ +/* -------------- -------------------- ------------ -------------------------------- + * XTPT2046 Module Module LX_CPU LED + * Signal Connector Connector + * -------------- -------------------- ------------ --------------------------------- + * Pin 11 PENIRQ\ PENIRQ (pulled high) PORT3 Pin 1 P2.15 PENIRQ + * Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP LED) + * Pin 13 BUSY BUSY (pulled high) PORT3 Pin 9 P2.14 BUSY + * Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device up LED and SD CD pin) + * Pin 15 CS\ SSEL (pulled high) PORT3 Pin 6 P1.8 GPIO (Also RMII_CRS_DV) + * Pin 16 DCLK SCK PORT3 Pin 5 P1.19 SCK1 + * -------------- -------------------- ------------ --------------------------------- + * + * Pins should not need to be configured as pull-ups because, according to the LCD + * schematic, the are pulled-up on board the LCD module. + */ + +#define GPIO_TC_PENIRQ (GPIO_INTBOTH | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_TC_BUSY (GPIO_INPUT | GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_TC_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN8) + +#define LPC17_40_IRQ_PENIRQ LPC17_40_IRQ_P2p15 + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lx_cpu_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library via boardctl() + * + ************************************************************************************/ + +int lx_cpu_bringup(void); + +/************************************************************************************ + * Name: lx_cpu_sspdev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the WaveShare LX_CPU board. + * + ************************************************************************************/ + +void weak_function lx_cpu_sspdev_initialize(void); + +/************************************************************************************ + * Name: lx_cpu_sdram_initialize + * + * Description: + * Initialize SDRAM + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_40_EMC +#ifdef CONFIG_LPC17_40_EXTDRAM +void lx_cpu_sdram_initialize(void); +#endif + +/************************************************************************************ + * Name: lx_cpu_fpga_initialize + * + * Description: + * Initialize FPGA chipselect + * + ************************************************************************************/ + +void lx_cpu_fpga_initialize(void); + +#endif /* CONFIG_LPC17_40_EMC */ + +/************************************************************************************ + * Name: lx_cpu_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ************************************************************************************/ + +#ifdef CONFIG_CAN +int lx_cpu_can_setup(void); +#endif + + +#endif /* __ASSEMBLY__ */ +#endif /* _CONFIGS_LX_CPU_SRC_LX_CPU_H */ diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/tools/gdb-openocd.init b/boards/arm/lpc17xx_40xx/lx_cpu/tools/gdb-openocd.init new file mode 100644 index 00000000000..e8ca7f9e05b --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/tools/gdb-openocd.init @@ -0,0 +1,3 @@ +#set endian big +target remote localhost:3333 +#load diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/tools/jt_usb5-jtag.cfg b/boards/arm/lpc17xx_40xx/lx_cpu/tools/jt_usb5-jtag.cfg new file mode 100644 index 00000000000..33906699649 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/tools/jt_usb5-jtag.cfg @@ -0,0 +1,2 @@ +interface ftdi +#ftdi_device_desc "Dual RS232" diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/tools/lx_cpu-jt_usb5-ddd b/boards/arm/lpc17xx_40xx/lx_cpu/tools/lx_cpu-jt_usb5-ddd new file mode 100644 index 00000000000..49e5c4b5d73 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/tools/lx_cpu-jt_usb5-ddd @@ -0,0 +1,22 @@ +#!/bin/sh + +SCRIP_DIR="$(dirname "$(readlink -f "$0")")" + +nc -w 3 -z localhost 4444 +if [ $? -ne 0 ] +then + echo "Starting OpenOCD" + openocd -f "$SCRIP_DIR/lx_cpu-lpc4088.cfg" & + OPENOCD_PID=$! + nc -w 10 -z localhost 4444 + if [ $? -ne 0 ] + then + echo "OpenOCD start failed" + fi +fi + +sleep 10 + +ddd --debugger arm-elf-gdb -x "$SCRIP_DIR/gdb-openocd.init" "$1" + +kill $OPENOCD_PID diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/tools/lx_cpu-lpc4088.cfg b/boards/arm/lpc17xx_40xx/lx_cpu/tools/lx_cpu-lpc4088.cfg new file mode 100644 index 00000000000..f44598e1b28 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/tools/lx_cpu-lpc4088.cfg @@ -0,0 +1,24 @@ +# This is configuration for PiKRON's LX_CPU1 based on NXP LPC4088 chip. +# http://pikron.com/pages/products/cpu_boards/lx_cpu.html + +#daemon configuration + +telnet_port 4444 +gdb_port 3333 + +adapter_khz 1000 + +source [find jt_usb5-jtag.cfg] + +source [find target/lpc40xx.cfg] + +init + +reset init +#wait_halt +resume +sleep 1000 +halt +wait_halt + +adapter_khz 1000 diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/tools/oocd.sh b/boards/arm/lpc17xx_40xx/lx_cpu/tools/oocd.sh new file mode 100644 index 00000000000..d71e44b6225 --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/tools/oocd.sh @@ -0,0 +1,57 @@ +#!/bin/sh +# +# See boards/arm/lpc17xx_40xx/lx_cpu/README.txt for information about +# this file. + +TOPDIR=$1 +USAGE="$0 [-d]" +if [ -z "${TOPDIR}" ]; then + echo "Missing argument" + echo $USAGE + exit 1 +fi + +# Assume that OpenOCD was installed and at /usr/local/bin. Uncomment +# the following to run directly from the build directory + +# OPENOCD_PATH="/home/OpenOCD/openocd/src" +# OPENOCD_PATH="/usr/bin" +OPENOCD_PATH="/usr/local/bin" + +# TARGET_PATH="/home/OpenOCD/openocd/tcl" +# TARGET_PATH="/usr/share/openocd/scripts" +TARGET_PATH="/usr/local/share/openocd/scripts" + +# Assume a Unix development environment. Uncomment to use a Windows +# like environment + +OPENOCD_EXE=openocd.exe +# OPENOCD_EXE=openocd + +OPENOCD_CFG="${TOPDIR}/boards/arm/lpc17xx_40xx/lx_cpu/tools/lx_cpu-lpc4088.cfg" +OPENOCD_ARGS="-f ${OPENOCD_CFG} -s ${TARGET_PATH}" + +if [ "X$2" = "X-d" ]; then + OPENOCD_ARGS=$OPENOCD_ARGS" -d3" + set -x +fi + +if [ ! -d ${OPENOCD_PATH} ]; then + echo "OpenOCD path does not exist: ${OPENOCD_PATH}" + exit 1 +fi +if [ ! -x ${OPENOCD_PATH}/${OPENOCD_EXE} ]; then + echo "OpenOCD does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" + exit 1 +fi +if [ ! -f ${OPENOCD_CFG} ]; then + echo "OpenOCD config file does not exist: ${OPENOCD_CFG}" + exit 1 +fi + +echo "Starting OpenOCD" +cd ${OPENOCD_PATH} || { echo "Failed to CD to ${OPENOCD_PATH}"; exit 1; } +${OPENOCD_EXE} ${OPENOCD_ARGS} & +echo "OpenOCD daemon started" +ps -ef | grep openocd +echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/tools/openocd.cfg b/boards/arm/lpc17xx_40xx/lx_cpu/tools/openocd.cfg new file mode 100644 index 00000000000..ccc4143203e --- /dev/null +++ b/boards/arm/lpc17xx_40xx/lx_cpu/tools/openocd.cfg @@ -0,0 +1,16 @@ +#daemon configuration + +telnet_port 4444 +gdb_port 3333 + +adapter_khz 5000 + +source [find lx_cpu-lpc4088.cfg] + +init + +reset halt + +wait_halt + +adapter_khz 5000