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Docs/esp32c3: esp32c3 new approach documentation added
This commit is contained in:
Eren Terzioglu
committed by
Alin Jerpelea
Alin Jerpelea
parent
25670bac9f
commit
34c6bb3bd7
@@ -1,5 +1,6 @@
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.. note::
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.. note::
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A new approach is being adopted for this chip and this implementation will be deprecated when the same support level is achieved.
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A new approach is being adopted for this chip and this implementation will be deprecated when the same support level is achieved.
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For the new approach please check :ref:`here<esp32c3>`.
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===========================
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===========================
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Espressif ESP32-C3 (Legacy)
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Espressif ESP32-C3 (Legacy)
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================
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ESP32-C3 DevKit
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================
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The ESP32-C3 DevKit is an entry-level development board equipped with either
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an ESP32-C3-WROOM-02 or an ESP32-C3-MINI-1.
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ESP32-C3-WROOM-02 and ESP32-C3-MINI-1 are SoMs based on the RISC-V ESP32-C3 CPU.
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Most of the I/O pins are broken out to the pin headers on both sides for easy
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interfacing. Developers can either connect peripherals with jumper wires or
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mount ESP32-C3 DevKit on a breadboard.
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.. list-table::
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:align: center
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* - .. figure:: ESP32-C3-DevKitC-02-v1.1.png
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:align: center
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ESP32-C3-DevKitC-02
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- .. figure:: ESP32-C3-DevKitM-1-v1.0.png
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:align: center
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ESP32-C3-DevKitM-1
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Buttons and LEDs
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================
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Board Buttons
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-------------
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There are two buttons labeled Boot and RST. The RST button is not available
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to software. It pulls the chip enable line that doubles as a reset line.
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The BOOT button is connected to IO9. On reset it is used as a strapping
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pin to determine whether the chip boots normally or into the serial
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bootloader. After reset, however, the BOOT button can be used for software
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input.
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Board LEDs
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----------
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There is one on-board LED that indicates the presence of power.
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Another WS2812 LED is connected to GPIO8 and is available for software.
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Configurations
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==============
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All of the configurations presented below can be tested by running the following commands::
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$ ./tools/configure.sh esp32c3-generic:<config_name>
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$ make flash ESPTOOL_PORT=/dev/ttyUSB0 -j
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Where <config_name> is the name of board configuration you want to use, i.e.: nsh, buttons, wifi...
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Then use a serial console terminal like ``picocom`` configured to 115200 8N1.
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coremark
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--------
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This configuration sets the CoreMark benchmark up for running on the maximum
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number of cores for this system. It also enables some optimization flags and
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disables the NuttShell to get the best possible score.
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.. note:: As the NSH is disabled, the application will start as soon as the
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system is turned on.
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gpio
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----
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This is a test for the GPIO driver. It uses GPIO1 and GPIO2 as outputs and
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GPIO9 as an interrupt pin.
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At the nsh, we can turn the outputs on and off with the following::
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nsh> gpio -o 1 /dev/gpio0
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nsh> gpio -o 1 /dev/gpio1
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nsh> gpio -o 0 /dev/gpio0
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nsh> gpio -o 0 /dev/gpio1
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We can use the interrupt pin to send a signal when the interrupt fires::
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nsh> gpio -w 14 /dev/gpio2
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The pin is configured as a rising edge interrupt, so after issuing the
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above command, connect it to 3.3V.
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nsh
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---
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Basic configuration to run the NuttShell (nsh).
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ostest
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------
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This is the NuttX test at ``apps/testing/ostest`` that is run against all new
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architecture ports to assure a correct implementation of the OS.
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pwm
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---
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This configuration demonstrates the use of PWM through a LED connected to GPIO2.
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To test it, just execute the ``pwm`` application::
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nsh> pwm
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pwm_main: starting output with frequency: 10000 duty: 00008000
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pwm_main: stopping output
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rtc
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---
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This configuration demonstrates the use of the RTC driver through alarms.
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You can set an alarm, check its progress and receive a notification after it expires::
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nsh> alarm 10
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alarm_daemon started
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alarm_daemon: Running
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Opening /dev/rtc0
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Alarm 0 set in 10 seconds
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nsh> alarm -r
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Opening /dev/rtc0
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Alarm 0 is active with 10 seconds to expiration
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nsh> alarm_daemon: alarm 0 received
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sotest
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------
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This config is to run apps/examples/sotest.
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timer
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-----
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This config test the general use purpose timers. It includes the 4 timers,
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adds driver support, registers the timers as devices and includes the timer
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example.
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To test it, just run the following::
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nsh> timer -d /dev/timerx
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Where x in the timer instance.
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usbconsole
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----------
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This configuration tests the built-in USB-to-serial converter found in ESP32-C3 (revision 3).
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``esptool`` can be used to check the version of the chip and if this feature is
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supported. Running ``esptool.py -p <port> chip_id`` should have ``Chip is
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ESP32-C3 (revision 3)`` in its output.
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When connecting the board a new device should appear, a ``/dev/ttyACMX`` on Linux
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or a ``/dev/cu.usbmodemXXX`` om macOS.
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This can be used to flash and monitor the device with the usual commands::
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make download ESPTOOL_PORT=/dev/ttyACM0
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minicom -D /dev/ttyACM0
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watchdog
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--------
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This configuration tests the watchdog timers. It includes the 2 MWDTS,
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adds driver support, registers the WDTs as devices and includes the watchdog
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example application.
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To test it, just run the following command::
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nsh> wdog -i /dev/watchdogX
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Where X is the watchdog instance.
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@@ -0,0 +1,285 @@
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.. _esp32c3:
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==================
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Espressif ESP32-C3
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==================
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The ESP32-C3 is an ultra-low-power and highly integrated SoC with a RISC-V
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core and supports 2.4 GHz Wi-Fi and Bluetooth Low Energy.
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* Address Space
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- 800 KB of internal memory address space accessed from the instruction bus
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- 560 KB of internal memory address space accessed from the data bus
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- 1016 KB of peripheral address space
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- 8 MB of external memory virtual address space accessed from the instruction bus
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- 8 MB of external memory virtual address space accessed from the data bus
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- 480 KB of internal DMA address space
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* Internal Memory
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- 384 KB ROM
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- 400 KB SRAM (16 KB can be configured as Cache)
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- 8 KB of SRAM in RTC
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* External Memory
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- Up to 16 MB of external flash
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* Peripherals
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- 35 peripherals
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* GDMA
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- 7 modules are capable of DMA operations.
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ESP32-C3 Toolchain
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==================
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A generic RISC-V toolchain can be used to build ESP32-C3 projects. It's recommended to use the same
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toolchain used by NuttX CI. Please refer to the Docker
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`container <https://github.com/apache/nuttx/tree/master/tools/ci/docker/linux/Dockerfile>`_ and
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check for the current compiler version being used. For instance:
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.. code-block::
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###############################################################################
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# Build image for tool required by RISCV builds
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###############################################################################
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FROM nuttx-toolchain-base AS nuttx-toolchain-riscv
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# Download the latest RISCV GCC toolchain prebuilt by xPack
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RUN mkdir riscv-none-elf-gcc && \
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curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v12.3.0-2/xpack-riscv-none-elf-gcc-12.3.0-2-linux-x64.tar.gz" \
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| tar -C riscv-none-elf-gcc --strip-components 1 -xz
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It uses the xPack's prebuilt toolchain based on GCC 12.3.0.
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Installing
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----------
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First, create a directory to hold the toolchain:
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.. code-block:: console
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$ mkdir -p /path/to/your/toolchain/riscv-none-elf-gcc
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Download and extract toolchain:
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.. code-block:: console
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$ curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v12.3.0-2/xpack-riscv-none-elf-gcc-12.3.0-2-linux-x64.tar.gz" \
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| tar -C /path/to/your/toolchain/riscv-none-elf-gcc --strip-components 1 -xz
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Add the toolchain to your `PATH`:
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.. code-block:: console
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$ echo "export PATH=/path/to/your/toolchain/riscv-none-elf-gcc/bin:$PATH" >> ~/.bashrc
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You can edit your shell's rc files if you don't use bash.
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Second stage bootloader and partition table
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===========================================
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The NuttX port for now relies on IDF's second stage bootloader to carry on some hardware
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|
initializations. The binaries for the bootloader and the partition table can be found in
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this repository: https://github.com/espressif/esp-nuttx-bootloader
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That repository contains a dummy IDF project that's used to build the bootloader and
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partition table, these are then presented as Github assets and can be downloaded
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from: https://github.com/espressif/esp-nuttx-bootloader/releases
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Download ``bootloader-esp32c3.bin`` and ``partition-table-esp32c3.bin`` and place them
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in a folder, the path to this folder will be used later to program them. This
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can be: ``../esp-bins``
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Building and flashing
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|
=====================
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|
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First make sure that ``esptool.py`` is installed. This tool is used to convert
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the ELF to a compatible ESP32 image and to flash the image into the board.
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It can be installed with: ``pip install esptool``.
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Configure the NuttX project: ``./tools/configure.sh esp32c3-devkit:nsh``
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Run ``make`` to build the project. Note that the conversion mentioned above is
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|
included in the build process.
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The ``esptool.py`` command to flash all the binaries is::
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esptool.py --chip esp32c3 --port /dev/ttyUSBXX --baud 921600 write_flash 0x0 bootloader.bin 0x8000 partition-table.bin 0x10000 nuttx.bin
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|
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|
However, this is also included in the build process and we can build and flash with::
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make flash ESPTOOL_PORT=<port> ESPTOOL_BINDIR=../esp-bins
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Where ``<port>`` is typically ``/dev/ttyUSB0`` or similar and ``../esp-bins`` is
|
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|
the path to the folder containing the bootloader and the partition table
|
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for the ESP32-C3 as explained above.
|
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|
Note that this step is required only one time. Once the bootloader and partition
|
||||||
|
table are flashed, we don't need to flash them again. So subsequent builds
|
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|
would just require: ``make flash ESPTOOL_PORT=/dev/ttyUSBXX``
|
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|
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|
Debugging with OpenOCD
|
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|
======================
|
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|
|
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|
Download and build OpenOCD from Espressif, that can be found in
|
||||||
|
https://github.com/espressif/openocd-esp32
|
||||||
|
|
||||||
|
If you have an ESP32-C3 ECO3, no external JTAG is required to debug, the ESP32-C3
|
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|
integrates a USB-to-JTAG adapter.
|
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|
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|
OpenOCD can then be used::
|
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|
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|
openocd -c 'set ESP_RTOS none' -f board/esp32c3-builtin.cfg
|
||||||
|
|
||||||
|
For versions prior to ESP32-C3 ECO3, an external JTAG adapter is needed.
|
||||||
|
It can be connected as follows::
|
||||||
|
|
||||||
|
TMS -> GPIO4
|
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|
TDI -> GPIO5
|
||||||
|
TCK -> GPIO6
|
||||||
|
TDO -> GPIO7
|
||||||
|
|
||||||
|
Furthermore, an efuse needs to be burnt to be able to debug::
|
||||||
|
|
||||||
|
espefuse.py -p <port> burn_efuse DIS_USB_JTAG
|
||||||
|
|
||||||
|
OpenOCD can then be used::
|
||||||
|
|
||||||
|
openocd -c 'set ESP_RTOS none' -f board/esp32c3-ftdi.cfg
|
||||||
|
|
||||||
|
Peripheral Support
|
||||||
|
==================
|
||||||
|
|
||||||
|
The following list indicates the state of peripherals' support in NuttX:
|
||||||
|
|
||||||
|
=========== ======= =====
|
||||||
|
Peripheral Support NOTES
|
||||||
|
=========== ======= =====
|
||||||
|
ADC No
|
||||||
|
AES No
|
||||||
|
Bluetooth No
|
||||||
|
CDC Console Yes Rev.3
|
||||||
|
DMA No
|
||||||
|
eFuse No
|
||||||
|
GPIO Yes
|
||||||
|
I2C No
|
||||||
|
LED_PWM Yes
|
||||||
|
RNG No
|
||||||
|
RSA No
|
||||||
|
RTC Yes
|
||||||
|
SHA No
|
||||||
|
SPI No
|
||||||
|
SPIFLASH No
|
||||||
|
Timers Yes
|
||||||
|
Touch No
|
||||||
|
UART Yes
|
||||||
|
Watchdog Yes
|
||||||
|
Wifi No
|
||||||
|
=========== ======= =====
|
||||||
|
|
||||||
|
Secure Boot and Flash Encryption
|
||||||
|
================================
|
||||||
|
|
||||||
|
Secure Boot
|
||||||
|
-----------
|
||||||
|
|
||||||
|
Secure Boot protects a device from running any unauthorized (i.e., unsigned) code by checking that
|
||||||
|
each piece of software that is being booted is signed. On an ESP32-C3, these pieces of software include
|
||||||
|
the second stage bootloader and each application binary. Note that the first stage bootloader does not
|
||||||
|
require signing as it is ROM code thus cannot be changed. This is achieved using specific hardware in
|
||||||
|
conjunction with MCUboot (read more about MCUboot `here <https://docs.mcuboot.com/>`__).
|
||||||
|
|
||||||
|
The Secure Boot process on the ESP32-C3 involves the following steps performed:
|
||||||
|
|
||||||
|
1. The first stage bootloader verifies the second stage bootloader's RSA-PSS signature. If the verification is successful,
|
||||||
|
the first stage bootloader loads and executes the second stage bootloader.
|
||||||
|
|
||||||
|
2. When the second stage bootloader loads a particular application image, the application's signature (RSA, ECDSA or ED25519) is verified
|
||||||
|
by MCUboot.
|
||||||
|
If the verification is successful, the application image is executed.
|
||||||
|
|
||||||
|
.. warning:: Once enabled, Secure Boot will not boot a modified bootloader. The bootloader will only boot an
|
||||||
|
application firmware image if it has a verified digital signature. There are implications for reflashing
|
||||||
|
updated images once Secure Boot is enabled. You can find more information about the ESP32-C3's Secure boot
|
||||||
|
`here <https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/security/secure-boot-v2.html>`__.
|
||||||
|
|
||||||
|
.. note:: As the bootloader image is built on top of the Hardware Abstraction Layer component
|
||||||
|
of `ESP-IDF <https://github.com/espressif/esp-idf>`_, the
|
||||||
|
`API port by Espressif <https://docs.mcuboot.com/readme-espressif.html>`_ will be used
|
||||||
|
by MCUboot rather than the original NuttX port.
|
||||||
|
|
||||||
|
Flash Encryption
|
||||||
|
----------------
|
||||||
|
|
||||||
|
Flash encryption is intended for encrypting the contents of the ESP32-C3's off-chip flash memory. Once this feature is enabled,
|
||||||
|
firmware is flashed as plaintext, and then the data is encrypted in place on the first boot. As a result, physical readout
|
||||||
|
of flash will not be sufficient to recover most flash contents.
|
||||||
|
|
||||||
|
.. warning:: After enabling Flash Encryption, an encryption key is generated internally by the device and
|
||||||
|
cannot be accessed by the user for re-encrypting data and re-flashing the system, hence it will be permanently encrypted.
|
||||||
|
Re-flashing an encrypted system is complicated and not always possible. You can find more information about the ESP32-C3's Flash Encryption
|
||||||
|
`here <https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/security/flash-encryption.html>`__.
|
||||||
|
|
||||||
|
Prerequisites
|
||||||
|
-------------
|
||||||
|
|
||||||
|
First of all, we need to install ``imgtool`` (a MCUboot utility application to manipulate binary
|
||||||
|
images) and ``esptool`` (the ESP32-C3 toolkit)::
|
||||||
|
|
||||||
|
$ pip install imgtool esptool
|
||||||
|
|
||||||
|
We also need to make sure that the python modules are added to ``PATH``::
|
||||||
|
|
||||||
|
$ echo "PATH=$PATH:/home/$USER/.local/bin" >> ~/.bashrc
|
||||||
|
|
||||||
|
Now, we will create a folder to store the generated keys (such as ``~/signing_keys``)::
|
||||||
|
|
||||||
|
$ mkdir ~/signing_keys && cd ~/signing_keys
|
||||||
|
|
||||||
|
With all set up, we can now generate keys to sign the bootloader and application binary images,
|
||||||
|
respectively, of the compiled project::
|
||||||
|
|
||||||
|
$ espsecure.py generate_signing_key --version 2 bootloader_signing_key.pem
|
||||||
|
$ imgtool keygen --key app_signing_key.pem --type rsa-3072
|
||||||
|
|
||||||
|
.. important:: The contents of the key files must be stored securely and kept secret.
|
||||||
|
|
||||||
|
Enabling Secure Boot and Flash Encryption
|
||||||
|
-----------------------------------------
|
||||||
|
|
||||||
|
To enable Secure Boot for the current project, go to the project's NuttX directory, execute ``make menuconfig`` and the following steps:
|
||||||
|
|
||||||
|
1. Enable experimental features in :menuselection:`Build Setup --> Show experimental options`;
|
||||||
|
|
||||||
|
2. Enable MCUboot in :menuselection:`Application Configuration --> Bootloader Utilities --> MCUboot`;
|
||||||
|
|
||||||
|
3. Change image type to ``MCUboot-bootable format`` in :menuselection:`System Type --> Application Image Configuration --> Application Image Format`;
|
||||||
|
|
||||||
|
4. Enable building MCUboot from the source code by selecting ``Build binaries from source``;
|
||||||
|
in :menuselection:`System Type --> Application Image Configuration --> Source for bootloader binaries`;
|
||||||
|
|
||||||
|
5. Enable Secure Boot in :menuselection:`System Type --> Application Image Configuration --> Enable hardware Secure Boot in bootloader`;
|
||||||
|
|
||||||
|
6. If you want to protect the SPI Bus against data sniffing, you can enable Flash Encryption in
|
||||||
|
:menuselection:`System Type --> Application Image Configuration --> Enable Flash Encryption on boot`.
|
||||||
|
|
||||||
|
Now you can design an update and confirm agent to your application. Check the `MCUboot design guide <https://docs.mcuboot.com/design.html>`_ and the
|
||||||
|
`MCUboot Espressif port documentation <https://docs.mcuboot.com/readme-espressif.html>`_ for
|
||||||
|
more information on how to apply MCUboot. Also check some `notes about the NuttX MCUboot port <https://github.com/mcu-tools/mcuboot/blob/main/docs/readme-nuttx.md>`_,
|
||||||
|
the `MCUboot porting guide <https://github.com/mcu-tools/mcuboot/blob/main/docs/PORTING.md>`_ and some
|
||||||
|
`examples of MCUboot applied in Nuttx applications <https://github.com/apache/nuttx-apps/tree/master/examples/mcuboot>`_.
|
||||||
|
|
||||||
|
After you developed an application which implements all desired functions, you need to flash it into the primary image slot
|
||||||
|
of the device (it will automatically be in the confirmed state, you can learn more about image
|
||||||
|
confirmation `here <https://docs.mcuboot.com/design.html#image-swapping>`_).
|
||||||
|
To flash to the primary image slot, select ``Application image primary slot`` in
|
||||||
|
:menuselection:`System Type --> Application Image Configuration --> Target slot for image flashing`
|
||||||
|
and compile it using ``make -j ESPSEC_KEYDIR=~/signing_keys``.
|
||||||
|
|
||||||
|
When creating update images, make sure to change :menuselection:`System Type --> Application Image Configuration --> Target slot for image flashing`
|
||||||
|
to ``Application image secondary slot``.
|
||||||
|
|
||||||
|
.. important:: When deploying your application, make sure to disable UART Download Mode by selecting ``Permanently disabled`` in
|
||||||
|
:menuselection:`System Type --> Application Image Configuration --> UART ROM download mode`
|
||||||
|
and change usage mode to ``Release`` in `System Type --> Application Image Configuration --> Enable usage mode`.
|
||||||
|
**After disabling UART Download Mode you will not be able to flash other images through UART.**
|
||||||
|
|
||||||
|
|
||||||
|
Supported Boards
|
||||||
|
================
|
||||||
|
|
||||||
|
.. toctree::
|
||||||
|
:glob:
|
||||||
|
:maxdepth: 1
|
||||||
|
|
||||||
|
boards/*/*
|
||||||
Reference in New Issue
Block a user