Add support for .data and .bss in SDRAM

arch/arm/src/armv7-a/arm.h

@@ -111,6 +111,22 @@ extern "C" {
 #define EXTERN extern
 #endif
 
+/****************************************************************************
+ * Name: arm_data_initialize
+ *
+ * Description:
+ *   Clear all of .bss to zero; set .data to the correct initial values
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void arm_data_initialize(void);
+
 #undef EXTERN
 #ifdef __cplusplus
 }

arch/arm/src/armv7-a/arm_head.S

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/armv7-a/arm_head.S
  *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -70,8 +70,6 @@
  */
 
 #ifdef CONFIG_BOOT_RUNFROMFLASH
-#  define DO_SDRAM_INIT 1
-
   /* Check for the identity mapping:  For this configuration, this would be
    * the case where the virtual beginning of FLASH is the same as the physical
    * beginning of FLASH.
@@ -98,7 +96,6 @@
 
 #elif defined(CONFIG_BOOT_COPYTORAM)
 #  error "configuration not implemented
-#  define DO_SDRAM_INIT 1
 
   /* Check for the identity mapping:  For this configuration, this would be
    * the case where the virtual beginning of FLASH is the same as the physical
@@ -193,18 +190,6 @@ __start:
 	mov		r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
 	msr		cpsr_c, r0
 
-	/* Initialize DRAM using a macro provided by board-specific logic.
-	 *
-	 * This must be done in two cases:
-	 * 1. CONFIG_BOOT_RUNFROMFLASH.  The system is running from FLASH
-	 * 2. CONFIG_BOOT_COPYTORAM.  The system booted from FLASH but
-	 *    will copy itself to SDRAM.
-	 */
-
-#ifdef DO_SDRAM_INIT
-	config_sdram
-#endif
-
 	/* Clear the 16K level 1 page table */
 
 	ldr		r5, .LCppgtable			/* r5=phys. page table */
@@ -626,19 +611,70 @@ __start:
 	str		r3, [r5, r3, lsr #18]	/* identity mapping */
 #endif /* !CONFIG_ARCH_ROMPGTABLE && !CONFIG_IDENTITY_TEXTMAP */
 
-	/* Zero BSS and set up the stack pointer */
+	/* Set up the stack pointer and clear the frame pointer */
+
+	ldr		sp, .Lstackpointer
+	mov     fp, #0
+
+	/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
+	 * ready to use.  Other memory, such as SDRAM, must be initialized before
+	 * it can be used.  up_boot() will perform that memory initialization and
+	 * .bss and .data can be initialized after up_boot() returns.
+	 */
+
+#ifndef CONFIG_BOOT_SDRAM_DATA
+	bl		arm_data_initialize
+#endif
+
+	/* Perform early C-level, platform-specific initialization.  Logic
+	 * within up_boot() must configure SDRAM and call arm_ram_initailize.
+	 */
+
+	bl		up_boot
+
+#ifdef CONFIG_DEBUG_STACK
+	/* Write a known value to the IDLE thread stack to support stack
+	 * monitoring logic
+	 */
+
+	adr		r3, .Lstkinit
+	ldmia	r3, {r0, r1, r2}	/* R0 = start of IDLE stack; R1 = Size of tack; R2 = coloration */
+
+1:								/* Top of the loop */
+	sub		r1, r1, #1			/* R1 = Number of words remaining */
+	cmp		r1, #0				/* Check (nwords == 0) */
+	str		r2, [r0], #4		/* Save stack color word, increment stack address */
+	bne		1b					/* Bottom of the loop */
+#endif
+
+	/* Finally branch to the OS entry point */
+
+	mov		lr, #0				/* LR = return address (none) */
+	b		os_start			/* Branch to os_start */
+	.size	.Lvstart, .-.Lvstart
+
+/***************************************************************************
+ * Name: arm_data_initialize
+ ***************************************************************************/
+
+	.global	arm_data_initialize
+	.type	arm_data_initialize, #function
+
+arm_data_initialize:
+
+	/* zero BSS and set up the stack pointer */
 
 	adr		r0, .Linitparms
-	ldmia	r0, {r0, r1, sp}
+	ldmia	r0, {r0, r1}
 
 	/* Clear the frame pointer and .bss */
 
 	mov     fp, #0
 
-.Lbssinit:	
+1:
 	cmp		r0, r1				/* Clear up to _bss_end_ */
 	strcc	fp, [r0],#4
-	bcc		.Lbssinit
+	bcc		1b
 
 	/* If the .data section is in a separate, uninitialized address space,
 	 * then we will also need to copy the initial values of of the .data
@@ -653,45 +689,34 @@ __start:
 	adr		r3, .Ldatainit
 	ldmia	r3, {r0, r1, r2}
 
-1:	ldmia	r0!, {r3 - r10}
+2:
+	ldmia	r0!, {r3 - r10}
 	stmia	r1!, {r3 - r10}
 	cmp		r1, r2
-	blt		1b
+	blt		2b
 #endif
 
-	/* Perform early C-level, platform-specific initialization */
+	/* And return to the caller */
 
-	bl		up_boot
+	bx		lr
+	.size	arm_data_initialize, . - arm_data_initialize
 
-#ifdef CONFIG_DEBUG_STACK
+/***************************************************************************
-	/* Write a known value to the IDLE thread stack to support stack
+ * Text-section constants
-	 * monitoring logic
+ ***************************************************************************/
-	 */
-
-	adr		r3, .Lstkinit
-	ldmia	r3, {r0, r1, r2}	/* R0 = start of IDLE stack; R1 = Size of tack; R2 = coloration */
-
-2:								/* Top of the loop */
-	sub		r1, r1, #1			/* R1 = Number of words remaining */
-	cmp		r1, #0				/* Check (nwords == 0) */
-	str		r2, [r0], #4		/* Save stack color word, increment stack address */
-	bne		2b					/* Bottom of the loop */
-
-#endif
-
-	/* Finally branch to the OS entry point */
-
-	mov		lr, #0				/* LR = return address (none) */
-	b		os_start			/* Branch to os_start */
 
 	/* Text-section constants:
 	 *
 	 *   _sbss is the start of the BSS region (see ld.script)
-	 *   _ebss is the end of the BSS regsion (see ld.script)
+	 *   _ebss is the end of the BSS region (see ld.script)
 	 *
-	 * The idle task stack starts at the end of BSS and is of size
+	 * The idle task stack usually starts at the end of BSS and is of size
 	 * CONFIG_IDLETHREAD_STACKSIZE.  The heap continues from there until the
 	 * end of memory.  See g_idle_topstack below.
+	 *
+	 * In the case where CONFIG_BOOT_SDRAM_DATA is defined, the IDLE stack is
+	 * in ISRAM, but the heap is in SDRAM beginning at _ebss and extending
+	 * to the end of SDRAM.
 	 */
 
 #ifndef CONFIG_ARCH_ROMPGTABLE
@@ -708,9 +733,16 @@ __start:
 .Linitparms:
 	.long	_sbss
 	.long	_ebss
-	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE-4
 	.size	.Linitparms, . -.Linitparms
 
+.Lstackpointer:
+#ifdef CONFIG_BOOT_SDRAM_DATA
+	.long	IDLE_STACK_VBASE+CONFIG_IDLETHREAD_STACKSIZE-4
+#else
+	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE-4
+#endif
+	.size	.Lstackpointer, . -.Lstackpointer
+
 #ifdef CONFIG_BOOT_RUNFROMFLASH
 	.type	.Ldatainit, %object
 .Ldatainit:
@@ -723,14 +755,19 @@ __start:
 #ifdef CONFIG_DEBUG_STACK
 	.type	.Lstkinit, %object
 .Lstkinit:
+#ifdef CONFIG_BOOT_SDRAM_DATA
+	.long	IDLE_STACK_VBASE		/* Beginning of the IDLE stack, then words of IDLE stack */
+#else
 	.long	_ebss					/* Beginning of the IDLE stack, then words of IDLE stack */
+#endif
 	.long	(CONFIG_IDLETHREAD_STACKSIZE >> 2)
 	.long	STACK_COLOR				/* Stack coloration word */
 	.size	.Lstkinit, . -.Lstkinit
 #endif
-	.size	.Lvstart, .-.Lvstart
 
-	 /* Data section variables */
+/***************************************************************************
+ * Data section variables
+ ***************************************************************************/
 
 	/* This global variable is unsigned long g_idle_topstack and is
 	 * exported from here only because of its coupling to .Linitparms
@@ -741,7 +778,13 @@ __start:
 	.align	4
 	.globl	g_idle_topstack
 	.type	g_idle_topstack, object
+
 g_idle_topstack:
+
+#ifdef CONFIG_BOOT_SDRAM_DATA
+	.long	IDLE_STACK_VBASE+CONFIG_IDLETHREAD_STACKSIZE
+#else
 	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE
+#endif
 	.size	g_idle_topstack, .-g_idle_topstack
 	.end

arch/arm/src/armv7-a/arm_pghead.S

@@ -80,8 +80,6 @@
  */
 
 #ifdef CONFIG_BOOT_RUNFROMFLASH
-#  define DO_SDRAM_INIT 1
-
   /* Check for the identity mapping:  For this configuration, this would be
    * the case where the virtual beginning of FLASH is the same as the physical
    * beginning of FLASH.
@@ -108,7 +106,6 @@
 
 #elif defined(CONFIG_BOOT_COPYTORAM)
 #  error "configuration not implemented
-#  define DO_SDRAM_INIT 1
 
   /* Check for the identity mapping:  For this configuration, this would be
    * the case where the virtual beginning of FLASH is the same as the physical
@@ -221,18 +218,6 @@ __start:
 	mov		r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
 	msr		cpsr_c, r0
 
-	/* Initialize DRAM using a macro provided by board-specific logic.
-	 *
-	 * This must be done in two cases:
-	 * 1. CONFIG_BOOT_RUNFROMFLASH.  The system is running from FLASH
-	 * 2. CONFIG_BOOT_COPYTORAM.  The system booted from FLASH but
-	 *    will copy itself to SDRAM.
-	 */
-
-#ifdef DO_SDRAM_INIT
-	config_sdram
-#endif
-
 	/* Clear the 16K level 1 page table */
 
 	ldr		r4, .LCppgtable			/* r4=phys. page table */
@@ -665,38 +650,30 @@ __start:
 
 #endif /* CONFIG_BOOT_RUNFROMFLASH */
 
-	/* Zero BSS and set up the stack pointer */
+	/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
-
+	 * ready to use.  Other memory, such as SDRAM, must be initialized before
-	adr		r0, .Linitparms
+	 * it can be used.  up_boot() will perform that memory initialization and
-	ldmia	r0, {r0, r1, sp}
+	 * .bss and .data can be initialized after up_boot() returns.
-
-	/* Clear the frame pointer and .bss */
-
-	mov     fp, #0
-
-.Lbssinit:	
-	cmp		r0, r1				/* Clear up to _bss_end_ */
-	strcc	fp, [r0],#4
-	bcc		.Lbssinit
-
-	/* If the .data section is in a separate, unitialized address space,
-	 * then we will also need to copy the initial values of of the .data
-	 * section from the .text region into that .data region.  This would
-	 * be the case if we are executing from FLASH and the .data section
-	 * lies in a different physical address region OR if we are support
-	 * on-demand paging and the .data section lies in a different virtual
-	 * address region.
 	 */
 
-	adr		r3, .Ldatainit
+	/* Set up the stack pointer and clear the frame pointer */
-	ldmia	r3, {r0, r1, r2}
 
-1:	ldmia	r0!, {r3 - r10}
+	ldr		sp, .Lstackpointer
-	stmia	r1!, {r3 - r10}
+	mov     fp, #0
-	cmp		r1, r2
-	blt		1b
 
-	/* Perform early C-level, platform-specific initialization */
+	/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
+	 * ready to use.  Other memory, such as SDRAM, must be initialized before
+	 * it can be used.  up_boot() will perform that memory initialization and
+	 * .bss and .data can be initialized after up_boot() returns.
+	 */
+
+#ifndef CONFIG_BOOT_SDRAM_DATA
+	bl		arm_data_initialize
+#endif
+
+	/* Perform early C-level, platform-specific initialization.  Logic
+	 * within up_boot() must configure SDRAM and call arm_ram_initailize.
+	 */
 
 	bl		up_boot
 
@@ -708,36 +685,99 @@ __start:
 	adr		r3, .Lstkinit
 	ldmia	r3, {r0, r1, r2}	/* R0 = start of IDLE stack; R1 = Size of tack; R2 = coloration */
 
-2:								/* Top of the loop */
+1:								/* Top of the loop */
 	sub		r1, r1, #1			/* R1 = Number of words remaining */
 	cmp		r1, #0				/* Check (nwords == 0) */
 	str		r2, [r0], #4		/* Save stack color word, increment stack address */
-	bne		2b					/* Bottom of the loop */
+	bne		1b					/* Bottom of the loop */
-
 #endif
 
 	/* Finally branch to the OS entry point */
 
 	mov		lr, #0				/* LR = return address (none) */
 	b		os_start			/* Branch to os_start */
+	.size	.Lvstart, .-.Lvstart
+
+/***************************************************************************
+ * Name: arm_data_initialize
+ ***************************************************************************/
+
+	.global	arm_data_initialize
+	.type	arm_data_initialize, #function
+
+arm_data_initialize:
+
+	/* zero BSS and set up the stack pointer */
+
+	adr		r0, .Linitparms
+	ldmia	r0, {r0, r1}
+
+	/* Clear the frame pointer and .bss */
+
+	mov     fp, #0
+
+1:
+	cmp		r0, r1				/* Clear up to _bss_end_ */
+	strcc	fp, [r0],#4
+	bcc		1b
+
+	/* If the .data section is in a separate, uninitialized address space,
+	 * then we will also need to copy the initial values of of the .data
+	 * section from the .text region into that .data region.  This would
+	 * be the case if we are executing from FLASH and the .data section
+	 * lies in a different physical address region OR if we are support
+	 * on-demand paging and the .data section lies in a different virtual
+	 * address region.
+	 */
+
+#if defined(CONFIG_BOOT_RUNFROMFLASH)
+	adr		r3, .Ldatainit
+	ldmia	r3, {r0, r1, r2}
+
+2:
+	ldmia	r0!, {r3 - r10}
+	stmia	r1!, {r3 - r10}
+	cmp		r1, r2
+	blt		2b
+#endif
+
+	/* And return to the caller */
+
+	bx		lr
+	.size	arm_data_initialize, . - arm_data_initialize
+
+/***************************************************************************
+ * Text-section constants
+ ***************************************************************************/
 
 	/* Text-section constants:
 	 *
 	 *   _sbss is the start of the BSS region (see ld.script)
 	 *   _ebss is the end of the BSS regsion (see ld.script)
 	 *
-	 * The idle task stack starts at the end of BSS and is of size
+	 * The idle task stack usually starts at the end of BSS and is of size
 	 * CONFIG_IDLETHREAD_STACKSIZE.  The heap continues from there until the
 	 * end of memory.  See g_idle_topstack below.
+	 *
+	 * In the case where CONFIG_BOOT_SDRAM_DATA is defined, the IDLE stack is
+	 * in ISRAM, but the heap is in SDRAM beginning at _ebss and extending
+	 * to the end of SDRAM.
 	 */
 
 	.type	.Linitparms, %object
 .Linitparms:
 	.long	_sbss
 	.long	_ebss
-	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE-4
 	.size	.Linitparms, . -.Linitparms
 
+.Lstackpointer:
+#ifdef CONFIG_BOOT_SDRAM_DATA
+	.long	IDLE_STACK_VBASE+CONFIG_IDLETHREAD_STACKSIZE-4
+#else
+	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE-4
+#endif
+	.size	.Lstackpointer, . -.Lstackpointer
+
 	.type	.Ldataspan, %object
 .Ldataspan:
 	.long	PG_L1_DATA_VADDR		/* Virtual address in the L1 table */
@@ -765,15 +805,19 @@ __start:
 #ifdef CONFIG_DEBUG_STACK
 	.type	.Lstkinit, %object
 .Lstkinit:
+#ifdef CONFIG_BOOT_SDRAM_DATA
+	.long	IDLE_STACK_VBASE		/* Beginning of the IDLE stack, then words of IDLE stack */
+#else
 	.long	_ebss					/* Beginning of the IDLE stack, then words of IDLE stack */
+#endif
 	.long	(CONFIG_IDLETHREAD_STACKSIZE >> 2)
 	.long	STACK_COLOR				/* Stack coloration word */
 	.size	.Lstkinit, . -.Lstkinit
 #endif
 
-	.size	.Lvstart, .-.Lvstart
+/***************************************************************************
-
+ * Data section variables
-	 /* Data section variables */
+ ***************************************************************************/
 
 	/* This global variable is unsigned long g_idle_topstack and is
 	 * exported from here only because of its coupling to .Linitparms
@@ -784,7 +828,13 @@ __start:
 	.align	4
 	.globl	g_idle_topstack
 	.type	g_idle_topstack, object
+
 g_idle_topstack:
+
+#ifdef CONFIG_BOOT_SDRAM_DATA
+	.long	IDLE_STACK_VBASE+CONFIG_IDLETHREAD_STACKSIZE
+#else
 	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE
+#endif
 	.size	g_idle_topstack, .-g_idle_topstack
 	.end

arch/arm/src/sama5/Kconfig

@@ -2969,6 +2969,7 @@ config SAMA5_DDRCS
 	bool "External DDR-SDRAM Memory"
 	default n
 	depends on SAMA5_MPDDRC
+	select ARCH_HAVE_SDRAM
 	---help---
 		Build in support for DDR-SDRAM memory resources.
 

arch/arm/src/sama5/chip/sama5d3x_memorymap.h

@@ -616,6 +616,10 @@
 #    endif
 #    define PGTABLE_IN_HIGHSRAM   1
 
+#    ifdef CONFIG_BOOT_SDRAM_DATA
+#      error CONFIG_BOOT_SDRAM_DATA not suupported in this configuration
+#    endif
+
 #  else /* CONFIG_BOOT_RUNFROMISRAM && CONFIG_ARCH_LOWVECTORS */
 
   /* Otherwise, the vectors lie at another location (perhaps in NOR FLASH, perhaps
@@ -629,6 +633,11 @@
 #    endif
 #    define PGTABLE_IN_LOWSRAM    1
 
+#    ifdef CONFIG_BOOT_SDRAM_DATA
+#      define IDLE_STACK_PBASE    (PGTABLE_BASE_PADDR + PGTABLE_SIZE)
+#      define IDLE_STACK_VBASE    (PGTABLE_BASE_VADDR + PGTABLE_SIZE)
+#    endif
+
 #  endif /* CONFIG_BOOT_RUNFROMISRAM && CONFIG_ARCH_LOWVECTORS */
 
   /* In either case, the page table lies in ISRAM.  If ISRAM is not the
@@ -640,6 +649,21 @@
 #    define ARMV7A_PGTABLE_MAPPING 1
 #  endif
 
+#else /* !PGTABLE_BASE_PADDR || !PGTABLE_BASE_VADDR */
+
+  /* Sanity check.. if one is defined, both should be defined */
+
+#  if !defined(PGTABLE_BASE_PADDR) || !defined(PGTABLE_BASE_VADDR)
+#    error "One of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is undefined"
+#  endif
+
+  /* If data is in SDRAM, then the IDLE stack at the beginning of ISRAM */
+
+#    ifdef CONFIG_BOOT_SDRAM_DATA
+#      define IDLE_STACK_PBASE    (SAM_ISRAM0_PADDR + PGTABLE_SIZE)
+#      define IDLE_STACK_VBASE    (SAM_ISRAM0_VADDR + PGTABLE_SIZE)
+#    endif
+
 #endif /* !PGTABLE_BASE_PADDR || !PGTABLE_BASE_VADDR */
 
 /* Level 2 Page table start addresses.

arch/arm/src/sama5/sam_allocateheap.c

@@ -72,7 +72,7 @@
  * start would exclude, for example, any memory at the bottom of the RAM
  * region used for the 16KB page table.  If we are also executing from this
  * same RAM region then CONFIG_RAM_START is not used.  Instead, the value of
- * g_idle_stack is the used; this variable holds the first avaiable byte of
+ * g_idle_stack is the used; this variable holds the first available byte of
  * memory after the .text, .data, .bss, and IDLE stack allocations.
  *
  * CONFIG_RAM_VEND is defined in the configuration it is the usable top of
@@ -94,7 +94,8 @@
 #  undef CONFIG_SAMA5_ISRAM_HEAP
 #endif
 
-#if !defined(CONFIG_SAMA5_DDRCS) || defined(CONFIG_SAMA5_BOOT_SDRAM)
+#if !defined(CONFIG_SAMA5_DDRCS) || defined(CONFIG_SAMA5_BOOT_SDRAM) || \
+    defined(CONFIG_BOOT_SDRAM_DATA)
 #  undef CONFIG_SAMA5_DDRCS_HEAP
 #endif
 
@@ -216,9 +217,20 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
   board_led_on(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)ubase;
   *heap_size  = usize;
-#else
 
-  /* Return the heap settings */
+#elif defined(CONFIG_BOOT_SDRAM_DATA)
+  /* In this case, the IDLE stack is in ISRAM, but data is in SDRAM.  The
+   * heap is at the end of BSS through the configured end of SDRAM.
+   */
+
+  board_led_on(LED_HEAPALLOCATE);
+  *heap_start = (FAR void*)&_ebss;
+  *heap_size  = CONFIG_RAM_VEND - (size_t)&_ebss;
+
+#else
+  /* Both data and the heap are in ISRAM.  The heap is then from the end of
+   * IDLE stack through the configured end of ISRAM.
+   */
 
   board_led_on(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;

arch/arm/src/sama5/sam_boot.c

@@ -633,6 +633,35 @@ void up_boot(void)
   arm_fpuconfig();
 #endif
 
+  /* Perform board-specific initialization,  This must include:
+   *
+   * - Initialization of board-specific memory resources (e.g., SDRAM)
+   * - Configuration of board specific resources (PIOs, LEDs, etc).
+   *
+   * NOTE: We must use caution prior to this point to make sure that
+   * the logic does not access any global variables that might lie
+   * in SDRAM.
+   */
+
+  sam_boardinitialize();
+
+  /* SDRAM was configured in a temporary state to support low-level
+   * initialization.  Now that the SDRAM has been fully initialized,
+   * we can reconfigure the SDRAM in its final, fully cache-able state.
+   */
+
+#ifdef NEED_SDRAM_REMAPPING
+  sam_remap();
+#endif
+
+  /* If .data and .bss reside in SDRAM, then initialize the data sections
+   * now after SDRAM has been initialized.
+   */
+
+#ifdef CONFIG_BOOT_SDRAM_DATA
+  arm_data_initialize();
+#endif
+
   /* Perform common, low-level chip initialization (might do nothing) */
 
   sam_lowsetup();
@@ -654,21 +683,4 @@ void up_boot(void)
 #ifdef CONFIG_NUTTX_KERNEL
   sam_userspace();
 #endif
-
-  /* Perform board-specific initialization,  This must include:
-   *
-   * - Initialization of board-specific memory resources (e.g., SDRAM)
-   * - Configuration of board specific resources (PIOs, LEDs, etc).
-   */
-
-  sam_boardinitialize();
-
-  /* SDRAM was configured in a temporary state to support low-level
-   * ininitialization.  Now that the SDRAM has been fully initialized,
-   * we can reconfigure the SDRAM in its final, fully cache-able state.
-   */
-
-#ifdef NEED_SDRAM_REMAPPING
-  sam_remap();
-#endif
 }

configs/sama5d3x-ek/README.txt

@@ -1284,8 +1284,8 @@ NOR FLASH Support
 SDRAM Support
 =============
 
-  Configuration
+  SRAM Heap Configuration
-  -------------
+  -----------------------
 
   In these configurations, .data and .bss are retained in ISRAM.  SDRAM can
   be initialized and included in the heap.  Relevant configuration settings:
@@ -1350,6 +1350,40 @@ SDRAM Support
     RAMTest: Pattern test: 20000000 268435456 33333333 cccccccc
     RAMTest: Address-in-address test: 20000000 268435456
 
+  SDRAM Data Configuration
+  ------------------------
+ 
+  In these configurations, .data and .bss are retained in ISRAM by default.
+  .data and .bss can also be retained in SDRAM using these slightly
+  different configuration settings.  In this configuration, ISRAM is
+  used only for the Cortex-A5 page table for the IDLE thread stack.
+
+    System Type->ATSAMA5 Peripheral Support
+      CONFIG_SAMA5_MPDDRC=y                 : Enable the DDR controller
+
+    System Type->External Memory Configuration
+      CONFIG_SAMA5_DDRCS=y                  : Tell the system that DRAM is at the DDR CS
+      CONFIG_SAMA5_DDRCS_SIZE=268435456     : 2Gb DRAM -> 256GB
+      CONFIG_SAMA5_DDRCS_LPDDR2=y           : Its DDR2
+      CONFIG_SAMA5_MT47H128M16RT=y          : This is the type of DDR2
+
+    System Type->Heap Configuration
+      CONFIG_SAMA5_ISRAM_HEAP=n              : These do not apply in this case
+      CONFIG_SAMA5_DCRS_HEAP=n
+
+    System Type->Boot Memory Configuration
+      CONFIG_RAM_START=0x20000000           : Physical address of SDRAM
+      CONFIG_RAM_VSTART=0x20000000          : Virtual address of SDRAM
+      CONFIG_RAM_SIZE=268435456             : Size of SDRAM
+      CONFIG_BOOT_SDRAM_DATA=y              : Data is in SDRAM
+
+      Care must be used applied these RAM locations; the graphics
+      configurations use SDRAM in an incompatible way to set aside
+      LCD framebuffers.
+
+    Memory Management
+      CONFIG_MM_REGIONS=1                   : One heap memory region:  ISDRAM
+
 NAND Support
 ============
 
@@ -2676,38 +2710,41 @@ Configurations
        be loaded via SAM-BA.  The are the relevant configuration options
        are provided above in the section entitled "NOR FLASH Support".
 
+    4. Data resides in ISRAM, but can be moved to SDRAM as described above
+       under "SDRAM Data Configuration."
+
     The following features are pre-enabled in the demo configuration, but not
     in the nsh configuration:
 
-    4. SDRAM is supported.  .data and .bss is still retained in ISRAM, but
+    5. SDRAM is supported.  .data and .bss is still retained in ISRAM, but
        SDRAM is initializeed and the SDRAM memory is included in the heap.
        Relevant configuration settings are provided in the paragraph entitled
        "SDRAM Support" above.
 
-    5. The Real Time Clock/Calendar RTC) is enabled.  See the sectino entitled
+    6. The Real Time Clock/Calendar RTC) is enabled.  See the sectino entitled
        "RTC" above.
 
-    6. The Embest or Ronetix CPU module includes an Atmel AT25DF321A,
+    7. The Embest or Ronetix CPU module includes an Atmel AT25DF321A,
        32-megabit, 2.7-volt SPI serial flash.  Support for that serial
        FLASH can is enabled in this configuration.  See the paragraph
        entitle "AT25 Serial FLASH" for detailed configuration settings.
 
-    7. Support for HSMCI car slots. The SAMA5D3x-EK provides a two SD memory
+    8. Support for HSMCI car slots. The SAMA5D3x-EK provides a two SD memory
        card slots:  (1) a full size SD card slot (J7 labelled MCI0), and (2)
        a microSD memory card slot (J6 labelled MCI1).  The full size SD card
        slot connects via HSMCI0; the microSD connects vi HSMCI1.  Relevant
        configuration settings can be found in the section entitle "HSMCI
        Card Slots" above.
 
-    8. Support the USB high-speed device (UDPHS) driver is enabled.  See the
+    9. Support the USB high-speed device (UDPHS) driver is enabled.  See the
        section above entitled "USB High-Speed Device" for relevant NuttX
        configuration settings.
 
-    9. The USB high-speed EHCI and the low-/full- OHCI host drivers are supported
+    10. The USB high-speed EHCI and the low-/full- OHCI host drivers are supported
-       in this configuration.  See the section above entitle "USB High-Speed Host"
+        in this configuration.  See the section above entitle "USB High-Speed Host"
-       for relevant configuration information.
+        for relevant configuration information.
 
-    10. Support SAMA5D3 TRNG peripheral is enabled so that it provides
+    11. Support SAMA5D3 TRNG peripheral is enabled so that it provides
         /dev/random.  See the section entitled "TRNG and /dev/random"
         above for detailed configuration information.
 
@@ -2812,63 +2849,66 @@ Configurations
     4. This configuration has support for NSH built-in applications enabled.
        However, no built-in applications are selected in the base configuration.
 
-    5. This configuration has support for the FAT file system built in.  However,
+    5. Data resides in ISRAM, but can be moved to SDRAM as described above
+       under "SDRAM Data Configuration."
+
+    6. This configuration has support for the FAT file system built in.  However,
        by default, there are no block drivers initialized.  The FAT file system can
        still be used to create RAM disks.
 
-    6. SDRAM support can be enabled by modifying your NuttX configuration as
+    7. SDRAM support can be enabled by modifying your NuttX configuration as
        described above in the paragraph entitle "SDRAM Support"
 
-    7. The Embest or Ronetix CPU module includes an Atmel AT25DF321A,
+    8. The Embest or Ronetix CPU module includes an Atmel AT25DF321A,
        32-megabit, 2.7-volt SPI serial flash.  Support for that serial
        FLASH can be enabled by modifying the NuttX configuration as
        described above in the paragraph entitled "AT25 Serial FLASH".
 
-    8. Enabling HSMCI support. The SAMA5D3x-EK provides a two SD memory card
+    9. Enabling HSMCI support. The SAMA5D3x-EK provides a two SD memory card
        slots:  (1) a full size SD card slot (J7 labeled MCI0), and (2) a
        microSD memory card slot (J6 labeled MCI1).  The full size SD card
        slot connects via HSMCI0; the microSD connects vi HSMCI1.  Support
        for both SD slots can be enabled with the settings provided in the
        paragraph entitled "HSMCI Card Slots" above.
 
-    9. Support the USB low-, high- and full-speed OHCI host driver can be enabled
+    10. Support the USB low-, high- and full-speed OHCI host driver can be enabled
-       by changing the NuttX configuration file as described in the section
+        by changing the NuttX configuration file as described in the section
-       entitled "USB High-Speed Host" above.
+        entitled "USB High-Speed Host" above.
 
-    10. Support the USB high-speed USB device driver (UDPHS) can be enabled
+    11. Support the USB high-speed USB device driver (UDPHS) can be enabled
         by changing the NuttX configuration file as described above in the
         section entitled "USB High-Speed Device."
 
-    11. AT24 Serial EEPROM. A AT24C512 Serial EEPPROM was used for tested
+    12. AT24 Serial EEPROM. A AT24C512 Serial EEPPROM was used for tested
         I2C.  There is, however, no AT24 EEPROM on board the SAMA5D3x-EK:
         The  serial EEPROM was mounted on an external adaptor board and
         connected to the SAMA5D3x-EK thusly.  See the section above entitle
         "AT24 Serial EEPROM" for further information.
 
-    12. I2C Tool. NuttX supports an I2C tool at apps/system/i2c that can be
+    13. I2C Tool. NuttX supports an I2C tool at apps/system/i2c that can be
         used to peek and poke I2C devices.  See the discussion above under
         "I2C Tool" for detailed configuration settings.
 
-    13. Networking support via the can be added to NSH by modifying the
+    14. Networking support via the can be added to NSH by modifying the
         configuration.  See the "Networking" section above for detailed
         configuration settings.
 
-    14. You can enable the touchscreen and a touchscreen by following the
+    15. You can enable the touchscreen and a touchscreen by following the
         configuration instrcutions in the section entitled "Touchscreen
         Testing" above.
 
-    15. The Real Time Clock/Calendar RTC) may be enabled by reconfiguring NuttX.
+    16. The Real Time Clock/Calendar RTC) may be enabled by reconfiguring NuttX.
         See the section entitled "RTC" above for detailed configuration settings.
 
-    16. This example can be configured to exercise the watchdog timer test
+    17. This example can be configured to exercise the watchdog timer test
         (apps/examples/watchdog).  See the detailed configuration settings in
         the section entitled "Watchdog Timer" above.
 
-    17. This example can be configured to enable the SAMA5 TRNG peripheral so
+    18. This example can be configured to enable the SAMA5 TRNG peripheral so
         that it provides /dev/random.  See the section entitled "TRNG and
         /dev/random" above for detailed configuration information.
 
-    18. See also the sections above for additional configuration options:
+    19. See also the sections above for additional configuration options:
         "AT24 Serial EEPROM", "CAN Usage", "SAMA5 ADC Support", "SAMA5 PWM
         Support", "OV2640 Camera Interface", "I2S Audio Support"
 
@@ -3047,6 +3087,9 @@ Configurations
        NOTE:  In order to boot in this configuration, you need to close the
        BMS jumper.
 
+    4. Data resides in ISRAM, but can be moved to SDRAM as described above
+       under "SDRAM Data Configuration."
+
     STATUS:
        See the To-Do list below
 
@@ -3069,18 +3112,14 @@ To-Do List
    have been using the norboot configuration to start the program in NOR
    FLASH (see just above).  See "Creating and Using NORBOOT" above.
 
-3) Currently, these configurations keep all .bss and .data in internal SRAM.
+3) Neither USB OHCI nor EHCI support Isochronous endpoints.  Interrupt
-   The SDRAM is available for heap, but not for static data.  This is
-   because the SDRAM does not get configured until after the system has
-   booted; until after .bss and .data have been initialized.  To change
-   this, the solution would be to port the Bareboard assembly language
-   setup into the NuttX assembly language startup and execute it BEFORE
-   initializing .bss and .data.
-
-4) Neither USB OHCI nor EHCI support Isochronous endpoints.  Interrupt
    endpoint support in the EHCI driver is untested (but works in similar
    EHCI drivers).
 
+4) The logic in "SDRAM Data Configuration" has generated some crashes.
+   Perhaps there are some issues with SDRAM when uses as the primary
+   heap?
+
 5) HSCMI TX DMA support is currently commented out.
 
 6) I believe that there is an issue when the internal AT25 FLASH is

configs/sama5d3x-ek/nsh/defconfig

@@ -211,6 +211,7 @@ CONFIG_ARCH_HAVE_IRQPRIO=y
 # CONFIG_ADDRENV is not set
 CONFIG_ARCH_HAVE_VFORK=y
 CONFIG_ARCH_HAVE_MMU=y
+CONFIG_ARCH_NAND_HWECC=y
 CONFIG_ARCH_IRQPRIO=y
 CONFIG_ARCH_STACKDUMP=y
 # CONFIG_ENDIAN_BIG is not set
@@ -248,6 +249,7 @@ CONFIG_RAM_SIZE=114688
 CONFIG_FLASH_START=0x10000000
 CONFIG_FLASH_VSTART=0x10000000
 CONFIG_FLASH_SIZE=134217728
+# CONFIG_ARCH_HAVE_SDRAM is not set
 
 #
 # Board Selection
@@ -359,7 +361,6 @@ CONFIG_DEV_NULL=y
 # CONFIG_LCD is not set
 # CONFIG_MMCSD is not set
 # CONFIG_MTD is not set
-CONFIG_ARCH_NAND_HWECC=y
 # CONFIG_PIPES is not set
 # CONFIG_PM is not set
 # CONFIG_POWER is not set

configs/sama5d3x-ek/scripts/nor-ddram.ld

@@ -0,0 +1,131 @@
+/****************************************************************************
+ * configs/sama5d3x-ek/scripts/nor-ddram.ld
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The SAMA5D3x-EK has 128MB of NOR flash at CS0 (0x1000:0000).  In this
+ * configuration, the .text and a copy of the .data section will be loaded
+ * into NOR flash.  NuttX .data, .bss, the IDLE stack, and the primary
+ * heap will be allocated in SRAM.  The SAMA5D3 has 128 KB of ISRAM beginning
+ * at virtual address 0x0030:0000.
+ *
+ * The SAMA5D3 has 128 KB of ISRAM beginning at virtual address 0x0030:0000
+ * And 256Mb of SDRAm at address 0x2000:0000.  This script assumes ISRAM used
+ * only for the page table.  All variables are retained in SDRAM.
+ *
+ * Vectors in low memory are assumed to reside at the beginning of NOR flash.
+ */
+
+MEMORY
+{
+	norflash (W!RX) : ORIGIN = 0x10000000, LENGTH = 128M
+	isram    (WR)   : ORIGIN = 0x00304000, LENGTH = 128K - 16K
+	sdram    (W!RX) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(entry)
+ENTRY(_stext)
+
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		*(.ARM.extab*)
+		*(.gnu.linkonce.armextab.*)
+		_etext = ABSOLUTE(.);
+	} > norflash
+
+	.init_section : {
+		_sinit = ABSOLUTE(.);
+		*(.init_array .init_array.*)
+		_einit = ABSOLUTE(.);
+	} > norflash
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} > norflash
+
+	/* .ARM.exidx is sorted, so has to go in its own output section.  */
+
+	PROVIDE_HIDDEN (__exidx_start = .);
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > norflash
+	PROVIDE_HIDDEN (__exidx_end = .);
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sdram AT > norflash
+
+	_eronly = LOADADDR(.data);
+
+	.bss : {
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > sdram
+
+	/* Stabs debugging sections. */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}