From 33df35f003947346c55b81f348d230bf90b4a2fd Mon Sep 17 00:00:00 2001 From: Huang Qi Date: Thu, 30 Dec 2021 18:08:20 +0800 Subject: [PATCH] arch/risc-v: Correct epc adjustment with C ISA Signed-off-by: Huang Qi --- arch/risc-v/src/bl602/bl602_irq_dispatch.c | 2 +- arch/risc-v/src/fe310/fe310_irq_dispatch.c | 2 +- arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/risc-v/src/bl602/bl602_irq_dispatch.c b/arch/risc-v/src/bl602/bl602_irq_dispatch.c index b21aa1c1fb6..1d8c06b8ae5 100644 --- a/arch/risc-v/src/bl602/bl602_irq_dispatch.c +++ b/arch/risc-v/src/bl602/bl602_irq_dispatch.c @@ -67,7 +67,7 @@ void *bl602_dispatch_irq(uint32_t vector, uint32_t *regs) if (BL602_IRQ_ECALLM == irq) { - *mepc += 4; + *mepc += 2; } /* Acknowledge the interrupt */ diff --git a/arch/risc-v/src/fe310/fe310_irq_dispatch.c b/arch/risc-v/src/fe310/fe310_irq_dispatch.c index 26c88e5d7a3..ba3e73601b7 100644 --- a/arch/risc-v/src/fe310/fe310_irq_dispatch.c +++ b/arch/risc-v/src/fe310/fe310_irq_dispatch.c @@ -72,7 +72,7 @@ void *fe310_dispatch_irq(uint32_t vector, uint32_t *regs) if (FE310_IRQ_ECALLM == irq) { - *mepc += 4; + *mepc += 2; } /* Acknowledge the interrupt */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c b/arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c index aba75551a48..ae0fe3bc04a 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c +++ b/arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c @@ -65,7 +65,7 @@ void *rv32m1_dispatch_irq(uint32_t vector, uint32_t *regs) if (RV32M1_IRQ_ECALL_M == irq) { - *mepc += 4; + *mepc += 2; } if (RV32M1_IRQ_INTMUX0 <= irq)