diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c
index 06a994524ca..40b1a29a091 100644
--- a/arch/arm/src/stm32/stm32_spi.c
+++ b/arch/arm/src/stm32/stm32_spi.c
@@ -1368,15 +1368,20 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 
       priv = &g_spi1dev;
 
-      /* Configure SPI1 pins: SCK, MISO, and MOSI */
+      /* Only configure if the port is not already configured */
 
-      stm32_configgpio(GPIO_SPI1_SCK);
-      stm32_configgpio(GPIO_SPI1_MISO);
-      stm32_configgpio(GPIO_SPI1_MOSI);
+      if ((spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_SPE) == 0)
+        {
+          /* Configure SPI1 pins: SCK, MISO, and MOSI */
 
-      /* Set up default configuration: Master, 8-bit, etc. */
+          stm32_configgpio(GPIO_SPI1_SCK);
+          stm32_configgpio(GPIO_SPI1_MISO);
+          stm32_configgpio(GPIO_SPI1_MOSI);
 
-      spi_portinitialize(priv);
+          /* Set up default configuration: Master, 8-bit, etc. */
+
+          spi_portinitialize(priv);
+        }
     }
   else
 #endif
@@ -1387,15 +1392,20 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 
       priv = &g_spi2dev;
 
-      /* Configure SPI2 pins: SCK, MISO, and MOSI */
+      /* Only configure if the port is not already configured */
 
-      stm32_configgpio(GPIO_SPI2_SCK);
-      stm32_configgpio(GPIO_SPI2_MISO);
-      stm32_configgpio(GPIO_SPI2_MOSI);
+      if ((spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_SPE) == 0)
+        {
+          /* Configure SPI2 pins: SCK, MISO, and MOSI */
 
-      /* Set up default configuration: Master, 8-bit, etc. */
+          stm32_configgpio(GPIO_SPI2_SCK);
+          stm32_configgpio(GPIO_SPI2_MISO);
+          stm32_configgpio(GPIO_SPI2_MOSI);
 
-      spi_portinitialize(priv);
+          /* Set up default configuration: Master, 8-bit, etc. */
+
+          spi_portinitialize(priv);
+        }
     }
   else
 #endif
@@ -1406,15 +1416,20 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 
       priv = &g_spi3dev;
 
-      /* Configure SPI3 pins: SCK, MISO, and MOSI */
+      /* Only configure if the port is not already configured */
 
-      stm32_configgpio(GPIO_SPI3_SCK);
-      stm32_configgpio(GPIO_SPI3_MISO);
-      stm32_configgpio(GPIO_SPI3_MOSI);
+      if ((spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_SPE) == 0)
+        {
+          /* Configure SPI3 pins: SCK, MISO, and MOSI */
 
-      /* Set up default configuration: Master, 8-bit, etc. */
+          stm32_configgpio(GPIO_SPI3_SCK);
+          stm32_configgpio(GPIO_SPI3_MISO);
+          stm32_configgpio(GPIO_SPI3_MOSI);
 
-      spi_portinitialize(priv);
+          /* Set up default configuration: Master, 8-bit, etc. */
+
+          spi_portinitialize(priv);
+        }
     }
 #endif