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arch/arm/src/s32k1xx/s32k14x and boards/arm/s32k1xx/s32k146evb/src: Numerous fixes to get a clean build of the S32K146EVB.

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This commit is contained in:
Gregory Nutt
2019-08-19 10:49:50 -06:00
parent 66d66b0616
commit 33ab25ae14
14 changed files with 81 additions and 58 deletions
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boards/arm/s32k1xx/s32k146evb/README.txt
+4 -3
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@@ -16,9 +16,10 @@ Status
2019-08-148 Configuration created but entirely untested. This
configuration is intended, initially, to verify s32k14x architecture
support. This is VERY much a work in progress and you should not
use this configuration unless you are interested in assisting with
the bring-up.
support. The configuration builds and linkes without error but has
not yet been tested. This is VERY much a work in progress and you
should not use this configuration unless you are interested in
assisting with the bring-up.
Serial Console
==============
boards/arm/s32k1xx/s32k146evb/src/s32k146_clockconfig.c
+5 -5
View File
@@ -114,11 +114,11 @@ const struct clock_configuration_s g_initial_clkconfig =
},
.spll =
{
.mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
.prediv = SCG_SPLL_CLOCK_PREDIV_BY_1, /* PREDIV */
.mult = SCG_SPLL_CLOCK_MULTIPLY_BY_28, /* MULT */
.mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
.prediv = 1, /* PREDIV */
.mult = 28, /* MULT */
.src = 0, /* SOURCE */
.initialize = true, /* Initialize */
.stopmode = false, /* */
boards/arm/s32k1xx/s32k146evb/src/s32k146_periphclocks.c
+11 -11
View File
@@ -80,77 +80,77 @@
const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
{
{
.clkname = PCC_ADC0_CLOCK,
.clkname = ADC0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_FIRC,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PCC_ADC1_CLOCK,
.clkname = ADC1_CLK,
.clkgate = true,
.clksrc = CLK_SRC_FIRC,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PCC_LPTMR0_CLOCK,
.clkname = LPTMR0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PCC_LPUART0_CLOCK,
.clkname = LPUART0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PCC_LPUART1_CLOCK,
.clkname = LPUART1_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PCC_LPUART2_CLOCK,
.clkname = LPUART2_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PCC_PORTA_CLOCK,
.clkname = PORTA_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PCC_PORTB_CLOCK,
.clkname = PORTB_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PCC_PORTC_CLOCK,
.clkname = PORTC_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PCC_PORTD_CLOCK,
.clkname = PORTD_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
},
{
.clkname = PCC_PORTE_CLOCK,
.clkname = PORTE_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,