diff --git a/arch/arm/src/stm32l4/stm32l4_comp.h b/arch/arm/src/stm32l4/stm32l4_comp.h index 029c26c7308..6d939520b37 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/stm32l4_comp.h @@ -58,7 +58,7 @@ enum stm32l4_comp_e { STM32L4_COMP1, STM32L4_COMP2, - STM32L4_COMP_NUM /* Number of comparators */ + STM32L4_COMP_NUM /* Number of comparators */ }; /* Plus input */ @@ -94,7 +94,7 @@ enum stm32l4_comp_e { STM32L4_COMP1, STM32L4_COMP2, - STM32L4_COMP_NUM /* Number of comparators */ + STM32L4_COMP_NUM /* Number of comparators */ }; /* Plus input */ diff --git a/drivers/lcd/Kconfig b/drivers/lcd/Kconfig index d432bab3bed..f9914b35e34 100644 --- a/drivers/lcd/Kconfig +++ b/drivers/lcd/Kconfig @@ -331,6 +331,24 @@ config LCD_UG2832HSWEG04 Required SPI driver settings: SPI_CMDDATA - Include support for cmd/data selection. +config LCD_DD12864WO4A + bool "DD-12864WO-4A OLED Display Module" + default n + depends on !LCD_UG2864HSWEG01 && !LCD_UG2832HSWEG04 + select LCD_SSD1306 + select SPI_CMDDATA + ---help--- + OLED Display Module, DD-12864WO-4A, Densitron Technologies + based on the Solomon Tech SSD1309 LCD controller. Used with the + ThingseeOne board. + + Required LCD driver settings: + LCD_MAXCONTRAST should be 255, but any value >0 and <=255 will be accepted. + LCD_MAXPOWER should be 1: 0=off, 1=on + + Required SPI driver settings: + SPI_CMDDATA - Include support for cmd/data selection. + config LCD_SSD1306 bool @@ -359,14 +377,16 @@ if LCD_SSD1306_SPI config SSD1306_SPIMODE int "SSD1306 SPI Mode" - default 0 + default 0 if !LCD_DD12864WO4A + default 3 if LCD_DD12864WO4A range 0 3 ---help--- Selects the SPI mode used with the SSD1306 device config SSD1306_FREQUENCY int "SSD1306 SPI Frequency" - default 3500000 + default 3500000 if !LCD_DD12864WO4A + default 10000000 if LCD_DD12864WO4A ---help--- Selects the SPI bus frequency used with the SSD1306 device diff --git a/drivers/lcd/ssd1306.h b/drivers/lcd/ssd1306.h index f8fcaa3097e..a873bf2e0a2 100644 --- a/drivers/lcd/ssd1306.h +++ b/drivers/lcd/ssd1306.h @@ -65,7 +65,7 @@ #endif #if !defined(CONFIG_LCD_SH1106_OLED_132) && !defined(CONFIG_LCD_UG2864HSWEG01) && \ - !defined(CONFIG_LCD_UG2832HSWEG04) + !defined(CONFIG_LCD_UG2832HSWEG04) && !defined(CONFIG_LCD_DD12864WO4A) # error "Unknown and unsupported SSD1306 LCD" #endif @@ -139,6 +139,10 @@ #define SSD1306_STATUS_ONOFF (0x40) #define SSD1306_RDDATA(d) (d) /* Read Display Data */ +#define SSD1309_PROTOFF (0xfd) +#define SSD1309_SETMEMORY (0x20) +# define SSD1309_MEMADDR(ma) ((ma) & 0x03) + /* Color Properties *******************************************************************/ /* Display Resolution * @@ -152,18 +156,28 @@ # define SSD1306_DEV_XOFFSET 2 /* Offset to logical column 0 */ # define SSD1306_DEV_PAGES 8 /* 8 pages */ # define SSD1306_DEV_CMNPAD 0x12 /* COM configuration */ +# undef IS_SSD1309 #elif defined(CONFIG_LCD_UG2832HSWEG04) # define SSD1306_DEV_NATIVE_XRES 128 /* Only 128 of 131 columns used */ # define SSD1306_DEV_NATIVE_YRES 32 /* 4 pages each 8 rows */ # define SSD1306_DEV_XOFFSET 2 /* Offset to logical column 0 */ # define SSD1306_DEV_PAGES 4 /* 4 pages */ # define SSD1306_DEV_CMNPAD 0x02 /* COM configuration */ +# undef IS_SSD1309 #elif defined(CONFIG_LCD_SH1106_OLED_132) # define SSD1306_DEV_NATIVE_XRES 128 /* Only 128 columns used, supporting 132 is a bit difficult */ # define SSD1306_DEV_NATIVE_YRES 64 /* 8 pages each 8 rows */ # define SSD1306_DEV_XOFFSET 0 /* Offset to logical column 0 */ # define SSD1306_DEV_PAGES 8 /* 8 pages */ # define SSD1306_DEV_CMNPAD 0x12 /* COM configuration */ +# undef IS_SSD1309 +#elif defined(CONFIG_LCD_DD12864WO4A) +# define SSD1306_DEV_NATIVE_XRES 128 /* 128 of 128 columns used */ +# define SSD1306_DEV_NATIVE_YRES 64 /* 8 pages each 8 rows */ +# define SSD1306_DEV_XOFFSET 0 /* Offset to logical column 0 */ +# define SSD1306_DEV_PAGES 8 /* 8 pages */ +# define SSD1306_DEV_CMNPAD 0x10 /* COM configuration */ +# define IS_SSD1309 1 /* SSD1309 based LCD. */ #endif #if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) @@ -194,6 +208,7 @@ /* Default contrast */ #define SSD1306_DEV_CONTRAST (128) +#define SSD1309_DEV_CONTRAST (255) /* The size of the shadow frame buffer or one row buffer. * @@ -230,6 +245,14 @@ # define SSD1306_DEV_REVERSEX 1 # undef SSD1306_DEV_REVERSEY # endif +#elif defined(CONFIG_LCD_DD12864WO4A) +# if defined(CONFIG_LCD_LANDSCAPE) +# define SSD1306_DEV_REVERSEX 1 +# undef SSD1306_DEV_REVERSEY +# elif defined(CONFIG_LCD_RLANDSCAPE) +# undef SSD1306_DEV_REVERSEX +# define SSD1306_DEV_REVERSEY 1 +# endif #endif /* Bit helpers */ diff --git a/drivers/lcd/ssd1306_base.c b/drivers/lcd/ssd1306_base.c index d26808e93d6..0062347bb76 100644 --- a/drivers/lcd/ssd1306_base.c +++ b/drivers/lcd/ssd1306_base.c @@ -1,7 +1,8 @@ /************************************************************************************** * drivers/lcd/ssd1306.c * Driver for Univision UG-2864HSWEG01 OLED display or UG-2832HSWEG04 both with the - * Univision SSD1306 controller in SPI mode + * Univision SSD1306 controller in SPI mode and Densitron DD-12864WO-4A with SSD1309 + * in SPI mode. * * Copyright (C) 2012-2013, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -13,6 +14,8 @@ * Doc No.: SAS1-B020-B, Univision Technology Inc. * 3. SSD1306, 128 X 64 Dot Matrix OLED/PLED, Preliminary Segment/Common Driver with * Controller, Solomon Systech + * 4. SSD1309, 128 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller, + * Solomon Systech * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -198,7 +201,7 @@ static uint8_t g_runbuffer[SSD1306_DEV_ROWSIZE]; static const struct fb_videoinfo_s g_videoinfo = { - .fmt = SSD1306_DEV_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ + .fmt = SSD1306_DEV_COLORFMT, /* Color format: B&W */ .xres = SSD1306_DEV_XRES, /* Horizontal resolution in pixel columns */ .yres = SSD1306_DEV_YRES, /* Vertical resolution in pixel rows */ .nplanes = 1, /* Number of color planes supported */ @@ -813,7 +816,7 @@ FAR struct lcd_dev_s *ssd1306_initialize(FAR struct i2c_master_s *dev, unsigned FAR struct ssd1306_dev_s *priv = &g_oleddev; lcdinfo("Initializing\n"); - DEBUGASSERT(spi && devno == 0); + DEBUGASSERT(dev && devno == 0); #ifdef CONFIG_LCD_SSD1306_SPI priv->spi = dev; @@ -843,6 +846,40 @@ FAR struct lcd_dev_s *ssd1306_initialize(FAR struct i2c_master_s *dev, unsigned /* Configure the device */ +#ifdef IS_SSD1309 + + ssd1306_sendbyte(priv, SSD1309_PROTOFF); /* Unlock driver IC */ + ssd1306_sendbyte(priv, SSD1306_DISPOFF); /* Display off 0xae */ + ssd1306_sendbyte(priv, SSD1309_SETMEMORY); /* Set page addressing mode: 0x0, 0x01 or 0x02 */ + ssd1306_sendbyte(priv, SSD1309_MEMADDR(0x02)); + ssd1306_sendbyte(priv, SSD1306_SETCOLL(0)); /* Set lower column address 0x00 */ + ssd1306_sendbyte(priv, SSD1306_SETCOLH(0)); /* Set higher column address 0x10 */ + ssd1306_sendbyte(priv, SSD1306_STARTLINE(0)); /* Set display start line 0x40 */ + ssd1306_sendbyte(priv, SSD1306_PAGEADDR(0)); /* Set page address (Can ignore) */ + ssd1306_sendbyte(priv, SSD1306_CONTRAST_MODE); /* Contrast control 0x81 */ + ssd1306_sendbyte(priv ,SSD1306_CONTRAST(SSD1309_DEV_CONTRAST)); /* Default contrast 0xff */ + ssd1306_sendbyte(priv, SSD1306_REMAPPLEFT); /* Set segment remap left 95 to 0 | 0xa1 */ + ssd1306_sendbyte(priv, SSD1306_EDISPOFF); /* Normal display off 0xa4 (Can ignore) */ + ssd1306_sendbyte(priv, SSD1306_NORMAL); /* Normal (un-reversed) display mode 0xa6 */ + ssd1306_sendbyte(priv, SSD1306_MRATIO_MODE); /* Multiplex ratio 0xa8 */ + ssd1306_sendbyte(priv, SSD1306_MRATIO(SSD1306_DEV_DUTY)); /* Duty = 1/64 or 1/32 */ + ssd1306_sendbyte(priv, SSD1306_SCANFROMCOM0); /* Com scan direction: Scan from COM[0] to COM[n-1] */ + ssd1306_sendbyte(priv, SSD1306_DISPOFFS_MODE); /* Set display offset 0xd3 */ + ssd1306_sendbyte(priv, SSD1306_DISPOFFS(0)); + ssd1306_sendbyte(priv, SSD1306_CLKDIV_SET); /* Set clock divider 0xd5 */ + ssd1306_sendbyte(priv, SSD1306_CLKDIV(7,0)); /* 0x70 */ + + ssd1306_sendbyte(priv, SSD1306_CHRGPER_SET); /* Set pre-charge period 0xd9 */ + ssd1306_sendbyte(priv, SSD1306_CHRGPER(0x0f,0x0a)); /* 0xfa: Fh cycles for discharge and Ah cycles for pre-charge */ + + ssd1306_sendbyte(priv, SSD1306_CMNPAD_CONFIG); /* Set common pads / set com pins hardware configuration 0xda */ + ssd1306_sendbyte(priv, SSD1306_CMNPAD(SSD1306_DEV_CMNPAD)); /* 0x12 or 0x02 */ + + ssd1306_sendbyte(priv, SSD1306_VCOM_SET); /* set vcomh 0xdb */ + ssd1306_sendbyte(priv, SSD1306_VCOM(0x3C)); + +#else + ssd1306_sendbyte(priv, SSD1306_DISPOFF); /* Display off 0xae */ ssd1306_sendbyte(priv, SSD1306_SETCOLL(0)); /* Set lower column address 0x00 */ ssd1306_sendbyte(priv, SSD1306_SETCOLH(0)); /* Set higher column address 0x10 */ @@ -876,6 +913,8 @@ FAR struct lcd_dev_s *ssd1306_initialize(FAR struct i2c_master_s *dev, unsigned //ssd1306_sendbyte(priv, SSD1306_DCDC_MODE); /* DC/DC control mode: on (SSD1306 Not supported) */ //ssd1306_sendbyte(priv, SSD1306_DCDC_ON); +#endif + ssd1306_sendbyte(priv, SSD1306_DISPON); /* Display ON 0xaf */ /* De-select and unlock the device */