LPC1788 updates from Rommel Marcelo

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5696 42af7a65-404d-4744-a932-0658087f49c3

configs/open1788/scripts/ld.script

@@ -37,8 +37,8 @@
 /* The LPC1788 has 512Kb of FLASH beginning at address 0x0000:0000 and
  * 96Kb of total SRAM: 64Kb of SRAM in the CPU block beginning at address
  * 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8Kb at addresses
- * 0x20000000 bank0 first and 8kb at 0x20020000 at bank0 second. And 16Kb
- * at 0x20040000 on bank1.
+ * 0x20000000 bank0 first and 8kb at 0x20002000 at bank0 second. And 16Kb
+ * at 0x20004000 on bank1.
  *
  * Here we assume that .data and .bss will all fit into the 64Kb CPU SRAM
  * address range.
@@ -48,8 +48,9 @@ MEMORY
 {
     FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
     SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
-    PSRAM0 (rwx) : ORIGIN = 0x20000000, LENGTH = 16K /* Peripheral SRAM Bank 0 */
-    PSRAM1 (rwx) : ORIGIN = 0x20040000, LENGTH = 16K /* Peripheral SRAM Bank 1 */
+    AHBRAM8_B0A(rwx): ORIGIN = 0x20000000, LENGTH = 8K
+    AHBRAM8_B0B(rwx): ORIGIN = 0x20002000, LENGTH = 8K
+    AHBRAM16(rwx): ORIGIN = 0x20004000, LENGTH = 16K
 }
 
 OUTPUT_ARCH(arm)
@@ -86,6 +87,7 @@ SECTIONS
     .ARM.exidx : {
         *(.ARM.exidx*)
     } > FLASH
+
     __exidx_end = ABSOLUTE(.);
 
     _eronly = ABSOLUTE(.);
@@ -105,20 +107,8 @@ SECTIONS
         *(COMMON)
         _ebss = ABSOLUTE(.);
     } > SRAM
-/*
-    .psram0 (NOLOAD) :
-    {
-        *(.psram0)
-        . = ALIGN(4)
-    } > PSRAM0
 
 
-    .psram1 (NOLOAD) :
-    {
-        *(.psram1)
-        . = ALIGN(4)
-    } > PSRAM1
-*/
     /* Stabs debugging sections */
 
     .stab 0 : { *(.stab) }