diff --git a/arch/mips/src/common/up_initialize.c b/arch/mips/src/common/up_initialize.c
index 682d3f006a2..b60662e824d 100644
--- a/arch/mips/src/common/up_initialize.c
+++ b/arch/mips/src/common/up_initialize.c
@@ -86,7 +86,7 @@ void up_initialize(void)
 {
   /* Initialize global variables */
 
-  g_current_regs = NULL;
+  CURRENT_REGS = NULL;
 
   /* Add any extra memory fragments to the memory manager */
 
diff --git a/arch/mips/src/common/up_internal.h b/arch/mips/src/common/up_internal.h
index e8253c186c7..1c5ff32f63c 100644
--- a/arch/mips/src/common/up_internal.h
+++ b/arch/mips/src/common/up_internal.h
@@ -93,8 +93,8 @@
  * only a referenced is passed to get the state from the TCB.
  */
 
-#define up_savestate(regs)    up_copystate(regs, (uint32_t*)g_current_regs)
-#define up_restorestate(regs) (g_current_regs = regs)
+#define up_savestate(regs)    up_copystate(regs, (uint32_t*)CURRENT_REGS)
+#define up_restorestate(regs) (CURRENT_REGS = regs)
 
 /****************************************************************************
  * Public Types
@@ -109,11 +109,28 @@ typedef void (*up_vector_t)(void);
  ****************************************************************************/
 
 #ifndef __ASSEMBLY__
-/* This holds a references to the current interrupt level register storage
- * structure.  If is non-NULL only during interrupt processing.
+/* g_current_regs holds a references to the current interrupt level
+ * register storage structure.  It is non-NULL only during interrupt
+ * processing.  Access to g_current_regs must be through the macro
+ * CURRENT_REGS for portability.
  */
 
-extern volatile uint32_t *g_current_regs;
+#ifdef CONFIG_SMP
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+int up_cpu_index(void); /* See include/nuttx/arch.h */
+extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
+#  define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#else
+
+extern volatile uint32_t *g_current_regs[1];
+#  define CURRENT_REGS (g_current_regs[0])
+
+#endif
+
 
 /* This is the beginning of heap as provided from up_head.S. This is the
  * first address in DRAM after the loaded program+bss+idle stack.  The end
diff --git a/arch/mips/src/common/up_interruptcontext.c b/arch/mips/src/common/up_interruptcontext.c
index 581f254bcd2..ab0807ee96b 100644
--- a/arch/mips/src/common/up_interruptcontext.c
+++ b/arch/mips/src/common/up_interruptcontext.c
@@ -66,5 +66,5 @@
 
 bool up_interrupt_context(void)
 {
-  return g_current_regs != NULL;
+  return CURRENT_REGS != NULL;
 }
diff --git a/arch/mips/src/mips32/up_assert.c b/arch/mips/src/mips32/up_assert.c
index 8656f2977e4..8df546fbea2 100644
--- a/arch/mips/src/mips32/up_assert.c
+++ b/arch/mips/src/mips32/up_assert.c
@@ -86,7 +86,7 @@ static void _up_assert(int errorcode)
 
   /* Are we in an interrupt handler or the idle task? */
 
-  if (g_current_regs || running_task()->flink == NULL)
+  if (CURRENT_REGS || running_task()->flink == NULL)
     {
       up_irq_save();
       for (; ; )
diff --git a/arch/mips/src/mips32/up_blocktask.c b/arch/mips/src/mips32/up_blocktask.c
index e9648f2388c..06668b6a515 100644
--- a/arch/mips/src/mips32/up_blocktask.c
+++ b/arch/mips/src/mips32/up_blocktask.c
@@ -117,7 +117,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
 
       /* Are we in an interrupt handler? */
 
-      if (g_current_regs)
+      if (CURRENT_REGS)
         {
           /* Yes, then we have to do things differently.
            * Just copy the g_current_regs into the OLD rtcb.
diff --git a/arch/mips/src/mips32/up_doirq.c b/arch/mips/src/mips32/up_doirq.c
index afa17bf4a5e..d178be8f478 100644
--- a/arch/mips/src/mips32/up_doirq.c
+++ b/arch/mips/src/mips32/up_doirq.c
@@ -84,8 +84,8 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
    * Nested interrupts are not supported
    */
 
-  DEBUGASSERT(g_current_regs == NULL);
-  g_current_regs = regs;
+  DEBUGASSERT(CURRENT_REGS == NULL);
+  CURRENT_REGS = regs;
 
   /* Disable further occurrences of this interrupt (until the interrupt
    * srouce have been cleared by the driver).
@@ -105,12 +105,12 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
    * returning from the interrupt.
    */
 
-  if (regs != g_current_regs)
+  if (regs != CURRENT_REGS)
     {
 #ifdef CONFIG_ARCH_FPU
       /* Restore floating point registers */
 
-      up_restorefpu((uint32_t *)g_current_regs);
+      up_restorefpu((uint32_t *)CURRENT_REGS);
 #endif
 
 #ifdef CONFIG_ARCH_ADDRENV
@@ -131,13 +131,13 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
    * switch occurred during interrupt processing.
    */
 
-  regs = (uint32_t *)g_current_regs;
+  regs = (uint32_t *)CURRENT_REGS;
 
   /* Set g_current_regs to NULL to indicate that we are no longer in an
    * interrupt handler.
    */
 
-  g_current_regs = NULL;
+  CURRENT_REGS = NULL;
 
   /* Unmask the last interrupt (global interrupts are still disabled) */
 
diff --git a/arch/mips/src/mips32/up_dumpstate.c b/arch/mips/src/mips32/up_dumpstate.c
index 59d86eac1d4..e1dce51589c 100644
--- a/arch/mips/src/mips32/up_dumpstate.c
+++ b/arch/mips/src/mips32/up_dumpstate.c
@@ -100,38 +100,38 @@ static inline void up_registerdump(void)
 {
   /* Are user registers available from interrupt processing? */
 
-  if (g_current_regs)
+  if (CURRENT_REGS)
     {
       _alert("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n",
-            g_current_regs[REG_MFLO], g_current_regs[REG_MFHI],
-            g_current_regs[REG_EPC], g_current_regs[REG_STATUS]);
+            CURRENT_REGS[REG_MFLO], CURRENT_REGS[REG_MFHI],
+            CURRENT_REGS[REG_EPC], CURRENT_REGS[REG_STATUS]);
       _alert("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n",
-            g_current_regs[REG_AT], g_current_regs[REG_V0],
-            g_current_regs[REG_V1], g_current_regs[REG_A0],
-            g_current_regs[REG_A1], g_current_regs[REG_A2],
-            g_current_regs[REG_A3]);
+            CURRENT_REGS[REG_AT], CURRENT_REGS[REG_V0],
+            CURRENT_REGS[REG_V1], CURRENT_REGS[REG_A0],
+            CURRENT_REGS[REG_A1], CURRENT_REGS[REG_A2],
+            CURRENT_REGS[REG_A3]);
       _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x "
              "T6:%08x T7:%08x\n",
-            g_current_regs[REG_T0], g_current_regs[REG_T1],
-            g_current_regs[REG_T2], g_current_regs[REG_T3],
-            g_current_regs[REG_T4], g_current_regs[REG_T5],
-            g_current_regs[REG_T6], g_current_regs[REG_T7]);
+            CURRENT_REGS[REG_T0], CURRENT_REGS[REG_T1],
+            CURRENT_REGS[REG_T2], CURRENT_REGS[REG_T3],
+            CURRENT_REGS[REG_T4], CURRENT_REGS[REG_T5],
+            CURRENT_REGS[REG_T6], CURRENT_REGS[REG_T7]);
       _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x "
              "S6:%08x S7:%08x\n",
-            g_current_regs[REG_S0], g_current_regs[REG_S1],
-            g_current_regs[REG_S2], g_current_regs[REG_S3],
-            g_current_regs[REG_S4], g_current_regs[REG_S5],
-            g_current_regs[REG_S6], g_current_regs[REG_S7]);
+            CURRENT_REGS[REG_S0], CURRENT_REGS[REG_S1],
+            CURRENT_REGS[REG_S2], CURRENT_REGS[REG_S3],
+            CURRENT_REGS[REG_S4], CURRENT_REGS[REG_S5],
+            CURRENT_REGS[REG_S6], CURRENT_REGS[REG_S7]);
 #ifdef MIPS32_SAVE_GP
       _alert("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n",
-            g_current_regs[REG_T8], g_current_regs[REG_T9],
-            g_current_regs[REG_GP], g_current_regs[REG_SP],
-            g_current_regs[REG_FP], g_current_regs[REG_RA]);
+            CURRENT_REGS[REG_T8], CURRENT_REGS[REG_T9],
+            CURRENT_REGS[REG_GP], CURRENT_REGS[REG_SP],
+            CURRENT_REGS[REG_FP], CURRENT_REGS[REG_RA]);
 #else
       _alert("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n",
-            g_current_regs[REG_T8], g_current_regs[REG_T9],
-            g_current_regs[REG_SP], g_current_regs[REG_FP],
-            g_current_regs[REG_RA]);
+            CURRENT_REGS[REG_T8], CURRENT_REGS[REG_T9],
+            CURRENT_REGS[REG_SP], CURRENT_REGS[REG_FP],
+            CURRENT_REGS[REG_RA]);
 #endif
     }
 }
@@ -202,7 +202,7 @@ void up_dumpstate(void)
       sp = g_intstackbase;
       _alert("sp:     %08x\n", sp);
     }
-  else if (g_current_regs)
+  else if (CURRENT_REGS)
     {
       _alert("ERROR: Stack pointer is not within the interrupt stack\n");
       up_stackdump(istackbase - istacksize, istackbase);
diff --git a/arch/mips/src/mips32/up_initialstate.c b/arch/mips/src/mips32/up_initialstate.c
index 9ed793983b6..6ce523c0127 100644
--- a/arch/mips/src/mips32/up_initialstate.c
+++ b/arch/mips/src/mips32/up_initialstate.c
@@ -63,7 +63,7 @@
  *   the processor specific portions of the new TCB.
  *
  *   This function must setup the initial architecture registers
- *   and/or  stack so that execution will begin at tcb->start
+ *   and/or stack so that execution will begin at tcb->start
  *   on the next context switch.
  *
  ****************************************************************************/
@@ -80,7 +80,7 @@ void up_initial_state(struct tcb_s *tcb)
   /* Save the initial stack pointer.  Hmmm.. the stack is set to the very
    * beginning of the stack region.  Some functions may want to store data on
    * the caller's stack and it might be good to reserve some space.  However,
-   * only the start function would do that and we have control over that one
+   * only the start function would do that and we have control over that one.
    */
 
   xcp->regs[REG_SP]      = (uint32_t)tcb->adj_stack_ptr;
diff --git a/arch/mips/src/mips32/up_releasepending.c b/arch/mips/src/mips32/up_releasepending.c
index 3adb1de04a3..c9d3473b781 100644
--- a/arch/mips/src/mips32/up_releasepending.c
+++ b/arch/mips/src/mips32/up_releasepending.c
@@ -86,7 +86,7 @@ void up_release_pending(void)
 
       /* Are we operating in interrupt context? */
 
-      if (g_current_regs)
+      if (CURRENT_REGS)
         {
           /* Yes, then we have to do things differently.
            * Just copy the g_current_regs into the OLD rtcb.
diff --git a/arch/mips/src/mips32/up_reprioritizertr.c b/arch/mips/src/mips32/up_reprioritizertr.c
index addd44b42d3..d9fdffc16d5 100644
--- a/arch/mips/src/mips32/up_reprioritizertr.c
+++ b/arch/mips/src/mips32/up_reprioritizertr.c
@@ -140,7 +140,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
 
           /* Are we in an interrupt handler? */
 
-          if (g_current_regs)
+          if (CURRENT_REGS)
             {
               /* Yes, then we have to do things differently.
                * Just copy the g_current_regs into the OLD rtcb.
diff --git a/arch/mips/src/mips32/up_schedulesigaction.c b/arch/mips/src/mips32/up_schedulesigaction.c
index b8bf89df3dc..ad31e5e085c 100644
--- a/arch/mips/src/mips32/up_schedulesigaction.c
+++ b/arch/mips/src/mips32/up_schedulesigaction.c
@@ -107,8 +107,8 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
        * being delivered to the currently executing task.
        */
 
-      sinfo("rtcb=0x%p g_current_regs=0x%p\n",
-            this_task(), g_current_regs);
+      sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n",
+            this_task(), CURRENT_REGS);
 
       if (tcb == this_task())
         {
@@ -116,7 +116,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
            * a task is signalling itself for some reason.
            */
 
-          if (!g_current_regs)
+          if (!CURRENT_REGS)
             {
               /* In this case just deliver the signal now. */
 
@@ -143,18 +143,18 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
                */
 
               tcb->xcp.sigdeliver       = sigdeliver;
-              tcb->xcp.saved_epc        = g_current_regs[REG_EPC];
-              tcb->xcp.saved_status     = g_current_regs[REG_STATUS];
+              tcb->xcp.saved_epc        = CURRENT_REGS[REG_EPC];
+              tcb->xcp.saved_status     = CURRENT_REGS[REG_STATUS];
 
               /* Then set up to vector to the trampoline with interrupts
                * disabled
                */
 
-              g_current_regs[REG_EPC]      = (uint32_t)up_sigdeliver;
-              status                     = g_current_regs[REG_STATUS];
+              CURRENT_REGS[REG_EPC]      = (uint32_t)up_sigdeliver;
+              status                     = CURRENT_REGS[REG_STATUS];
               status                    &= ~CP0_STATUS_IM_MASK;
               status                    |= CP0_STATUS_IM_SWINTS;
-              g_current_regs[REG_STATUS]   = status;
+              CURRENT_REGS[REG_STATUS]   = status;
 
               /* And make sure that the saved context in the TCB
                * is the same as the interrupt return context.
@@ -164,7 +164,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
               sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n",
                     tcb->xcp.saved_epc, tcb->xcp.saved_status,
-                    g_current_regs[REG_EPC], g_current_regs[REG_STATUS]);
+                    CURRENT_REGS[REG_EPC], CURRENT_REGS[REG_STATUS]);
             }
         }
 
diff --git a/arch/mips/src/mips32/up_swint0.c b/arch/mips/src/mips32/up_swint0.c
index a372007af51..600dbad2adb 100644
--- a/arch/mips/src/mips32/up_swint0.c
+++ b/arch/mips/src/mips32/up_swint0.c
@@ -138,7 +138,7 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
   uint32_t *regs = (uint32_t *)context;
   uint32_t cause;
 
-  DEBUGASSERT(regs && regs == g_current_regs);
+  DEBUGASSERT(regs && regs == CURRENT_REGS);
 
   /* Software interrupt 0 is invoked with REG_A0 (REG_R4) = system call
    * command and REG_A1-3 and REG_T0-2 (REG_R5-10) = variable number of
@@ -173,7 +173,7 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
       case SYS_restore_context:
         {
           DEBUGASSERT(regs[REG_A1] != 0);
-          g_current_regs = (uint32_t *)regs[REG_A1];
+          CURRENT_REGS = (uint32_t *)regs[REG_A1];
         }
         break;
 
@@ -197,7 +197,7 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
         {
           DEBUGASSERT(regs[REG_A1] != 0 && regs[REG_A2] != 0);
           up_copystate((uint32_t *)regs[REG_A1], regs);
-          g_current_regs = (uint32_t *)regs[REG_A2];
+          CURRENT_REGS = (uint32_t *)regs[REG_A2];
         }
         break;
 
@@ -227,7 +227,7 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
            * the original mode.
            */
 
-          g_current_regs[REG_EPC] = rtcb->xcp.syscall[index].sysreturn;
+          CURRENT_REGS[REG_EPC] = rtcb->xcp.syscall[index].sysreturn;
 #error "Missing logic -- need to restore the original mode"
           rtcb->xcp.nsyscalls     = index;
 
@@ -254,7 +254,7 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
 
           /* Verify that the SYS call number is within range */
 
-          DEBUGASSERT(g_current_regs[REG_A0] < SYS_maxsyscall);
+          DEBUGASSERT(CURRENT_REGS[REG_A0] < SYS_maxsyscall);
 
           /* Make sure that we got here that there is a no saved syscall
            * return address.  We cannot yet handle nested system calls.
@@ -273,7 +273,7 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
 
           /* Offset R0 to account for the reserved values */
 
-          g_current_regs[REG_R0] -= CONFIG_SYS_RESERVED;
+          CURRENT_REGS[REG_R0] -= CONFIG_SYS_RESERVED;
 
           /* Indicate that we are in a syscall handler. */
 
@@ -288,10 +288,10 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
   /* Report what happened.  That might difficult in the case of a context switch */
 
 #ifdef CONFIG_DEBUG_SYSCALL_INFO
-  if (regs != g_current_regs)
+  if (regs != CURRENT_REGS)
     {
       svcinfo("SWInt Return: Context switch!\n");
-      up_registerdump((const uint32_t *)g_current_regs);
+      up_registerdump((const uint32_t *)CURRENT_REGS);
     }
   else
     {
diff --git a/arch/mips/src/mips32/up_unblocktask.c b/arch/mips/src/mips32/up_unblocktask.c
index c5ca4794dae..56e62357e66 100644
--- a/arch/mips/src/mips32/up_unblocktask.c
+++ b/arch/mips/src/mips32/up_unblocktask.c
@@ -100,7 +100,7 @@ void up_unblock_task(struct tcb_s *tcb)
 
       /* Are we in an interrupt handler? */
 
-      if (g_current_regs)
+      if (CURRENT_REGS)
         {
           /* Yes, then we have to do things differently.
            * Just copy the g_current_regs into the OLD rtcb.
diff --git a/arch/mips/src/pic32mx/pic32mx-decodeirq.c b/arch/mips/src/pic32mx/pic32mx-decodeirq.c
index 912cb3ce952..82c9ec44983 100644
--- a/arch/mips/src/pic32mx/pic32mx-decodeirq.c
+++ b/arch/mips/src/pic32mx/pic32mx-decodeirq.c
@@ -105,11 +105,11 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
    */
 
 #ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS
-  savestate = (uint32_t *)g_current_regs;
+  savestate = (uint32_t *)CURRENT_REGS;
 #else
-  DEBUGASSERT(g_current_regs == NULL);
+  DEBUGASSERT(CURRENT_REGS == NULL);
 #endif
-  g_current_regs = regs;
+  CURRENT_REGS = regs;
 
   /* Loop while there are pending interrupts with priority greater than zero */
 
@@ -146,7 +146,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
    * switch occurred during interrupt processing.
    */
 
-  regs = (uint32_t *)g_current_regs;
+  regs = (uint32_t *)CURRENT_REGS;
 
 #if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV)
   /* Check for a context switch.  If a context switch occurred, then
@@ -156,12 +156,12 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
    * returning from the interrupt.
    */
 
-  if (regs != g_current_regs)
+  if (regs != CURRENT_REGS)
     {
 #ifdef CONFIG_ARCH_FPU
       /* Restore floating point registers */
 
-      up_restorefpu((uint32_t *)g_current_regs);
+      up_restorefpu((uint32_t *)CURRENT_REGS);
 #endif
 
 #ifdef CONFIG_ARCH_ADDRENV
@@ -186,13 +186,13 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
    * of fixing nested context switching.  The logic here is insufficient.
    */
 
-  g_current_regs = savestate;
-  if (g_current_regs == NULL)
+  CURRENT_REGS = savestate;
+  if (CURRENT_REGS == NULL)
     {
       board_autoled_off(LED_INIRQ);
     }
 #else
-  g_current_regs = NULL;
+  CURRENT_REGS = NULL;
   board_autoled_off(LED_INIRQ);
 #endif
 
diff --git a/arch/mips/src/pic32mx/pic32mx-exception.c b/arch/mips/src/pic32mx/pic32mx-exception.c
index 6117bbb4389..332c70f2073 100644
--- a/arch/mips/src/pic32mx/pic32mx-exception.c
+++ b/arch/mips/src/pic32mx/pic32mx-exception.c
@@ -177,7 +177,7 @@ uint32_t *pic32mx_exception(uint32_t *regs)
 
   /* Crash with currents_regs set so that we can dump the register contents. */
 
-  g_current_regs = regs;
+  CURRENT_REGS = regs;
   PANIC();
   return regs; /* Won't get here */
 }
diff --git a/arch/mips/src/pic32mx/pic32mx-irq.c b/arch/mips/src/pic32mx/pic32mx-irq.c
index a45ccaf3841..5b4f729bd0c 100644
--- a/arch/mips/src/pic32mx/pic32mx-irq.c
+++ b/arch/mips/src/pic32mx/pic32mx-irq.c
@@ -68,7 +68,7 @@
  * Public Data
  ****************************************************************************/
 
-volatile uint32_t *g_current_regs;
+volatile uint32_t *g_current_regs[1];
 
 /****************************************************************************
  * Private Data
@@ -159,7 +159,7 @@ void up_irqinitialize(void)
 
   /* currents_regs is non-NULL only while processing an interrupt */
 
-  g_current_regs = NULL;
+  CURRENT_REGS = NULL;
 
   /* And finally, enable interrupts */
 
diff --git a/arch/mips/src/pic32mz/pic32mz-decodeirq.c b/arch/mips/src/pic32mz/pic32mz-decodeirq.c
index 03712a4ee73..fa909db805f 100644
--- a/arch/mips/src/pic32mz/pic32mz-decodeirq.c
+++ b/arch/mips/src/pic32mz/pic32mz-decodeirq.c
@@ -105,11 +105,11 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs)
    */
 
 #ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
-  savestate = (uint32_t *)g_current_regs;
+  savestate = (uint32_t *)CURRENT_REGS;
 #else
-  DEBUGASSERT(g_current_regs == NULL);
+  DEBUGASSERT(CURRENT_REGS == NULL);
 #endif
-  g_current_regs = regs;
+  CURRENT_REGS = regs;
 
   /* Loop while there are pending interrupts with priority greater than zero */
 
@@ -146,7 +146,7 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs)
    * switch occurred during interrupt processing.
    */
 
-  regs = (uint32_t *)g_current_regs;
+  regs = (uint32_t *)CURRENT_REGS;
 
 #if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV)
   /* Check for a context switch.  If a context switch occurred, then
@@ -156,12 +156,12 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs)
    * returning from the interrupt.
    */
 
-  if (regs != g_current_regs)
+  if (regs != CURRENT_REGS)
     {
 #ifdef CONFIG_ARCH_FPU
       /* Restore floating point registers */
 
-      up_restorefpu((uint32_t *)g_current_regs);
+      up_restorefpu((uint32_t *)CURRENT_REGS);
 #endif
 
 #ifdef CONFIG_ARCH_ADDRENV
@@ -186,13 +186,13 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs)
    * of fixing nested context switching.  The logic here is insufficient.
    */
 
-  g_current_regs = savestate;
-  if (g_current_regs == NULL)
+  CURRENT_REGS = savestate;
+  if (CURRENT_REGS == NULL)
     {
       board_autoled_off(LED_INIRQ);
     }
 #else
-  g_current_regs = NULL;
+  CURRENT_REGS = NULL;
   board_autoled_off(LED_INIRQ);
 #endif
 
diff --git a/arch/mips/src/pic32mz/pic32mz-exception.c b/arch/mips/src/pic32mz/pic32mz-exception.c
index c6ce5ee7510..433c5183268 100644
--- a/arch/mips/src/pic32mz/pic32mz-exception.c
+++ b/arch/mips/src/pic32mz/pic32mz-exception.c
@@ -177,7 +177,7 @@ uint32_t *pic32mz_exception(uint32_t *regs)
 
   /* Crash with currents_regs set so that we can dump the register contents. */
 
-  g_current_regs = regs;
+  CURRENT_REGS = regs;
   PANIC();
   return regs; /* Won't get here */
 }
diff --git a/arch/mips/src/pic32mz/pic32mz-irq.c b/arch/mips/src/pic32mz/pic32mz-irq.c
index 999e99a378a..11a5fb677b1 100644
--- a/arch/mips/src/pic32mz/pic32mz-irq.c
+++ b/arch/mips/src/pic32mz/pic32mz-irq.c
@@ -73,7 +73,13 @@
  * Public Data
  ****************************************************************************/
 
-volatile uint32_t *g_current_regs;
+/* g_current_regs holds a references to the current interrupt level
+ * register storage structure.  It is non-NULL only during interrupt
+ * processing.  Access to g_current_regs must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
 
 /****************************************************************************
  * Private Data
@@ -241,7 +247,7 @@ void up_irqinitialize(void)
 
   /* currents_regs is non-NULL only while processing an interrupt */
 
-  g_current_regs = NULL;
+  CURRENT_REGS = NULL;
 
   /* And finally, enable interrupts */