diff --git a/arch/arm/src/efm32/efm32_adc.c b/arch/arm/src/efm32/efm32_adc.c index bf3cbc665ba..d8bbb6f164c 100644 --- a/arch/arm/src/efm32/efm32_adc.c +++ b/arch/arm/src/efm32/efm32_adc.c @@ -68,11 +68,11 @@ /* Some ADC peripheral must be enabled */ -#if defined(CONFIG_EFM32_ADC1) +#if defined(CONFIG_EFM32_ADC1) -/* This implementation is for the EFM32 F1, F2, and F4 only */ +/* This implementation is for the EFM32GG Only */ -#if defined(CONFIG_EFM32_EFM32GG) +#if defined(CONFIG_EFM32_EFM32GG) /**************************************************************************** * Pre-processor Definitions @@ -135,7 +135,7 @@ static void adc_timstart(FAR struct efm32_dev_s *priv, bool enable); static int adc_timinit(FAR struct efm32_dev_s *priv); #endif -#if defined(CONFIG_EFM32_EFM32GG) +#if defined(CONFIG_EFM32_EFM32GG) static void adc_startconv(FAR struct efm32_dev_s *priv, bool enable); #endif @@ -1280,6 +1280,6 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch return dev; } -#endif /* CONFIG_EFM32_EFM32F10XX || CONFIG_EFM32_EFM32F20XX || CONFIG_EFM32_EFM32F40XX */ -#endif /* CONFIG_EFM32_ADC || CONFIG_EFM32_ADC2 || CONFIG_EFM32_ADC3 */ +#endif /* CONFIG_EFM32_EFM32GG */ +#endif /* CONFIG_EFM32_ADC1 */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/efm32/efm32_bitband.c b/arch/arm/src/efm32/efm32_bitband.c index 5bb1b5ecb46..cb3f200da4d 100644 --- a/arch/arm/src/efm32/efm32_bitband.c +++ b/arch/arm/src/efm32/efm32_bitband.c @@ -49,11 +49,11 @@ #if defined(CONFIG_EFM32_BITBAND) -#ifndef EFM32_BITBAND_PER_BASE +#ifndef EFM32_BITBAND_PER_BASE # error "EFM32_BITBAND_PER_BASE not declared bitband may be not supported?" #endif -#ifndef EFM32_BITBAND_RAM_BASE +#ifndef EFM32_BITBAND_RAM_BASE # error "EFM32_BITBAND_RAM_BASE not declared bitband may be not supported?" #endif @@ -73,39 +73,40 @@ * Private Functions ****************************************************************************/ - /****************************************************************************** * Name: bitband_set_peripheral + * + * Description: * Perform bit-band write operation on peripheral memory location. * - * Description * Bit-banding provides atomic read-modify-write cycle for single bit * modification. Please refer to the reference manual for further details * about bit-banding. * * Note * This function is only atomic on cores which fully support bitbanding. - * - * Parameters - * addr Peripheral address location to modify bit in. - * bit Bit position to modify, 0-31. - * val Value to set bit to, 0 or 1. + * + * Input Parmeters: + * addr Peripheral address location to modify bit in. + * bit Bit position to modify, 0-31. + * val Value to set bit to, 0 or 1. * ******************************************************************************/ + inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val) { - uint32_t regval; + uint32_t regval; regval = EFM32_BITBAND_PER_BASE + ((addr-EFM32_PER_MEM_BASE)*32) + (bit*4); *((volatile uint32_t *)regval) = (uint32_t)val; } - /****************************************************************************** * Name: bitband_get_peripheral + * + * Description: * Perform bit-band operation on peripheral memory location. * - * Description * This function reads a single bit from the peripheral bit-band alias region. * Bit-banding provides atomic read-modify-write cycle for single bit * modification. Please refer to the reference manual for further details @@ -113,14 +114,16 @@ inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val) * * Note * This function is only atomic on cores which fully support bitbanding. - * - * Parameters - * addr Peripheral address location to read. - * bit Bit position to modify, 0-31. * - * Return bit value read, 0 or 1. + * Input Parmeters: + * addr Peripheral address location to read. + * bit Bit position to modify, 0-31. + * + * Returned Value: + * Return bit value read, 0 or 1. * ******************************************************************************/ + inline uint32_t bitband_get_peripheral(uint32_t addr, uint32_t bit) { uint32_t regval; @@ -129,25 +132,26 @@ inline uint32_t bitband_get_peripheral(uint32_t addr, uint32_t bit) return *((volatile uint32_t *)regval); } - /****************************************************************************** * Name: bitband_set_sram + * + * Description: * Perform bit-band write operation on SRAM memory location. * - * Description * Bit-banding provides atomic read-modify-write cycle for single bit * modification. Please refer to the reference manual for further details * about bit-banding. * * Note * This function is only atomic on cores which fully support bitbanding. - * - * Parameters - * addr SRAM address location to modify bit in. - * bit Bit position to modify, 0-31. - * val Value to set bit to, 0 or 1. + * + * Input Parmeters: + * addr SRAM address location to modify bit in. + * bit Bit position to modify, 0-31. + * val Value to set bit to, 0 or 1. * ******************************************************************************/ + inline void bitband_set_sram(uint32_t addr, uint32_t bit, uint32_t val) { uint32_t regval; @@ -156,12 +160,12 @@ inline void bitband_set_sram(uint32_t addr, uint32_t bit, uint32_t val) *((volatile uint32_t *)regval) = (uint32_t)val; } - /****************************************************************************** * Name: bitband_get_sram + * + * Description:: * Perform bit-band operation on SRAM memory location. * - * Description * This function reads a single bit from the RAM bit-band alias region. * Bit-banding provides atomic read-modify-write cycle for single bit * modification. Please refer to the reference manual for further details @@ -169,14 +173,16 @@ inline void bitband_set_sram(uint32_t addr, uint32_t bit, uint32_t val) * * Note * This function is only atomic on cores which fully support bitbanding. - * - * Parameters - * addr Peripheral address location to read. - * bit Bit position to modify, 0-31. * - * Return bit value read, 0 or 1. + * Input Parmeters: + * addr Peripheral address location to read. + * bit Bit position to modify, 0-31. + * + * Returned Value: + * Return bit value read, 0 or 1. * ******************************************************************************/ + inline uint32_t bitband_get_sram(uint32_t addr, uint32_t bit) { uint32_t regval; @@ -184,6 +190,4 @@ inline uint32_t bitband_get_sram(uint32_t addr, uint32_t bit) return *((volatile uint32_t *)regval); } -#endif - - +#endif diff --git a/arch/arm/src/efm32/efm32_flash.c b/arch/arm/src/efm32/efm32_flash.c index f38105d67e0..adf34fe1801 100644 --- a/arch/arm/src/efm32/efm32_flash.c +++ b/arch/arm/src/efm32/efm32_flash.c @@ -1,7 +1,7 @@ /***************************************************************************** * arch/arm/src/efm32/efm32_flash.c * - * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it @@ -87,7 +87,7 @@ /* Only for the EFM32 family for now */ -#if ( defined(CONFIG_ARCH_CHIP_EFM32) && defined(CONFIG_EFM32_FLASHPROG) ) +#if (defined(CONFIG_ARCH_CHIP_EFM32) && defined(CONFIG_EFM32_FLASHPROG)) /************************************************************************************ * Pre-processor Definitions @@ -113,16 +113,15 @@ # define EFM32_USERDATA_PAGESIZE (EFM32_USERDATA_SIZE/EFM32_USERDATA_NPAGES) #endif -/* - * brief: +/* brief: * The timeout used while waiting for the flash to become ready after * a write. This number indicates the number of iterations to perform before * issuing a timeout. * note: * This timeout is set very large (in the order of 100x longer than * necessary). This is to avoid any corner cases. - * */ + #define MSC_PROGRAM_TIMEOUT 10000000ul /************************************************************************************ @@ -141,7 +140,7 @@ void efm32_flash_unlock(void) bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,0); -#if defined( _MSC_TIMEBASE_MASK ) +#if defined(_MSC_TIMEBASE_MASK) regval = getreg32(EFM32_MSC_TIMEBASE); regval &= ~(_MSC_TIMEBASE_BASE_MASK | _MSC_TIMEBASE_PERIOD_MASK); @@ -179,17 +178,17 @@ void efm32_flash_unlock(void) regval |= (cycles << _MSC_TIMEBASE_BASE_SHIFT); } - putreg32(regval,EFM32_MSC_TIMEBASE); #endif } - /******************************************************************************* * Name: msc_load_verify_address - * Perform address phase of FLASH write cycle. + * * Description: + * Perform address phase of FLASH write cycle. + * * This function performs the address phase of a Flash write operation by * writing the given flash address to the ADDRB register and issuing the * LADDRIM command to load the address. @@ -207,8 +206,8 @@ void efm32_flash_unlock(void) * -EBUSY - Busy timeout. * -EINVAL - Operation tried to access a non-flash area. * -EACCES - Operation tried to access a locked area of the flash. - ******************************************************************************* - */ + *******************************************************************************/ + int __ramfunc__ msc_load_verify_address(uint32_t* address) { uint32_t status; @@ -237,7 +236,7 @@ int __ramfunc__ msc_load_verify_address(uint32_t* address) status = getreg32(EFM32_MSC_STATUS); if (status & (MSC_STATUS_INVADDR | MSC_STATUS_LOCKED)) { - + /* Check for invalid address */ if (status & MSC_STATUS_INVADDR) @@ -248,25 +247,31 @@ int __ramfunc__ msc_load_verify_address(uint32_t* address) if (status & MSC_STATUS_LOCKED) return -EACCES; } + return OK; } /******************************************************************************* * Name:msc_load_data - * Perform data phase of FLASH write cycle. + * * Description: + * Perform data phase of FLASH write cycle. + * * This function performs the data phase of a Flash write operation by loading * the given number of 32-bit words to the WDATA register. + * * note: * This function MUST be executed from RAM. Failure to execute this portion * of the code in RAM will result in a hardfault. For IAR, Rowley and * Codesourcery this will be achieved automatically. For Keil uVision 4 you * must define a section called "ram_code" and place this manually in your * project's scatter file. - * paramelters: + * + * Input Parameters: * data : Pointer to the first data word to load. * num_words : Number of data words (32-bit) to load. - * return: + * + * Returned Value: * Returns the status of the data load operation, #msc_Return_TypeDef * OK - Operation completed successfully. * -ETIMEDOUT - Operation timed out waiting for flash operation @@ -281,20 +286,18 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, int words_per_data_phase; int ret = 0; -#if defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK ) +#if defined(_MSC_WRITECTRL_LPWRITE_MASK) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) /* If LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word) */ if (!(getreg32(EFM32_MSC_WRITECTRL) & MSC_WRITECTRL_LPWRITE)) { - /* If the number of words to be written are odd, we need to align by writing - * a single word first, before setting the WDOUBLE bit. + * a single word first, before setting the WDOUBLE bit. */ if (num_words & 0x1) { - /* Wait for the msc to be ready for the next word. */ timeout = MSC_PROGRAM_TIMEOUT; @@ -320,9 +323,9 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, putreg32(*data++,EFM32_MSC_WDATA); putreg32(MSC_WRITECMD_WRITEONCE,EFM32_MSC_WRITECMD); - /* Wait for the operation to finish. It may be required to change the - * WDOUBLE config after the initial write. It should not be changed - * while BUSY. + /* Wait for the operation to finish. It may be required to change the + * WDOUBLE config after the initial write. It should not be changed + * while BUSY. */ timeout = MSC_PROGRAM_TIMEOUT; @@ -345,7 +348,7 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, } /* Now we can set the double word option in order to write two words per - * data phase. + * data phase. */ bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WDOUBLE_SHIFT,1); @@ -359,12 +362,11 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, /* Write the rest as double word write if wordsPerDataPhase == 2 */ - if ( num_words > 0 ) + if (num_words > 0) { - /* Write strategy: msc_write_int_safe */ - if ( write_strategy_safe ) + if (write_strategy_safe) { /* Requires a system core clock at 1MHz or higher */ @@ -381,9 +383,11 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, while (!(getreg32(EFM32_MSC_STATUS) & MSC_STATUS_WDATAREADY)) { } + putreg32(*data++,EFM32_MSC_WDATA); word_index++; } + putreg32(MSC_WRITECMD_WRITEONCE,EFM32_MSC_WRITECMD); /* Wait for the transaction to finish. */ @@ -402,7 +406,8 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, ret = -ETIMEDOUT; break; } -#if defined( CONFIG_EFM32_EFM32G ) + +#if defined(CONFIG_EFM32_EFM32G) putreg32(getreg32(EFM32_MSC_ADDRB)+4,EFM32_MSC_ADDRB); putreg32(MSC_WRITECMD_LADDRIM,EFM32_MSC_WRITECMD); #endif @@ -413,7 +418,7 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, else { -#if defined( CONFIG_EFM32_EFM32G ) +#if defined(CONFIG_EFM32_EFM32G) /* Gecko does not have auto-increment of ADDR. */ @@ -435,14 +440,14 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, { uint32_t regval; - /* If the write to MSC->WDATA below missed the 30us timeout - * and the following MSC_WRITECMD_WRITETRIG command arrived - * while MSC_STATUS_BUSY is 1, then the MSC_WRITECMD_WRITETRIG - * could be ignored by the MSC. In this case, - * MSC_STATUS_WORDTIMEOUT is set to 1 and MSC_STATUS_BUSY is - * 0. A new trigger is therefore needed here to complete write - * of data in MSC->WDATA. If WDATAREADY became high since - * entry into this loop, exit and continue to the next WDATA + /* If the write to MSC->WDATA below missed the 30us timeout + * and the following MSC_WRITECMD_WRITETRIG command arrived + * while MSC_STATUS_BUSY is 1, then the MSC_WRITECMD_WRITETRIG + * could be ignored by the MSC. In this case, + * MSC_STATUS_WORDTIMEOUT is set to 1 and MSC_STATUS_BUSY is + * 0. A new trigger is therefore needed here to complete write + * of data in MSC->WDATA. If WDATAREADY became high since + * entry into this loop, exit and continue to the next WDATA * write. */ @@ -450,18 +455,19 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, regval &= MSC_STATUS_WORDTIMEOUT; regval &= MSC_STATUS_BUSY; regval &= MSC_STATUS_WDATAREADY; - if ( regval == MSC_STATUS_WORDTIMEOUT ) + if (regval == MSC_STATUS_WORDTIMEOUT) { putreg32(MSC_WRITECMD_WRITETRIG,EFM32_MSC_WRITECMD); } } putreg32(*data,EFM32_MSC_WDATA); - if (( words_per_data_phase == 1) || \ + if ((words_per_data_phase == 1) || \ ((words_per_data_phase == 2) && (word_index & 0x1))) { putreg32(MSC_WRITECMD_WRITETRIG,EFM32_MSC_WRITECMD); } + data++; word_index++; } @@ -482,7 +488,7 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, ret = -ETIMEDOUT; } #endif - } + } } #ifdef _MSC_WRITECTRL_WDOUBLE_MASK @@ -493,14 +499,10 @@ int __ramfunc__ msc_load_write_data(uint32_t* data, uint32_t num_words, #endif return ret; - } - - void efm32_flash_lock(void) { - /* Disable writing to the flash */ bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,0); @@ -508,19 +510,18 @@ void efm32_flash_lock(void) /* Unlock the EFM32_MSC */ putreg32(0,EFM32_MSC_LOCK); - } #ifndef EFM32_FLASH_SIZE #define EFM32_FLASH_SIZE efm32_get_flash_size() uint32_t efm32_get_flash_size(void) { - uint32_t regval; - regval = getreg32(EFM32_DEVINFO_MEMINFO_SIZE); - regval = (regval & _DEVINFO_MEMINFO_SIZE_FLASH_MASK) \ - >> _DEVINFO_MEMINFO_SIZE_FLASH_SHIFT; + uint32_t regval; + regval = getreg32(EFM32_DEVINFO_MEMINFO_SIZE); + regval = (regval & _DEVINFO_MEMINFO_SIZE_FLASH_MASK) \ + >> _DEVINFO_MEMINFO_SIZE_FLASH_SHIFT; - return regval*1024; + return regval*1024; } #endif @@ -528,14 +529,16 @@ uint32_t efm32_get_flash_size(void) #define EFM32_FLASH_PAGESIZE efm32_get_flash_page_size() uint32_t efm32_get_flash_page_size(void) { - uint32_t regval; - regval = getreg32(EFM32_DEVINFO_MEMINFO_PAGE_SIZE); - regval = (regval & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) \ - >> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT; - if ( regval == 0xff ) - return 512; + uint32_t regval; + regval = getreg32(EFM32_DEVINFO_MEMINFO_PAGE_SIZE); + regval = (regval & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) \ + >> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT; + if (regval == 0xff) + { + return 512; + } - return 1<<(regval+10); + return 1 << (regval+10); } #endif @@ -543,7 +546,7 @@ uint32_t efm32_get_flash_page_size(void) #define EFM32_FLASH_NPAGES efm32_get_flash_page_nbr() uint32_t efm32_get_flash_page_nbr(void) { - return (EFM32_FLASH_SIZE/EFM32_FLASH_PAGESIZE); + return (EFM32_FLASH_SIZE/EFM32_FLASH_PAGESIZE); } #endif @@ -554,37 +557,40 @@ uint32_t efm32_get_flash_page_nbr(void) size_t up_progmem_pagesize(size_t page) { if (page < EFM32_FLASH_NPAGES) - return EFM32_FLASH_PAGESIZE; + { + return EFM32_FLASH_PAGESIZE; + } page -= EFM32_FLASH_NPAGES; if (page < EFM32_USERDATA_NPAGES) - return EFM32_USERDATA_PAGESIZE; + { + return EFM32_USERDATA_PAGESIZE; + } return 0; } ssize_t up_progmem_getpage(size_t addr) { -#if ( EFM32_FLASH_BASE != 0 ) - if ( (addr >= (EFM32_FLASH_BASE) ) && \ - (addr < (EFM32_FLASH_BASE+EFM32_FLASH_SIZE) ) - ) +#if (EFM32_FLASH_BASE != 0) + if ((addr >= (EFM32_FLASH_BASE)) && \ + (addr < (EFM32_FLASH_BASE+EFM32_FLASH_SIZE))) { addr -= EFM32_FLASH_BASE; return addr / EFM32_FLASH_PAGESIZE; } + #else - if ( addr < EFM32_FLASH_SIZE ) + if (addr < EFM32_FLASH_SIZE) { return addr / EFM32_FLASH_PAGESIZE; } #endif - if ( (addr >= (EFM32_USERDATA_BASE) ) && \ - (addr < (EFM32_USERDATA_BASE+EFM32_USERDATA_SIZE) ) - ) + if ((addr >= (EFM32_USERDATA_BASE)) && \ + (addr < (EFM32_USERDATA_BASE+EFM32_USERDATA_SIZE))) { addr -= EFM32_USERDATA_BASE; @@ -611,7 +617,6 @@ size_t up_progmem_getaddress(size_t page) return SIZE_MAX; } - size_t up_progmem_npages(void) { return EFM32_FLASH_NPAGES+EFM32_USERDATA_NPAGES; @@ -658,15 +663,15 @@ ssize_t __ramfunc__ up_progmem_erasepage(size_t page) /* Check for write protected page */ - if ( ( ret == 0 ) && (regval & MSC_STATUS_LOCKED) ) + if ((ret == 0) && (regval & MSC_STATUS_LOCKED)) { ret = -EPERM; } /* Send erase page command */ - if ( ret == 0 ) - { + if (ret == 0) + { putreg32(MSC_WRITECMD_ERASEPAGE,EFM32_MSC_WRITECMD); /* Wait for the erase to complete */ @@ -687,24 +692,26 @@ ssize_t __ramfunc__ up_progmem_erasepage(size_t page) bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WREN_SHIFT,0); - if ( ret == 0 ) - { + if (ret == 0) + { /* Verify */ if (up_progmem_ispageerased(page) != 0) { - ret = -EIO; + ret = -EIO; } } irqrestore(irqs); - if ( ret != 0 ) + if (ret != 0) + { return ret; + } - /* success */ + /* Success */ - return up_progmem_pagesize(page); + return up_progmem_pagesize(page); } ssize_t up_progmem_ispageerased(size_t page) @@ -736,11 +743,11 @@ ssize_t up_progmem_ispageerased(size_t page) ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) { int ret = 0; - int word_count; - int num_words; - int page_words; - uint32_t* p_data; - uint32_t* address = (uint32_t*) addr; + int word_count; + int num_words; + int page_words; + uint32_t* p_data; + uint32_t* address = (uint32_t*) addr; uint32_t num_bytes = size; /* EFM32 requires word access */ @@ -765,34 +772,34 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) /* Convert bytes to words */ - num_words = num_bytes >> 2; + num_words = num_bytes >> 2; /* The following loop splits the data into chunks corresponding to flash pages. * The address is loaded only once per page, because the hardware automatically - * increments the address internally for each data load inside a page. + * increments the address internally for each data load inside a page. */ - for (word_count = 0, p_data = (uint32_t*) buf; word_count < num_words; ) + for (word_count = 0, p_data = (uint32_t*) buf; word_count < num_words;) { int page_bytes; ssize_t page_idx; irqstate_t irqs; /* Compute the number of words to write to the current page. */ - + page_idx = up_progmem_getpage((size_t)address+(word_count<<2)); - if ( page_idx < 0 ) - { + if (page_idx < 0) + { ret = -EINVAL; break; - } + } page_bytes = up_progmem_pagesize(page_idx); - if ( page_bytes < 0 ) - { + if (page_bytes < 0) + { ret = -EINVAL; break; - } + } page_words = (page_bytes - (((uint32_t) (address + word_count)) & \ (page_bytes-1))) / sizeof(uint32_t); @@ -805,20 +812,21 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) irqs = irqsave(); /* First we load address. The address is auto-incremented within a page. - Therefore the address phase is only needed once for each page. */ + * Therefore the address phase is only needed once for each page. + */ ret = msc_load_verify_address(address + word_count); /* Now write the data in the current page. */ if (ret == 0) - { - ret = msc_load_write_data( p_data, page_words, true ); + { + ret = msc_load_write_data(p_data, page_words, true); } irqrestore(irqs); - if (ret != 0 ) + if (ret != 0) { break; } @@ -835,15 +843,16 @@ ssize_t __ramfunc__ up_progmem_write(size_t addr, const void *buf, size_t size) /* Turn off double word write cycle support. */ - bitband_set_peripheral(EFM32_MSC_WRITECTRL,_MSC_WRITECTRL_WDOUBLE_SHIFT,0); + bitband_set_peripheral(EFM32_MSC_WRITECTRL, _MSC_WRITECTRL_WDOUBLE_SHIFT, 0); #endif - if (ret < 0 ) - return ret; + if (ret < 0) + { + return ret; + } return word_count; } #endif /* defined(CONFIG_ARCH_CHIP_EFM32) */ - diff --git a/arch/arm/src/efm32/efm32_gpioirq.c b/arch/arm/src/efm32/efm32_gpioirq.c index 1043e3dae5d..0c21c912cbe 100644 --- a/arch/arm/src/efm32/efm32_gpioirq.c +++ b/arch/arm/src/efm32/efm32_gpioirq.c @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/efm32/efm32_gpioirq.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -276,7 +276,7 @@ void efm32_gpioirqenable(int irq) { /* Enable the interrupt associated with the pin */ -#ifndef CONFIG_EFM32_BITBAND +#ifndef CONFIG_EFM32_BITBAND irqstate_t flags; uint32_t regval; uint32_t bit; @@ -302,15 +302,15 @@ void efm32_gpioirqenable(int irq) void efm32_gpioirqdisable(int irq) { - if (irq >= EFM32_IRQ_EXTI0 && irq <= EFM32_IRQ_EXTI15) { /* Enable the interrupt associated with the pin */ -#ifndef CONFIG_EFM32_BITBAND +#ifndef CONFIG_EFM32_BITBAND irqstate_t flags; uint32_t regval; uint32_t bit; + bit = ((uint32_t)1 << (irq - EFM32_IRQ_EXTI0)); flags = irqsave(); regval = getreg32(EFM32_GPIO_IEN); @@ -333,12 +333,11 @@ void efm32_gpioirqdisable(int irq) void efm32_gpioirqclear(int irq) { - if (irq >= EFM32_IRQ_EXTI0 && irq <= EFM32_IRQ_EXTI15) { /* Enable the interrupt associated with the pin */ -#ifndef CONFIG_EFM32_BITBAND +#ifndef CONFIG_EFM32_BITBAND irqstate_t flags; uint32_t regval; uint32_t bit; diff --git a/arch/arm/src/efm32/efm32_i2c.c b/arch/arm/src/efm32/efm32_i2c.c index 7f72dec014a..415e11a7fbd 100644 --- a/arch/arm/src/efm32/efm32_i2c.c +++ b/arch/arm/src/efm32/efm32_i2c.c @@ -212,7 +212,7 @@ struct efm32_trace_s uint32_t i2c_reg_state; /* I2C register I2Cx_STATES */ uint32_t i2c_reg_if; /* I2C register I2Cx_IF */ uint32_t count; /* Interrupt count when status change */ - int dcnt; /* Interrupt count when status change */ + int dcnt; /* Interrupt count when status change */ uint32_t time; /* First of event or first status */ }; @@ -273,7 +273,7 @@ struct efm32_i2c_priv_s struct efm32_i2c_inst_s { const struct i2c_ops_s *ops; /* Standard I2C operations */ - struct efm32_i2c_priv_s *priv; /* Common driver private data structure + struct efm32_i2c_priv_s *priv; /* Common driver private data structure */ uint32_t frequency; /* Frequency used in this instantiation */ @@ -626,7 +626,7 @@ static inline int efm32_i2c_sem_waitdone(FAR struct efm32_i2c_priv_s *priv) if (ret != OK && errno != EINTR) { - /* Break out of the loop on irrecoverable errors. This would include + /* Break out of the loop on irrecoverable errors. This would include * timeouts and mystery errors reported by sem_timedwait. NOTE that * we try again if we are awakened by a signal (EINTR). */ @@ -834,8 +834,8 @@ static void efm32_i2c_tracedump(FAR struct efm32_i2c_priv_s *priv) syslog(LOG_DEBUG, "%2d. I2Cx_STATE: %08x I2Cx_PENDING: %08x dcnt %3d COUNT: %3d " "STATE: %s(%2d) TIME: %d\n", - i + 1, trace->i2c_reg_state, trace->i2c_reg_if, trace->dcnt, - trace->count, efm32_i2c_state_str(trace->i2c_state), + i + 1, trace->i2c_reg_state, trace->i2c_reg_if, trace->dcnt, + trace->count, efm32_i2c_state_str(trace->i2c_state), trace->i2c_state, trace->time - priv->start_time); } } @@ -921,7 +921,7 @@ static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv) if (priv->i2c_reg_if & I2C_IF_ARBLOST) { /* If arbitration fault, it indicates either a slave device not - * responding as expected, or other master which is not supported + * responding as expected, or other master which is not supported * by this SW. */ priv->result = I2CRESULT_ARBLOST; @@ -936,7 +936,7 @@ static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv) } /* If error situation occurred, it is difficult to know exact cause - * and how to resolve. It will be up to a wrapper to determine how to + * and how to resolve. It will be up to a wrapper to determine how to * handle a fault/recovery if possible. */ @@ -1194,7 +1194,7 @@ static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv) /********************************************************* * Wait for ACK/NACK from slave after sending data to it */ - + case I2CSTATE_DATAWFACKNACK: if (priv->i2c_reg_if & I2C_IF_NACK) { @@ -1248,14 +1248,13 @@ static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv) if (priv->dcnt == 1) { - /* If there is more than one byte to receive and this is - * the next to last byte we need to transmit the NACK - * now, before receiving the last byte. + /* If there is more than one byte to receive and this is + * the next to last byte we need to transmit the NACK + * now, before receiving the last byte. */ efm32_i2c_putreg(priv,EFM32_I2C_CMD_OFFSET,I2C_CMD_NACK); } - } } goto done; @@ -1603,16 +1602,13 @@ static int efm32_i2c_process(FAR struct i2c_dev_s *dev, /* Abort */ efm32_i2c_putreg(priv, EFM32_I2C_CMD_OFFSET, I2C_CMD_ABORT); - } else { - /* Check for error status conditions */ switch(priv->result) { - /* Arbitration lost during transfer. */ case I2CRESULT_ARBLOST: @@ -1638,7 +1634,7 @@ static int efm32_i2c_process(FAR struct i2c_dev_s *dev, break; /* Bus error during transfer (misplaced START/STOP). - * I2C Bus is for some reason busy + * I2C Bus is for some reason busy */ case I2CRESULT_BUSERR: @@ -1652,7 +1648,7 @@ static int efm32_i2c_process(FAR struct i2c_dev_s *dev, efm32_i2c_tracedump(priv); /* Ensure that any ISR happening after we finish can't overwrite any user - * data + * data */ priv->result = I2CRESULT_NONE; @@ -1769,7 +1765,7 @@ static int efm32_i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_dev_s *up_i2cinitialize(int port) { - struct efm32_i2c_priv_s *priv = NULL; /* Private data of device with multiple + struct efm32_i2c_priv_s *priv = NULL; /* Private data of device with multiple * instances */ struct efm32_i2c_inst_s *inst = NULL; /* Device, single instance */ irqstate_t irqs; diff --git a/arch/arm/src/efm32/efm32_rmu.c b/arch/arm/src/efm32/efm32_rmu.c index 43d84b1f2a0..3910e24aee9 100644 --- a/arch/arm/src/efm32/efm32_rmu.c +++ b/arch/arm/src/efm32/efm32_rmu.c @@ -80,83 +80,83 @@ typedef struct static efm32_reset_cause_list_t efm32_reset_cause_list[] = { { - 0x0001, //0bXXXX XXXX XXXX XXX1 - 0x0001, //0bXXXX XXXX XXXX XXX1 + 0x0001, /* 0bXXXX XXXX XXXX XXX1 */ + 0x0001, /* 0bXXXX XXXX XXXX XXX1 */ "A Power-on Reset has been performed. X bits are don't care." }, { - 0x0002, //0bXXXX XXXX 0XXX XX10 - 0x0003, //0bXXXX XXXX 1XXX XX11 + 0x0002, /* 0bXXXX XXXX 0XXX XX10 */ + 0x0003, /* 0bXXXX XXXX 1XXX XX11 */ "A Brown-out has been detected on the unregulated power." }, { - 0x0004, //0bXXXX XXXX XXX0 0100 - 0x001F, //0bXXXX XXXX XXX1 1111 + 0x0004, /* 0bXXXX XXXX XXX0 0100 */ + 0x001F, /* 0bXXXX XXXX XXX1 1111 */ "A Brown-out has been detected on the regulated power." }, { - 0x0008, //0bXXXX XXXX XXXX 1X00 - 0x000B, //0bXXXX XXXX XXXX 1X11 + 0x0008, /* 0bXXXX XXXX XXXX 1X00 */ + 0x000B, /* 0bXXXX XXXX XXXX 1X11 */ "An external reset has been applied." }, { - 0x0010, //0bXXXX XXXX XXX1 XX00 - 0x0013, //0bXXXX XXXX XXX1 XX11 + 0x0010, /* 0bXXXX XXXX XXX1 XX00 */ + 0x0013, /* 0bXXXX XXXX XXX1 XX11 */ "A watchdog reset has occurred." }, { - 0x0020, //0bXXXX X000 0010 0000 - 0x07FF, //0bXXXX X111 1111 1111 + 0x0020, /* 0bXXXX X000 0010 0000 */ + 0x07FF, /* 0bXXXX X111 1111 1111 */ "A lockup reset has occurred." }, { - 0x0040, //0bXXXX X000 01X0 0000 - 0x07DF, //0bXXXX X111 11X1 1111 + 0x0040, /* 0bXXXX X000 01X0 0000 */ + 0x07DF, /* 0bXXXX X111 11X1 1111 */ "A system request reset has occurred." }, { - 0x0080, //0bXXXX X000 1XX0 0XX0 - 0x0799, //0bXXXX X111 1XX1 1XX1 + 0x0080, /* 0bXXXX X000 1XX0 0XX0 */ + 0x0799, /* 0bXXXX X111 1XX1 1XX1 */ "The system has woken up from EM4." }, { - 0x0180, //0bXXXX X001 1XX0 0XX0 - 0x0799, //0bXXXX X111 1XX1 1XX1 + 0x0180, /* 0bXXXX X001 1XX0 0XX0 */ + 0x0799, /* 0bXXXX X111 1XX1 1XX1 */ "The system has woken up from EM4 on an EM4 wakeup reset request from pin." }, { - 0x0200, //0bXXXX X01X XXX0 0000 - 0x061F, //0bXXXX X11X XXX1 1111 + 0x0200, /* 0bXXXX X01X XXX0 0000 */ + 0x061F, /* 0bXXXX X11X XXX1 1111 */ "A Brown-out has been detected on Analog Power Domain 0 (AVDD0)." }, { - 0x0400, //0bXXXX X10X XXX0 0000 - 0x061F, //0bXXXX X11X XXX1 1111 + 0x0400, /* 0bXXXX X10X XXX0 0000 */ + 0x061F, /* 0bXXXX X11X XXX1 1111 */ "A Brown-out has been detected on Analog Power Domain 1 (AVDD1)." }, { - 0x0800, //0bXXXX 1XXX XXXX 0XX0 - 0x0809, //0bXXXX 1XXX XXXX 1XX1 + 0x0800, /* 0bXXXX 1XXX XXXX 0XX0 */ + 0x0809, /* 0bXXXX 1XXX XXXX 1XX1 */ "A Brown-out has been detected by the Backup BOD on VDD_DREG." }, { - 0x1000, //0bXXX1 XXXX XXXX 0XX0 - 0x1009, //0bXXX1 XXXX XXXX 1XX1 + 0x1000, /* 0bXXX1 XXXX XXXX 0XX0 */ + 0x1009, /* 0bXXX1 XXXX XXXX 1XX1 */ "A Brown-out has been detected by the Backup BOD on BU_VIN." }, { - 0x2000, //0bXX1X XXXX XXXX 0XX0 - 0x2009, //0bXX1X XXXX XXXX 1XX1 + 0x2000, /* 0bXX1X XXXX XXXX 0XX0 */ + 0x2009, /* 0bXX1X XXXX XXXX 1XX1 */ "A Brown-out has been detected by the Backup BOD on unregulated power" }, { - 0x4000, //0bX1XX XXXX XXXX 0XX0 - 0x4009, //0bX1XX XXXX XXXX 1XX1 + 0x4000, /* 0bX1XX XXXX XXXX 0XX0 */ + 0x4009, /* 0bX1XX XXXX XXXX 1XX1 */ "A Brown-out has been detected by the Backup BOD on regulated power." }, { - 0x8000, //0b1XXX XXXX XXXX XXX0 - 0x8001, //0b1XXX XXXX XXXX XXX1 + 0x8000, /* 0b1XXX XXXX XXXX XXX0 */ + 0x8001, /* 0b1XXX XXXX XXXX XXX1 */ "The system has been in Backup mode." } };