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toolchain/ghs: Adapt .macro syntax for GHS compiler
The GHS compiler uses different .macro syntax. Without this change, the GHS compiler reports error like: [asarm] (error #2014) nuttx/arch/arm/src/armv8-r/arm_vectors.S 155: expected a register vstmdb \ out ! , { s0 - s31 } ---------^ And: [asarm] (error #2179) nuttx/arch/arm/src/armv8-r/arm_vectors.S 141: unexpected token type (comma) encountered; expected type (char) .macro savefpu , out , tmp -----------------^ Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com> Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com>
This commit is contained in:
xiezhanpeng3
Xiang Xiao
@@ -53,10 +53,16 @@
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****************************************************************************/
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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#ifdef __ghs__
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.macro setirqstack tmp1 tmp2
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ldr sp, .Lirqstacktop /* SP = IRQ stack top */
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.endm
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#else
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.macro setirqstack, tmp1, tmp2
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ldr sp, .Lirqstacktop /* SP = IRQ stack top */
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.endm
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#endif
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#endif
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/****************************************************************************
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* Name: setfiqstack
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@@ -68,10 +74,16 @@
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****************************************************************************/
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#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
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#ifdef __ghs__
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.macro setfiqstack tmp1 tmp2
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ldr sp, .Lfiqstacktop /* SP = FIQ stack top */
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.endm
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#else
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.macro setfiqstack, tmp1, tmp2
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ldr sp, .Lfiqstacktop /* SP = FIQ stack top */
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.endm
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#endif
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#endif
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/****************************************************************************
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* Name: savefpu
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@@ -82,6 +94,26 @@
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****************************************************************************/
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#ifdef CONFIG_ARCH_FPU
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#ifdef __ghs__
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.macro savefpu out tmp
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/* Store all floating point registers. Registers are stored in numeric order,
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* s0, s1, ... in increasing address order.
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*/
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/* Store the floating point control and status register. */
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vmrs tmp, fpscr /* Fetch the FPSCR */
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str tmp, [out, #-4]! /* Save the floating point control and status register */
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#ifdef CONFIG_ARM_DPFPU32
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vstmdb.64 out!, {d16-d31} /* Save the full FP context */
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vstmdb.64 out!, {d0-d15}
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#else
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vstmdb out!, {s0-s31} /* Save the full FP context */
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#endif
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.endm
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#else /* __ghs__ */
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.macro savefpu, out, tmp
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/* Store all floating point registers. Registers are stored in numeric order,
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* s0, s1, ... in increasing address order.
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@@ -100,6 +132,7 @@
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#endif
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.endm
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#endif /* __ghs__ */
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#endif
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/****************************************************************************
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@@ -111,6 +144,27 @@
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****************************************************************************/
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#ifdef CONFIG_ARCH_FPU
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#ifdef __ghs__
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.macro restorefpu in tmp
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/* Load all floating point registers. Registers are loaded in numeric order,
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* s0, s1, ... in increasing address order.
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*/
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#ifdef CONFIG_ARM_DPFPU32
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vldmia.64 in!, {d0-d15} /* Restore the full FP context */
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vldmia.64 in!, {d16-d31}
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#else
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vldmia in!, {s0-s31} /* Restore the full FP context */
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#endif
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/* Load the floating point control and status register. At the end of the
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* vstmia, \in will point to the FPSCR storage location.
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*/
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ldr tmp, [in], #4 /* Fetch the floating point control and status register */
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vmsr fpscr, tmp /* Restore the FPSCR */
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.endm
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#else
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.macro restorefpu, in, tmp
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/* Load all floating point registers. Registers are loaded in numeric order,
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* s0, s1, ... in increasing address order.
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@@ -130,6 +184,7 @@
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ldr \tmp, [\in], #4 /* Fetch the floating point control and status register */
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vmsr fpscr, \tmp /* Restore the FPSCR */
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.endm
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#endif /* __ghs__ */
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#endif
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/****************************************************************************
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@@ -224,12 +224,21 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_enable_dcache tmp
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mrc p15, 0, tmp, c1, c0, 0 /* Read SCTLR */
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orr tmp, tmp, #(0x1 << 2) /* Enable D cache */
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mcr p15, 0, tmp, c1, c0, 0 /* Update the SCTLR */
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isb
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.endm
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#else
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.macro cp15_enable_dcache, tmp
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mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
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orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */
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mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_disable_dcache
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@@ -245,12 +254,21 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_disable_dcache tmp
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mrc p15, 0, tmp, c1, c0, 0 /* Read SCTLR */
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bic tmp, tmp, #(0x1 << 2) /* Disable D cache */
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mcr p15, 0, tmp, c1, c0, 0 /* Update the SCTLR */
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isb
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.endm
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#else
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.macro cp15_disable_dcache, tmp
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mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
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bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */
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mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_enable_icache
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@@ -266,12 +284,21 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_enable_icache tmp
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mrc p15, 0, tmp, c1, c0, 0 /* Read SCTLR */
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orr tmp, tmp, #(0x1 << 12) /* Enable I cache */
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mcr p15, 0, tmp, c1, c0, 0 /* Update the SCTLR */
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isb
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.endm
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#else
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.macro cp15_enable_icache, tmp
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mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
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orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */
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mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_disable_icache
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@@ -287,12 +314,21 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_disable_icache tmp
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mrc p15, 0, tmp, c1, c0, 0 /* Read SCTLR */
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bic tmp, tmp, #(0x1 << 12) /* Disable I cache */
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mcr p15, 0, tmp, c1, c0, 0 /* Update the SCTLR */
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isb
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.endm
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#else
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.macro cp15_disable_icache, tmp
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mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
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bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */
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mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_invalidate_icache_inner_sharable
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@@ -308,11 +344,19 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_invalidate_icache_inner_sharable tmp
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mov tmp, #0
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mrc p15, 0, tmp, c7, c1, 0 /* ICIALLUIS */
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isb
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.endm
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#else
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.macro cp15_invalidate_icache_inner_sharable, tmp
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mov \tmp, #0
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mrc p15, 0, \tmp, c7, c1, 0 /* ICIALLUIS */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_invalidate_btb_inner_sharable
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@@ -328,11 +372,19 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_invalidate_btb_inner_sharable tmp
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mov tmp, #0
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mrc p15, 0, tmp, c7, c1, 6 /* BPIALLIS */
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isb
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.endm
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#else
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.macro cp15_invalidate_btb_inner_sharable, tmp
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mov \tmp, #0
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mrc p15, 0, \tmp, c7, c1, 6 /* BPIALLIS */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_invalidate_icache_all
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@@ -349,11 +401,19 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_invalidate_icache_all tmp
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mov tmp, #0
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mrc p15, 0, tmp, c7, c5, 0 /* ICIALLU */
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isb
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.endm
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#else
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.macro cp15_invalidate_icache_all, tmp
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mov \tmp, #0
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mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_invalidate_icache_bymva
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@@ -369,10 +429,17 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_invalidate_icache_bymva va
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mrc p15, 0, va, c7, c5, 1 /* ICIMVAU */
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isb
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.endm
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#else
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.macro cp15_invalidate_icache_bymva, va
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mrc p15, 0, \va, c7, c5, 1 /* ICIMVAU */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_flush_btb
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@@ -388,11 +455,19 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_flush_btb tmp
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mov tmp, #0
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mrc p15, 0, tmp, c7, c5, 6 /* BPIALL */
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isb
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.endm
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#else
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.macro cp15_flush_btb, tmp
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mov \tmp, #0
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mrc p15, 0, \tmp, c7, c5, 6 /* BPIALL */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_flush_btb_bymva
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@@ -408,10 +483,17 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_flush_btb_bymva va
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mrc p15, 0, va, c7, c5, 7 /* BPIMVA */
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isb
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.endm
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#else
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.macro cp15_flush_btb_bymva, va
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mrc p15, 0, \va, c7, c5, 7 /* BPIMVA */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_invalidate_dcacheline_bymva
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@@ -427,10 +509,17 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_invalidate_dcacheline_bymva va
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mrc p15, 0, va, c7, c6, 1 /* DCIMVAC */
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isb
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.endm
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#else
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.macro cp15_invalidate_dcacheline_bymva, va
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mrc p15, 0, \va, c7, c6, 1 /* DCIMVAC */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_invalidate_dcacheline_bysetway
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@@ -446,10 +535,17 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_invalidate_dcacheline_bysetway setway
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mrc p15, 0, setway, c7, c6, 2 /* DCISW */
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isb
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.endm
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#else
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.macro cp15_invalidate_dcacheline_bysetway, setway
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mrc p15, 0, \setway, c7, c6, 2 /* DCISW */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_clean_dcache_bymva
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@@ -465,10 +561,17 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_clean_dcache_bymva va
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mrc p15, 0, va, c7, c10, 1 /* DCCMVAC */
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isb
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.endm
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#else
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.macro cp15_clean_dcache_bymva, va
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mrc p15, 0, \va, c7, c10, 1 /* DCCMVAC */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_clean_dcache_bysetway
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@@ -484,10 +587,17 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_clean_dcache_bysetway setway
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mrc p15, 0, setway, c7, c10, 2 /* DCCSW */
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isb
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.endm
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#else
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.macro cp15_clean_dcache_bysetway, setway
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mrc p15, 0, \setway, c7, c10, 2 /* DCCSW */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_clean_ucache_bymva
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@@ -503,10 +613,17 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_clean_ucache_bymva va
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mrc p15, 0, va, c7, c11, 1 /* DCCMVAU */
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isb
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.endm
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#else
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.macro cp15_clean_ucache_bymva, va
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mrc p15, 0, \va, c7, c11, 1 /* DCCMVAU */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_cleaninvalidate_dcacheline_bymva
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@@ -522,10 +639,17 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_cleaninvalidate_dcacheline_bymva va
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mrc p15, 0, va, c7, c14, 1 /* DCCIMVAC */
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isb
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.endm
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#else
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.macro cp15_cleaninvalidate_dcacheline_bymva, va
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mrc p15, 0, \va, c7, c14, 1 /* DCCIMVAC */
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isb
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.endm
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#endif
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/****************************************************************************
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* Name: cp15_cleaninvalidate_dcacheline
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@@ -541,10 +665,17 @@
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*
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****************************************************************************/
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#ifdef __ghs__
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.macro cp15_cleaninvalidate_dcacheline setway
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mrc p15, 0, setway, c7, c14, 2 /* DCCISW */
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isb
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.endm
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#else
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.macro cp15_cleaninvalidate_dcacheline, setway
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mrc p15, 0, \setway, c7, c14, 2 /* DCCISW */
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isb
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.endm
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#endif
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#endif /* __ASSEMBLY__ */
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@@ -496,6 +496,29 @@
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/* Get the device ID */
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#ifdef __ghs__
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.macro cp15_rdid id
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mrc p15, 0, id, c0, c0, 0
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.endm
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/* Read/write the system control register (SCTLR) */
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.macro cp15_rdsctlr sctlr
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mrc p15, 0, sctlr, c1, c0, 0
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.endm
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.macro cp15_wrsctlr sctlr
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mcr p15, 0, sctlr, c1, c0, 0
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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.endm
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#else
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.macro cp15_rdid, id
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mrc p15, 0, \id, c0, c0, 0
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.endm
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@@ -517,6 +540,7 @@
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nop
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nop
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.endm
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#endif
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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