Remove the tail spaces from all files except Documentation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

CONTRIBUTING.md

@@ -14,10 +14,10 @@ it is very important you follow these guidelines:
         <first line (up to ~80 characters)>
 
         <more paragraphs here>
-        
+
     * The first line should have a prefix to give context
       (unless context is really clear), such as:
-      
+
           <keyword>: <message>
           i.e sched: Fixed compiler warning
 

LICENSE

@@ -3018,7 +3018,7 @@ arch/arm/src/lc823450/lc823450_sddrv_dep.c
 arch/arm/src/lc823450/lc823450_sddrv_if.h
 arch/arm/src/lc823450/lc823450_sddrv_type.h
 arch/arm/src/lc823450/lc823450_symbols.ld
-============================================ 
+============================================
 
   Copyright (C) 2014-2015 ON Semiconductor. All rights reserved.
   Copyright 2014,2015,2016,2017 Sony Video & Sound Products Inc.
@@ -7199,7 +7199,7 @@ include/sys/queue.h
    $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $
    Copyright (c) 1991, 1993
    The Regents of the University of California.  All rights reserved.
- 
+
  Redistribution and use in source and binary forms, with or without
  modification, are permitted provided that the following conditions
  are met:

ReleaseNotes

@@ -30421,7 +30421,7 @@ USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT
 ```
 
 Change:
- 
+
 ```
 $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC)
 ```
@@ -31802,7 +31802,7 @@ NuttX-11.0.0 Release Notes
  * [#5966](https://github.com/apache/nuttx/pull/5966) arch:tcbinfo: update tcbinfo as xcpcontext update
  * [#5865](https://github.com/apache/nuttx/pull/5865) arch: Add -fsanitize=kernel-address to ARCHCPUFLAGS if CONFIG_MM_KASAN=y
  * [#5864](https://github.com/apache/nuttx/pull/5864) arch/Toolchain.defs: add wildcard for EXTRA_LIBS
- * [#5920](https://github.com/apache/nuttx/pull/5920) ARCH_ADDRENV: Add guard against mis-configuration 
+ * [#5920](https://github.com/apache/nuttx/pull/5920) ARCH_ADDRENV: Add guard against mis-configuration
  * [#6105](https://github.com/apache/nuttx/pull/6105) arch/clang: add support for Clang LTO
  * [#6089](https://github.com/apache/nuttx/pull/6089) arch: Move group_addrenv to common place
  * [#6183](https://github.com/apache/nuttx/pull/6183) arch: Remvoe the error message when toolchain can't find
@@ -31815,7 +31815,7 @@ NuttX-11.0.0 Release Notes
  * [#6254](https://github.com/apache/nuttx/pull/6254) arch: Remove board/libboard$(LIBEXT) from the rerequest of export_startup
  * [#6276](https://github.com/apache/nuttx/pull/6276) arch: Move "-nostartfiles -nodefaultlibs" from Make.defs to Toolchian.defs
  * [#6351](https://github.com/apache/nuttx/pull/6351) arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h
- * [#6286](https://github.com/apache/nuttx/pull/6286) arch: inline up_interrupt_context() 
+ * [#6286](https://github.com/apache/nuttx/pull/6286) arch: inline up_interrupt_context()
  * [#6284](https://github.com/apache/nuttx/pull/6284) arch/addrenv: Add missing FAR qualifier to addrenv_mprot
  * [#6277](https://github.com/apache/nuttx/pull/6277) arch/i2c: Change xxx_i2c_tousecs to xxx_i2c_toticks
  * [#6416](https://github.com/apache/nuttx/pull/6416) Fix CONFIG_ALLSYMS for arm, risc-v and xtensa after #5496
@@ -31870,7 +31870,7 @@ NuttX-11.0.0 Release Notes
  * [#5983](https://github.com/apache/nuttx/pull/5983) arch/risc-v: Remove the unnecessary inclusion of board header files
  * [#5754](https://github.com/apache/nuttx/pull/5754) arch/risc-v: Correct stack coloration in riscv_cpu_boot
  * [#5758](https://github.com/apache/nuttx/pull/5758) RISC-V: Prepare CONFIG_BUILD_KERNEL part 1
- * [#5760](https://github.com/apache/nuttx/pull/5760) ESP32-S3: Fix UART IRQ setup hardcoded to CPU 0 
+ * [#5760](https://github.com/apache/nuttx/pull/5760) ESP32-S3: Fix UART IRQ setup hardcoded to CPU 0
  * [#5766](https://github.com/apache/nuttx/pull/5766) arch/risc-v: Rework riscv_get_newintctx
  * [#5773](https://github.com/apache/nuttx/pull/5773) risc-v/esp32c3: Remove deprecated option for disabling atomics support
  * [#5775](https://github.com/apache/nuttx/pull/5775) arch/risc-v: Merge riscv_getnewintctx into common
@@ -31934,7 +31934,7 @@ NuttX-11.0.0 Release Notes
  * [#6069](https://github.com/apache/nuttx/pull/6069) RISC-V: Add support for CONFIG_BUILD_KERNEL
  * [#6005](https://github.com/apache/nuttx/pull/6005) ESP32C3 TWAI (CAN) controller support.
  * [#5740](https://github.com/apache/nuttx/pull/5740) Add ethernet support for risc-v/MPFS
- * [#5749](https://github.com/apache/nuttx/pull/5749) risc-v/mpfs: usb: fix ep0 stall/resume and rx reads 
+ * [#5749](https://github.com/apache/nuttx/pull/5749) risc-v/mpfs: usb: fix ep0 stall/resume and rx reads
  * [#5783](https://github.com/apache/nuttx/pull/5783) risc-v/mpfs: usb: fix ep0 read done
  * [#5881](https://github.com/apache/nuttx/pull/5881) MPFS: Fix issue with external interrupt detection
  * [#5875](https://github.com/apache/nuttx/pull/5875) MPFS: Fix error in flat build linker script
@@ -31961,7 +31961,7 @@ NuttX-11.0.0 Release Notes
  * [#6530](https://github.com/apache/nuttx/pull/6530) mpfs: Fix IHC memory locations to native width type
  * [#6490](https://github.com/apache/nuttx/pull/6490) mpfs: Allow mapping of RAM/ROM regions from different memory areas
  * [#6602](https://github.com/apache/nuttx/pull/6602) risc-v/mpfs: usb: fix illegal reads
- * [#6535](https://github.com/apache/nuttx/pull/6535) risc-v/mpfs: ihc: don't start rptun automatically 
+ * [#6535](https://github.com/apache/nuttx/pull/6535) risc-v/mpfs: ihc: don't start rptun automatically
  * [#6361](https://github.com/apache/nuttx/pull/6361) arch/risc-v: re-add missing riscv_udelay source
  * [#6343](https://github.com/apache/nuttx/pull/6343) Some cleanup for risc-v
  * [#6342](https://github.com/apache/nuttx/pull/6342) arch/risc-v: Unify common source include
@@ -32081,7 +32081,7 @@ NuttX-11.0.0 Release Notes
  * [#6379](https://github.com/apache/nuttx/pull/6379) arm/tlsr82: gpio driver bug fix and optimize
  * [#6334](https://github.com/apache/nuttx/pull/6334) arm/tlsr82: ble performance optimize and problems solve
  * [#6238](https://github.com/apache/nuttx/pull/6238) tlsr82/tc32: optimize the irq process
- * [#6332](https://github.com/apache/nuttx/pull/6332) arch: imx6: add support kernel build and smp 
+ * [#6332](https://github.com/apache/nuttx/pull/6332) arch: imx6: add support kernel build and smp
  * [#6429](https://github.com/apache/nuttx/pull/6429) arch: imx6: Enable imx_idle.c to reduce CPU load
  * [#6234](https://github.com/apache/nuttx/pull/6234) arm/tc32/Make.defs: filter-out arm_udelay.c
  * [#6736](https://github.com/apache/nuttx/pull/6736) arm/allocateheap: fix multiple definition of 'up_allocate_heap'
@@ -32100,9 +32100,9 @@ NuttX-11.0.0 Release Notes
  * [#6775](https://github.com/apache/nuttx/pull/6775) arch/stm32/stm32_foc.c: fix some ADC and PWM ifdefs
  * [#6769](https://github.com/apache/nuttx/pull/6769) arch/stm32f0l0g0: add SPI3 support (STM32G0B0 chips)
  * [#6218](https://github.com/apache/nuttx/pull/6218) STM32F746G-Disco, Audiosupport, Bugfix
- * [#6715](https://github.com/apache/nuttx/pull/6715) stm32wb: adding BLE support 
+ * [#6715](https://github.com/apache/nuttx/pull/6715) stm32wb: adding BLE support
  * [#6729](https://github.com/apache/nuttx/pull/6729) stm32f7: add showprogress in __start
- * [#6078](https://github.com/apache/nuttx/pull/6078) Stm32f746 audio 
+ * [#6078](https://github.com/apache/nuttx/pull/6078) Stm32f746 audio
  * [#6413](https://github.com/apache/nuttx/pull/6413) stm32wl5: add gpio exti support
  * [#6426](https://github.com/apache/nuttx/pull/6426) stm32wl5: add flash progmem driver support
  * [#6788](https://github.com/apache/nuttx/pull/6788) LPC17xx_40xx PWM multichannel support
@@ -32289,7 +32289,7 @@ NuttX-11.0.0 Release Notes
  * [#6138](https://github.com/apache/nuttx/pull/6138) boards/boardctl: correct boarctl return value
  * [#6141](https://github.com/apache/nuttx/pull/6141) boards/risc-v: Remove "MAXOPTIMIZATION = -Os" from Make.defs
  * [#6143](https://github.com/apache/nuttx/pull/6143) boards: Move -fno-common from Make.defs to Toolchain.defs
- * [#6144](https://github.com/apache/nuttx/pull/6144) boards: Move -g from Make.defs to Toolchain.defs 
+ * [#6144](https://github.com/apache/nuttx/pull/6144) boards: Move -g from Make.defs to Toolchain.defs
  * [#6146](https://github.com/apache/nuttx/pull/6146) boards: Move "-fno-exceptions -fcheck-new" from Make.defs to Toolchain.defs
  * [#6155](https://github.com/apache/nuttx/pull/6155) boards: Move -fno-strict-aliasing from Make.defs to Toolchain.defs
  * [#6195](https://github.com/apache/nuttx/pull/6195) boards: rv-virt: Add support ELF to nsh and nsh64 defconfigs

arch/arm/include/gd32f4/gd32f4xx_irq.h

@@ -219,7 +219,7 @@
 #elif defined(CONFIG_GD32F4_GD32F405)
 #  define GD32_IRQ_NEXTINT      (82)
 #  define NR_IRQS                (GD32_IRQ_EXINT + GD32_IRQ_NEXTINT)
-#else 
+#else
 #  error "Unknown GD32F4xx chip!"
 #endif
 

arch/arm/src/gd32f4/gd32f4xx_allocateheap.c

@@ -144,9 +144,9 @@
 /* Two memory regions.  Case 1 or 2 */
 
 #    if !defined(CONFIG_GD32F4_TCMEXCLUDE) && defined(CONFIG_GD32F4_EXTERNAL_RAM)
-#      error "Can not support both TCM SRAM and EXMC SRAM, when CONFIG_MM_REGIONS is 2 " 
+#      error "Can not support both TCM SRAM and EXMC SRAM, when CONFIG_MM_REGIONS is 2 "
 #      undef CONFIG_GD32F4_TCMEXCLUDE
-#      define CONFIG_GD32F4_TCMEXCLUDE 1  
+#      define CONFIG_GD32F4_TCMEXCLUDE 1
 #    endif
 
 /* Case 1, TCMSRAM is used. In this case, DMA should not be used  */

arch/arm/src/gd32f4/gd32f4xx_irq.c

@@ -129,7 +129,7 @@ static void gd32_dumpnvic(const char *msg, int irq)
           getreg32(NVIC_IRQ84_87_PRIORITY),
           getreg32(NVIC_IRQ88_91_PRIORITY),
           getreg32(NVIC_IRQ92_95_PRIORITY));
-#endif      
+#endif
 
   leave_critical_section(flags);
 }

arch/arm/src/gd32f4/gd32f4xx_rcu.c

@@ -83,7 +83,7 @@
  * Pravite Functions
  ****************************************************************************/
 
-#ifdef GD32_BOARD_SYSCLK_IRC16MEN 
+#ifdef GD32_BOARD_SYSCLK_IRC16MEN
 /****************************************************************************
  * Name: gd32_system_clock_irc16m
  *
@@ -512,7 +512,7 @@ static void gd32_system_clock_pll_hxtal(void)
 
 static void gd32_system_clock_config(void)
 {
-#ifdef GD32_BOARD_SYSCLK_IRC16MEN  
+#ifdef GD32_BOARD_SYSCLK_IRC16MEN
 
   /* Select IRC16M as SYSCLK based on board.h setting. */
 

arch/arm/src/gd32f4/gd32f4xx_serial.c

@@ -80,7 +80,7 @@
 /* USART DMA priority */
 #if defined(CONFIG_GD32F4_USART_PRIQ)
 #  define USART_DMA_PRIO  CONFIG_GD32F4_USART_PRIQ
-#else 
+#else
 #  define USART_DMA_PRIO  DMA_PRIO_MEDIUM_SELECT
 #endif
 #endif

arch/arm/src/gd32f4/gd32f4xx_spi.c

@@ -99,7 +99,7 @@
 
 #if defined(CONFIG_GD32F4_SPI_PRIQ)
 #  define SPI_DMA_PRIO  CONFIG_GD32F4_SPI_PRIQ
-#else 
+#else
 #  define SPI_DMA_PRIO  DMA_PRIO_MEDIUM_SELECT
 #endif
 

arch/arm/src/gd32f4/hardware/gd32f450_memorymap.h

@@ -84,7 +84,7 @@
 
 /* Peripheral Base Addresses ************************************************/
 
-#define GD32_APB1_BUS_BASE   0x40000000     /* APB1 base address */                                          
+#define GD32_APB1_BUS_BASE   0x40000000     /* APB1 base address */
 #define GD32_APB2_BUS_BASE   0x40010000     /* APB2 base address */
 #define GD32_AHB1_BUS_BASE   0x40020000     /* AHB1 base address */
 #define GD32_AHB2_BUS_BASE   0x50000000     /* AHB2 base address */

arch/arm/src/gd32f4/hardware/gd32f450_pinmap.h

@@ -530,7 +530,7 @@
 #define GPIO_SPI3_SCK_4        (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_G|GPIO_CFG_PIN_11)
 
 #define GPIO_SPI4_MISO_1       (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_A|GPIO_CFG_PIN_12)
-#define GPIO_SPI4_MISO_2       (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_E|GPIO_CFG_PIN_13)    
+#define GPIO_SPI4_MISO_2       (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_E|GPIO_CFG_PIN_13)
 #define GPIO_SPI4_MISO_3       (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_5|GPIO_CFG_PORT_F|GPIO_CFG_PIN_8)
 #define GPIO_SPI4_MISO_4       (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_5|GPIO_CFG_PORT_H|GPIO_CFG_PIN_7)
 #define GPIO_SPI4_MOSI_1       (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_A|GPIO_CFG_PIN_10)

arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h

@@ -196,7 +196,7 @@
 #define DMA_CHXCTL_TM(n)               ((n) << DMA_CHXCTL_TM_SHIFT)
 #  define DMA_PERIPH_TO_MEMORY         DMA_CHXCTL_TM(0)                /* 00: read from peripheral and write to memory */
 #  define DMA_MEMORY_TO_PERIPH         DMA_CHXCTL_TM(1)                /* 01: read from peripheral and write to memory */
-#  define DMA_MEMORY_TO_MEMORY         DMA_CHXCTL_TM(2)                /* 02: read from peripheral and write to memory */   
+#  define DMA_MEMORY_TO_MEMORY         DMA_CHXCTL_TM(2)                /* 02: read from peripheral and write to memory */
 
 #define DMA_CHXCTL_CMEN                (1 << 8)                        /* Bit 8: circulation mode */
 #define DMA_CHXCTL_PNAGA               (1 << 9)                        /* Bit 9: next address generation algorithm of peripheral */
@@ -229,7 +229,7 @@
 #define DMA_CHXCTL_MBS                 (1 << 19)                       /* Bit19: memory buffer select */
 
 #define DMA_CHXCTL_PBURST_SHIFT        (21)                            /* Bit 21-22: transfer burst type of peripheral */
-#define DMA_CHXCTL_PBURST_MASK         (3 << DMA_CHXCTL_PBURST_SHIFT) 
+#define DMA_CHXCTL_PBURST_MASK         (3 << DMA_CHXCTL_PBURST_SHIFT)
 #define DMA_CHXCTL_PBURST(n)           ((n) << DMA_CHXCTL_PBURST_SHIFT)
 #  define DMA_PERIPH_BURST_SINGLE      DMA_CHXCTL_PBURST(0)            /* single burst */
 #  define DMA_PERIPH_BURST_4_BEAT      DMA_CHXCTL_PBURST(1)            /* 4-beat burst */

arch/arm/src/gd32f4/hardware/gd32f4xx_exti.h

@@ -125,7 +125,7 @@
 #define EXTI_17                          GD32_EXTI_BIT(17)     /* EXTI line 17 */
 #define EXTI_18                          GD32_EXTI_BIT(18)     /* EXTI line 18 */
 #define EXTI_19                          GD32_EXTI_BIT(19)     /* EXTI line 19 */
-#define EXTI_20                          GD32_EXTI_BIT(20)     /* EXTI line 20 */    
+#define EXTI_20                          GD32_EXTI_BIT(20)     /* EXTI line 20 */
 #define EXTI_21                          GD32_EXTI_BIT(21)     /* EXTI line 21 */
 #define EXTI_22                          GD32_EXTI_BIT(22)     /* EXTI line 22 */
 

arch/arm/src/gd32f4/hardware/gd32f4xx_fmc.h

@@ -153,7 +153,7 @@
 
 #define FMC_CTL_SN_SHIFT                 (3)                    /* Bits 3-7: select which sector number to be erased */
 #define FMC_CTL_SN_MASK                  (31 << FMC_CTL_SN_SHIFT)
-#define FMC_CTL_SN(n)                    ((n) << FMC_CTL_SN_SHIFT)     /* Sector n, n=0..11 */                 
+#define FMC_CTL_SN(n)                    ((n) << FMC_CTL_SN_SHIFT)     /* Sector n, n=0..11 */
 #define FMC_CTL_SN_0_11(n)               ((n) << FMC_CTL_SN_SHIFT)     /* Sector n, n=0..11 */
 #define FMC_CTL_SN_12_23(n)              ((n+4) << FMC_CTL_SN_SHIFT))  /* Sector n, n=12..23 */
 #define FMC_CTL_SN_24_27(n)              ((n-12) << FMC_CTL_SN_SHIFT)) /* Sector n, n=24..27 */

arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h

@@ -297,7 +297,7 @@
 #define RCU_AHB1RST_PGRST                (1 << 6)              /* Bit 6: GPIO port G reset */
 #define RCU_AHB1RST_PHRST                (1 << 7)              /* Bit 7: GPIO port H reset */
 #define RCU_AHB1RST_PIRST                (1 << 8)              /* Bit 8: GPIO port I reset */
-#define RCU_AHB1RST_CRCRST               (1 << 12)             /* Bit 12: CRC reset */         
+#define RCU_AHB1RST_CRCRST               (1 << 12)             /* Bit 12: CRC reset */
 #define RCU_AHB1RST_DMA0RST              (1 << 21)             /* Bit 21: DMA0 reset */
 #define RCU_AHB1RST_DMA1RST              (1 << 22)             /* Bit 22: DMA1 reset */
 #define RCU_AHB1RST_IPARST               (1 << 23)             /* Bit 23: IPA reset */
@@ -562,13 +562,13 @@
 
 /* PLL clock spread spectrum control register */
 
-#define RCU_PLLSSCTL_MODCNT_SHIFT        (0)                   /* Bit 0-12: These bits configure PLL spread spectrum modulation 
+#define RCU_PLLSSCTL_MODCNT_SHIFT        (0)                   /* Bit 0-12: These bits configure PLL spread spectrum modulation
                                                                 *            profile amplitude and frequency. The following criteria
                                                                 *            must be met: MODSTEP*MODCNT<=2^15-1 */
 #define RCU_PLLSSCTL_MODCNT_MASK         (0x1fff << RCU_PLLSSCTL_MODCNT_SHIFT)
 #  define RCU_PLLSSCTL_MODCNT(n)         ((n) << RCU_PLLSSCTL_MODCNT_SHIFT)
 
-#define RCU_PLLSSCTL_MODSTEP_SHIFT       (13)                  /* Bit 13-27: These bits configure PLL spread spectrum modulation 
+#define RCU_PLLSSCTL_MODSTEP_SHIFT       (13)                  /* Bit 13-27: These bits configure PLL spread spectrum modulation
                                                                 *             profile amplitude and frequency. The following criteria
                                                                 *             must be met: MODSTEP*MODCNT<=2^15-1 */
 #define RCU_PLLSSCTL_MODSTEP_MASK        (0x7fff << RCU_PLLSSCTL_MODSTEP_SHIFT)
@@ -603,7 +603,7 @@
 #  define RCU_PLLSAI_PLLSAIP_DIV_6       RCU_PLLSAI_PLLSAIP(6)
 #  define RCU_PLLSAI_PLLSAIP_DIV_8       RCU_PLLSAI_PLLSAIP(8)
 
-#define RCU_PLLSAI_PLLSAIR_SHIFT         (28)                  /* Bits 28-30: The PLLSAI R output frequency division factor 
+#define RCU_PLLSAI_PLLSAIR_SHIFT         (28)                  /* Bits 28-30: The PLLSAI R output frequency division factor
                                                                 *              from PLLSAI VCO clock */
 #define RCU_PLLSAI_PLLSAIR_MASK          (7 << RCU_PLLSAI_PLLSAIR_SHIFT)
 #  define RCU_PLLSAI_PLLSAIR(n)          ((n) << RCU_PLLSAI_PLLSAIR_SHIFT)           /* n=2..7 */

arch/arm/src/gd32f4/hardware/gd32f4xx_spi.h

@@ -98,7 +98,7 @@
 #define SPI_CTL0_CKPH              (1 << 0)            /* Bit 0: clock phase selection*/
 #define SPI_CTL0_CKPL              (1 << 1)            /* Bit 1: clock polarity selection */
 #define SPI_CTL0_MSTMOD            (1 << 2)            /* Bit 2: master mode enable */
-#define SPI_CTL0_PSC_SHIFT         (3)                 /* Bit 3-5: master clock prescaler selection */ 
+#define SPI_CTL0_PSC_SHIFT         (3)                 /* Bit 3-5: master clock prescaler selection */
 #define SPI_CTL0_PSC_MASK          (7 << SPI_CTL0_PSC_SHIFT)
 #define SPI_CTL0_PSC(n)            ((n) << SPI_CTL0_PSC_SHIFT)
 #  define SPI_CTL0_PSC_2           SPI_CTL0_PSC(0)     /* 000: SPI clock prescale factor is 2 */

arch/arm/src/gd32f4/hardware/gd32f4xx_uart.h

@@ -150,7 +150,7 @@
 #  define USART_CTL0_PM_ODD        USART_CTL0_PMEN(3)
 
 #define USART_WL_9BIT              USART_CTL0_WL
-#define USART_WL_8BIT              (0)       
+#define USART_WL_8BIT              (0)
 
 #define USART_CTL0_INT_SHIFT       (4)
 #define USART_CTL0_INT_MASK        (0x1f << USART_CTL0_INT_SHIFT)

arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c

@@ -386,7 +386,7 @@ static int pwm_timer(struct lpc17_40_pwmtimer_s *priv,
              putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
                       LPC17_40_PWM1_MR6); /* Set PWM cycle */
              break;
-#endif      
+#endif
 
          default:
            {

arch/arm/src/nrf52/Kconfig

@@ -667,7 +667,7 @@ menuconfig NRF52_SOFTDEVICE_CONTROLLER
 	depends on NRF52_LFCLK_XTAL
 	---help---
 		This enables use of Nordic SoftDevice controller
-		(SDC). It is a library version of a subset of 
+		(SDC). It is a library version of a subset of
 		full SoftDevice, which only includes the BLE
 		controller implementation.
 

arch/arm/src/phy62xx/Make.defs

@@ -30,9 +30,9 @@ CHIP_CSRCS += phy62xx_ble.c
 endif
 
 ifeq ($(CONFIG_TIMER),y)
-CHIP_CSRCS += phyplus_tim.c 
+CHIP_CSRCS += phyplus_tim.c
 CHIP_CSRCS += phyplus_timer_lowerhalf.c
-CHIP_CSRCS += phyplus_timerisr.c 
+CHIP_CSRCS += phyplus_timerisr.c
 endif
 
 ifeq ($(CONFIG_DEV_GPIO),y)
@@ -53,15 +53,15 @@ INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)ble)
 CFLAGS += -ffunction-sections
 CFLAGS += -DCFG_CP
 CFLAGS += -DPHY_MCU_TYPE=MCU_BUMBEE_M0
-CFLAGS += -DHOST_CONFIG=4 
+CFLAGS += -DHOST_CONFIG=4
-CFLAGS += -DHCI_TL_NONE=1 
+CFLAGS += -DHCI_TL_NONE=1
-CFLAGS += -DMTU_SIZE=247 
+CFLAGS += -DMTU_SIZE=247
-CFLAGS += -DENABLE_LOG_ROMx=0 
+CFLAGS += -DENABLE_LOG_ROMx=0
-CFLAGS += -DPHY_MCU_TYPE=MCU_BUMBEE_M0 
+CFLAGS += -DPHY_MCU_TYPE=MCU_BUMBEE_M0
-CFLAGS += -DCFG_SLEEP_MODE=PWR_MODE_NO_SLEEP 
+CFLAGS += -DCFG_SLEEP_MODE=PWR_MODE_NO_SLEEP
-CFLAGS += -DDEBUG_INFO=1 
+CFLAGS += -DDEBUG_INFO=1
-CFLAGS += -DUSE_SYS_TICK 
+CFLAGS += -DUSE_SYS_TICK
-CFLAGS += -DHUGE_MODE=0 
+CFLAGS += -DHUGE_MODE=0
 CFLAGS += -DMAX_NUM_LL_CONN=1
 CFLAGS += -DUSE_ROMSYM_ALIAS
 CFLAGS += -Wno-unused-but-set-variable

arch/arm/src/phy62xx/phyplus_gpio.c

@@ -38,7 +38,7 @@
 #include "phyplus_gpio.h"
 #include "errno.h"
 
-#if defined(CONFIG_DEV_GPIO) 
+#if defined(CONFIG_DEV_GPIO)
 
 /****************************************************************************
  * phy6222  internal used functions..
@@ -171,7 +171,7 @@ static int phyplus_gpin_read(struct gpio_dev_s *dev, bool *value)
   gpioinfo("Reading...\n");
 
   *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]);
-#endif 
+#endif
   struct phyplus_gpio_dev_s *phyplus_gpin =
                         (struct phyplus_gpio_dev_s *)dev;
 
@@ -195,7 +195,7 @@ static int phyplus_gpout_read(struct gpio_dev_s *dev, bool *value)
   gpioinfo("Reading...\n");
 
   *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]);
-#endif	
+#endif
 
   struct phyplus_gpio_dev_s *phyplus_gpout =
                 (struct phyplus_gpio_dev_s *)dev;

arch/arm/src/phy62xx/phyplus_stub.c

@@ -520,7 +520,7 @@ static int phyplus_parse_params_and_action(char *buff)
           return -1;
         }
     }
-#if 0  
+#if 0
   else if (0 == strncmp(buff, "reg_timer", 9))
     {
       p += 10;

arch/arm/src/phy62xx/phyplus_timer_lowerhalf.c

@@ -114,7 +114,7 @@ static const struct timer_ops_s g_timer_ops =
   .getstatus   = phyplus_getstatus,
 #else
   .getstatus   = NULL,
-#endif  
+#endif
   .settimeout  = phyplus_settimeout,
   .setcallback = phyplus_setcallback,
 #if 1

arch/arm/src/rp2040/rp2040_ws2812.pio

@@ -13,10 +13,10 @@
 ;
 ;  clock    +-----+-----+-----+-----+-----+-----+-----+-----+-----+
 |           |    T1     |          T2           |       T3        |
-;  
+;
 ;           +-----------+
 ;  zero-bit |           |                                         |
-;                       +-----------------------------------------+         
+;                       +-----------------------------------------+
 ;
 ;           +-----------------------------------+
 ;  one-bit  |                                   |                 |

arch/arm/src/s32k1xx/Kconfig

@@ -630,15 +630,15 @@ endmenu # eDMA Global Configuration
 
 menu "LPUART Configuration"
 	depends on S32K1XX_LPUART
-	
+
 config S32K1XX_LPUART_INVERT
 	bool "Signal Invert Support"
 	default n
-endmenu	
+endmenu
 
 menu "LPSPI Configuration"
 	depends on S32K1XX_LPSPI
-	
+
 config S32K1XX_LPSPI_DWORD
 	bool "DWORD up to 64 bit transfer support"
 	default n
@@ -684,7 +684,7 @@ config S32K1XX_LPSPI_DMATHRESHOLD
 config S32K1XX_LPSPI_HWPCS
 	bool "Use native hardware peripheral chip selects instead of GPIO pins"
 	default n
-	
+
 endmenu # LPSPI Configuration
 
 menu "LPI2C Configuration"

arch/arm/src/s32k1xx/hardware/s32k1xx_flexio.h

@@ -329,7 +329,7 @@
 #define FLEXIO_TIMCTL_PINPOL              (1 << 7)  /* Bit 7: Timer Pin Polarity (PINPOL) */
 #  define FLEXIO_TIMCTL_PINPOL_HI         (0 << 7)  /*        Pin is active high */
 #  define FLEXIO_TIMCTL_PINPOL_LO         (1 << 7)  /*        Pin is active low */
-#define FLEXIO_TIMCTL_PINSEL_SHIFT        (8)       /* Bits 8-10: Timer Pin Select (PINSEL) */ 
+#define FLEXIO_TIMCTL_PINSEL_SHIFT        (8)       /* Bits 8-10: Timer Pin Select (PINSEL) */
 #define FLEXIO_TIMCTL_PINSEL_MASK         (0x07 << FLEXIO_TIMCTL_PINSEL_SHIFT)
 #  define FLEXIO_TIMCTL_PINSEL(n)         (((n) << FLEXIO_TIMCTL_PINSEL_SHIFT) & FLEXIO_TIMCTL_PINSEL_MASK)
                                                     /* Bits 11-15: Reserved */
@@ -363,7 +363,7 @@
 #  define FLEXIO_TIMCFG_TSTART_DIS        (0 << 1)  /*        Start bit disabled */
 #  define FLEXIO_TIMCFG_TSTART_ENA        (1 << 1)  /*        Start bit enabled */
                                                     /* Bits 2-3: Reserved */
-#define FLEXIO_TIMCFG_TSTOP_SHIFT         (4)       /* Bits 4-5: Timer Stop Bit (TSTOP) */ 
+#define FLEXIO_TIMCFG_TSTOP_SHIFT         (4)       /* Bits 4-5: Timer Stop Bit (TSTOP) */
 #define FLEXIO_TIMCFG_TSTOP_MASK          (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT)
 #  define FLEXIO_TIMCFG_TSTOP_DIS         (0x00 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit disabled */
 #  define FLEXIO_TIMCFG_TSTOP_TIMCMP      (0x01 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare */
@@ -371,7 +371,7 @@
 #  define FLEXIO_TIMCFG_TSTOP_BOTH        (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare and timer disable */
 
                                                     /* Bits 6-7: Reserved */
-#define FLEXIO_TIMCFG_TIMENA_SHIFT        (8)       /* Bits 8-10: Timer Enable (TIMENA) */ 
+#define FLEXIO_TIMCFG_TIMENA_SHIFT        (8)       /* Bits 8-10: Timer Enable (TIMENA) */
 #define FLEXIO_TIMCFG_TIMENA_MASK         (0x07 << FLEXIO_TIMCFG_TIMENA_SHIFT)
 #  define FLEXIO_TIMCFG_TIMENA_ALWAYS     (0x00 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer always enabled */
 #  define FLEXIO_TIMCFG_TIMENA_TIMENA     (0x01 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Timer N-1 enable */
@@ -404,7 +404,7 @@
 #  define FLEXIO_TIMCFG_TIMRST_TRGBOTH    (0x07 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer reset on Trigger rising or falling edge */
 
                                                     /* Bit 19: Reserved */
-#define FLEXIO_TIMCFG_TIMDEC_SHIFT             (20) /* Bits 20-21: Timer Decrement (TIMDEC) */ 
+#define FLEXIO_TIMCFG_TIMDEC_SHIFT             (20) /* Bits 20-21: Timer Decrement (TIMDEC) */
 #define FLEXIO_TIMCFG_TIMDEC_MASK              (0x03 << FLEXIO_TIMCFG_TIMDEC_SHIFT)
 #  define FLEXIO_TIMCFG_TIMDEC_CLKTIMOUT       (0x00 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on FlexIO clock, Shift clock equals Timer output */
 #  define FLEXIO_TIMCFG_TIMDEC_TRGINBOTHTIMOUT (0x01 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (both edges), Shift clock equals Timer output */
@@ -412,7 +412,7 @@
 #  define FLEXIO_TIMCFG_TIMDEC_TRGINBOTHTRGIN  (0x03 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (both edges), Shift clock equals Trigger input */
 
                                                     /* Bit 23: Reserved */
-#define FLEXIO_TIMCFG_TIMOUT_SHIFT        (24)      /* Bits 24-25: Timer Output (TIMOUT) */ 
+#define FLEXIO_TIMCFG_TIMOUT_SHIFT        (24)      /* Bits 24-25: Timer Output (TIMOUT) */
 #define FLEXIO_TIMCFG_TIMOUT_MASK         (0x03 << FLEXIO_TIMCFG_TIMOUT_SHIFT)
 #  define FLEXIO_TIMCFG_TIMOUT_ONE        (0x00 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic one when enabled and is not affected by timer reset */
 #  define FLEXIO_TIMCFG_TIMOUT_ZERO       (0x01 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic zero when enabled and is not affected by timer reset */

arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h

@@ -72,9 +72,9 @@
 /* SMC Power Mode Protection register */
 
 #define SMC_PMPROT_AVLP_SHIFT       (5)  /* Bit 5:  Allow Very-Low-Power Modes */
-#define SMC_PMPROT_AVLP             (1 << SMC_PMPROT_AVLP_SHIFT)  
+#define SMC_PMPROT_AVLP             (1 << SMC_PMPROT_AVLP_SHIFT)
 #define SMC_PMPROT_AHSRUN_SHIFT     (7)  /* Bit 7:  Allow High Speed Run mode */
-#define SMC_PMPROT_AHSRUN           (1 << SMC_PMPROT_AHSRUN_SHIFT)  
+#define SMC_PMPROT_AHSRUN           (1 << SMC_PMPROT_AHSRUN_SHIFT)
 
 /* SMC Power Mode Control register */
 

arch/arm/src/s32k3xx/Kconfig

@@ -376,7 +376,7 @@ config S32K3XX_QSPI
 	default n
 	select ARCH_USE_MPU
 	depends on S32K3XX_HAVE_QSPI
-	
+
 menu "FlexCAN"
 
 config S32K3XX_FLEXCAN0
@@ -591,7 +591,7 @@ endmenu # LPUART
 config S32K3XX_RTC
 	bool "RTC"
 	default n
-	
+
 config S32K3XX_FS26
 	bool "FS26 SBC Disable watchdog"
 	default n
@@ -1085,11 +1085,11 @@ endmenu # eDMA Global Configuration
 
 menu "LPSPI Configuration"
 	depends on S32K3XX_LPSPI
-	
+
 config S32K3XX_LPSPI_DWORD
 	bool "DWORD up to 64 bit transfer support"
 	default n
-	
+
 config S32K3XX_LPSPI_DMA
 	bool "SPI DMA"
 	depends on S32K3XX_EDMA
@@ -1131,7 +1131,6 @@ config S32K3XX_LPSPI4_DMA
 	depends on S32K3XX_LPSPI4 && S32K3XX_LPSPI_DMA
 	---help---
 		Use DMA to improve LPSPI4 transfer performance.
-		
 
 config S32K3XX_LPSPI5_DMA
 	bool "LPSPI5 DMA"
@@ -1149,13 +1148,13 @@ config S32K3XX_LPSPI_DMATHRESHOLD
 		When SPI DMA is enabled, small DMA transfers will still be performed
 		by polling logic.  But we need a threshold value to determine what
 		is small.
-	
+
 config S32K3XX_LPSPI0_PINCFG
 	int "LPSPI0 input & data pin config"
 	depends on S32K3XX_LPSPI0
 	default 0
 	---help---
-		Configures which pins are used for input and output data during serial transfers. 
+		Configures which pins are used for input and output data during serial transfers.
 		0 - SIN is used for input data and SOUT is used for output data
 		1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
 		2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
@@ -1166,7 +1165,7 @@ config S32K3XX_LPSPI1_PINCFG
 	depends on S32K3XX_LPSPI1
 	default 0
 	---help---
-		Configures which pins are used for input and output data during serial transfers. 
+		Configures which pins are used for input and output data during serial transfers.
 		0 - SIN is used for input data and SOUT is used for output data
 		1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
 		2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
@@ -1177,7 +1176,7 @@ config S32K3XX_LPSPI2_PINCFG
 	depends on S32K3XX_LPSPI2
 	default 0
 	---help---
-		Configures which pins are used for input and output data during serial transfers. 
+		Configures which pins are used for input and output data during serial transfers.
 		0 - SIN is used for input data and SOUT is used for output data
 		1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
 		2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
@@ -1188,7 +1187,7 @@ config S32K3XX_LPSPI3_PINCFG
 	depends on S32K3XX_LPSPI3
 	default 0
 	---help---
-		Configures which pins are used for input and output data during serial transfers. 
+		Configures which pins are used for input and output data during serial transfers.
 		0 - SIN is used for input data and SOUT is used for output data
 		1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
 		2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
@@ -1199,7 +1198,7 @@ config S32K3XX_LPSPI4_PINCFG
 	depends on S32K3XX_LPSPI4
 	default 0
 	---help---
-		Configures which pins are used for input and output data during serial transfers. 
+		Configures which pins are used for input and output data during serial transfers.
 		0 - SIN is used for input data and SOUT is used for output data
 		1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
 		2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
@@ -1210,12 +1209,12 @@ config S32K3XX_LPSPI5_PINCFG
 	depends on S32K3XX_LPSPI5
 	default 0
 	---help---
-		Configures which pins are used for input and output data during serial transfers. 
+		Configures which pins are used for input and output data during serial transfers.
 		0 - SIN is used for input data and SOUT is used for output data
 		1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
 		2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
 		3 - SOUT is used for input data and SIN is used for output data
-	
+
 endmenu # LPSPI Configuration
 
 menu "LPI2C Configuration"
@@ -1317,15 +1316,15 @@ endmenu # LPI2C Configuration
 
 menu "LPUART Configuration"
 	depends on S32K3XX_LPUART
-	
+
 config S32K3XX_LPUART_INVERT
 	bool "Signal Invert Support"
 	default n
-		
+
 config S32K3XX_LPUART_SINGLEWIRE
 	bool "Signal Wire Support"
 	default n
-	
+
 config S32K3XX_SERIAL_RXDMA_BUFFER_SIZE
 	int "RX DMA buffer size"
 	default 64

arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h

@@ -170,7 +170,7 @@
 #define S32K3XX_ADC_STAW2R_OFFSET         (0x038c) /* Self-Test Analog Watchdog S2 Register (STAW2R) */
 #define S32K3XX_ADC_STAW4R_OFFSET         (0x0394) /* Self-Test Analog Watchdog C0 Register (STAW4R) */
 #define S32K3XX_ADC_STAW5R_OFFSET         (0x0398) /* Self-Test Analog Watchdog C Register (STAW5R) */
-#define S32K3XX_ADC_AMSIO_OFFSET          (0x039c) /* Analog Miscellaneous In/Out Register (AMSIO) */ 
+#define S32K3XX_ADC_AMSIO_OFFSET          (0x039c) /* Analog Miscellaneous In/Out Register (AMSIO) */
 #define S32K3XX_ADC_CALBISTREG_OFFSET     (0x03a0) /* Control and Calibration Status Register (CALBISTREG) */
 #define S32K3XX_ADC_OFSGNUSR_OFFSET       (0x03a8) /* Offset and Gain User Register (OFSGNUSR) */
 #define S32K3XX_ADC_CAL2_OFFSET           (0x03b4) /* Calibration Value 2 (CAL2) */

arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h

@@ -548,12 +548,12 @@
 #define DCM_GPR_DCMRWD3_PRAM1_ECC_ERR_EN  (1 << 24) /* Bit 24: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from SRAM1 (PRAM1_ECC_ERR_EN) */
 #define DCM_GPR_DCMRWD3_PRAM0_ECC_ERR_EN  (1 << 25) /* Bit 25: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from SRAM0 (PRAM0_ECC_ERR_EN) */
 
-#define DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN (1 << 26) /* Bit 26: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache data memory (CM7_0_DCDATA_ECC_ERR_EN) */ 
+#define DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN (1 << 26) /* Bit 26: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache data memory (CM7_0_DCDATA_ECC_ERR_EN) */
-#define DCM_GPR_DCMRWD3_CM7_1_DCDATA_ECC_ERR_EN (1 << 27) /* Bit 27: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache data memory (CM7_1_DCDATA_ECC_ERR_EN) */ 
+#define DCM_GPR_DCMRWD3_CM7_1_DCDATA_ECC_ERR_EN (1 << 27) /* Bit 27: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache data memory (CM7_1_DCDATA_ECC_ERR_EN) */
-#define DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN  (1 << 28) /* Bit 28: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache tag memory (CM7_0_DCTAG_ECC_ERR_EN) */ 
+#define DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN  (1 << 28) /* Bit 28: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache tag memory (CM7_0_DCTAG_ECC_ERR_EN) */
-#define DCM_GPR_DCMRWD3_CM7_1_DCTAG_ECC_ERR_EN  (1 << 29) /* Bit 29: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache tag memory (CM7_1_DCTAG_ECC_ERR_EN) */ 
+#define DCM_GPR_DCMRWD3_CM7_1_DCTAG_ECC_ERR_EN  (1 << 29) /* Bit 29: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache tag memory (CM7_1_DCTAG_ECC_ERR_EN) */
-#define DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN (1 << 30) /* Bit 30: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 ICache data memory (CM7_0_DCDATA_ECC_ERR_EN) */ 
+#define DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN (1 << 30) /* Bit 30: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 ICache data memory (CM7_0_DCDATA_ECC_ERR_EN) */
-#define DCM_GPR_DCMRWD3_CM7_1_ICDATA_ECC_ERR_EN (1 << 31) /* Bit 31: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 ICache data memory (CM7_1_DCDATA_ECC_ERR_EN) */ 
+#define DCM_GPR_DCMRWD3_CM7_1_ICDATA_ECC_ERR_EN (1 << 31) /* Bit 31: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 ICache data memory (CM7_1_DCDATA_ECC_ERR_EN) */
 
 /* Read Write GPR On Destructive Reset Register 4 (DCMRWD4) */
 
@@ -809,7 +809,7 @@
 #  define DCM_GPR_DCMRWF5_BOOT_MODE_FAST   (1 << 0) /*        Fast Standby */
 
 #define DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT (1)      /* Bits 1-31: Cortex-M7_0 base address of vector table to be used after exiting (fast) standby mode (BOOT_ADDRESS) */
-#define DCM_GPR_DCMRWF5_BOOT_ADDRESS_MASK  (0x7fffffff << DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT) 
+#define DCM_GPR_DCMRWF5_BOOT_ADDRESS_MASK  (0x7fffffff << DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT)
 
 /* Read Only GPR On PMCPOR Reset Register 1 (DCMROPP1) */
 

arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h

@@ -312,7 +312,7 @@
                                                /* Bits 5-13: Reserved */
 #define EMIOS_C2_UCPRECLK            (1 << 14) /* Bit 14: Prescaler Clock Source (UCPRECLK) */
                                                /* Bit 15: Reserved */
-#define EMIOS_C2_UCEXTPRE_SHIFT      (16)      /* Bits 16-19: Extended Prescaler (UCEXTPRE) */ 
+#define EMIOS_C2_UCEXTPRE_SHIFT      (16)      /* Bits 16-19: Extended Prescaler (UCEXTPRE) */
 #define EMIOS_C2_UCEXTPRE_MASK       (0x0f << EMIOS_C2_UCEXTPRE_SHIFT)
 #define EMIOS_C2_UCEXTPRE(n)         (((n) << EMIOS_C2_UCEXTPRE_SHIFT) & EMIOS_C2_UCEXTPRE_MASK)
                                                /* Bits 20-31: Reserved */

arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h

@@ -548,7 +548,7 @@
 #define S32K3XX_CAN0_ERFIER                  (S32K3XX_CAN0_BASE + S32K3XX_CAN_ERFIER_OFFSET)
 #define S32K3XX_CAN0_ERFSR                   (S32K3XX_CAN0_BASE + S32K3XX_CAN_ERFSR_OFFSET)
 
-#define S32K3XX_CAN0_HR_TIME_STAMP(n)        (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))  
+#define S32K3XX_CAN0_HR_TIME_STAMP(n)        (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
 #  define S32K3XX_CAN0_HR_TIME_STAMP0        (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET)
 #  define S32K3XX_CAN0_HR_TIME_STAMP1        (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET)
 #  define S32K3XX_CAN0_HR_TIME_STAMP2        (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET)
@@ -916,7 +916,7 @@
 #define S32K3XX_CAN1_ERFIER                  (S32K3XX_CAN1_BASE + S32K3XX_CAN_ERFIER_OFFSET)
 #define S32K3XX_CAN1_ERFSR                   (S32K3XX_CAN1_BASE + S32K3XX_CAN_ERFSR_OFFSET)
 
-#define S32K3XX_CAN1_HR_TIME_STAMP(n)        (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))  
+#define S32K3XX_CAN1_HR_TIME_STAMP(n)        (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
 #  define S32K3XX_CAN1_HR_TIME_STAMP0        (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET)
 #  define S32K3XX_CAN1_HR_TIME_STAMP1        (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET)
 #  define S32K3XX_CAN1_HR_TIME_STAMP2        (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET)
@@ -1284,7 +1284,7 @@
 #define S32K3XX_CAN2_ERFIER                  (S32K3XX_CAN2_BASE + S32K3XX_CAN_ERFIER_OFFSET)
 #define S32K3XX_CAN2_ERFSR                   (S32K3XX_CAN2_BASE + S32K3XX_CAN_ERFSR_OFFSET)
 
-#define S32K3XX_CAN2_HR_TIME_STAMP(n)        (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))  
+#define S32K3XX_CAN2_HR_TIME_STAMP(n)        (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
 #  define S32K3XX_CAN2_HR_TIME_STAMP0        (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET)
 #  define S32K3XX_CAN2_HR_TIME_STAMP1        (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET)
 #  define S32K3XX_CAN2_HR_TIME_STAMP2        (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET)
@@ -1652,7 +1652,7 @@
 #define S32K3XX_CAN3_ERFIER                  (S32K3XX_CAN3_BASE + S32K3XX_CAN_ERFIER_OFFSET)
 #define S32K3XX_CAN3_ERFSR                   (S32K3XX_CAN3_BASE + S32K3XX_CAN_ERFSR_OFFSET)
 
-#define S32K3XX_CAN3_HR_TIME_STAMP(n)        (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))  
+#define S32K3XX_CAN3_HR_TIME_STAMP(n)        (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
 #  define S32K3XX_CAN3_HR_TIME_STAMP0        (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET)
 #  define S32K3XX_CAN3_HR_TIME_STAMP1        (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET)
 #  define S32K3XX_CAN3_HR_TIME_STAMP2        (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET)
@@ -2020,7 +2020,7 @@
 #define S32K3XX_CAN4_ERFIER                  (S32K3XX_CAN4_BASE + S32K3XX_CAN_ERFIER_OFFSET)
 #define S32K3XX_CAN4_ERFSR                   (S32K3XX_CAN4_BASE + S32K3XX_CAN_ERFSR_OFFSET)
 
-#define S32K3XX_CAN4_HR_TIME_STAMP(n)        (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))  
+#define S32K3XX_CAN4_HR_TIME_STAMP(n)        (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
 #  define S32K3XX_CAN4_HR_TIME_STAMP0        (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET)
 #  define S32K3XX_CAN4_HR_TIME_STAMP1        (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET)
 #  define S32K3XX_CAN4_HR_TIME_STAMP2        (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET)
@@ -2388,7 +2388,7 @@
 #define S32K3XX_CAN5_ERFIER                  (S32K3XX_CAN5_BASE + S32K3XX_CAN_ERFIER_OFFSET)
 #define S32K3XX_CAN5_ERFSR                   (S32K3XX_CAN5_BASE + S32K3XX_CAN_ERFSR_OFFSET)
 
-#define S32K3XX_CAN5_HR_TIME_STAMP(n)        (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))  
+#define S32K3XX_CAN5_HR_TIME_STAMP(n)        (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
 #  define S32K3XX_CAN5_HR_TIME_STAMP0        (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET)
 #  define S32K3XX_CAN5_HR_TIME_STAMP1        (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET)
 #  define S32K3XX_CAN5_HR_TIME_STAMP2        (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET)

arch/arm/src/s32k3xx/hardware/s32k3xx_flexio.h

@@ -637,7 +637,7 @@
 #define FLEXIO_TIMCTL_PINPOL              (1 << 7)  /* Bit 7: Timer Pin Polarity (PINPOL) */
 #  define FLEXIO_TIMCTL_PINPOL_HI         (0 << 7)  /*        Pin is active high */
 #  define FLEXIO_TIMCTL_PINPOL_LO         (1 << 7)  /*        Pin is active low */
-#define FLEXIO_TIMCTL_PINSEL_SHIFT        (8)       /* Bits 8-12: Timer Pin Select (PINSEL) */ 
+#define FLEXIO_TIMCTL_PINSEL_SHIFT        (8)       /* Bits 8-12: Timer Pin Select (PINSEL) */
 #define FLEXIO_TIMCTL_PINSEL_MASK         (0x1f << FLEXIO_TIMCTL_PINSEL_SHIFT)
 #  define FLEXIO_TIMCTL_PINSEL(n)         (((n) << FLEXIO_TIMCTL_PINSEL_SHIFT) & FLEXIO_TIMCTL_PINSEL_MASK)
                                                     /* Bits 13-15: Reserved */
@@ -671,7 +671,7 @@
 #  define FLEXIO_TIMCFG_TSTART_DIS        (0 << 1)  /*        Start bit disabled */
 #  define FLEXIO_TIMCFG_TSTART_ENA        (1 << 1)  /*        Start bit enabled */
                                                     /* Bits 2-3: Reserved */
-#define FLEXIO_TIMCFG_TSTOP_SHIFT         (4)       /* Bits 4-5: Timer Stop Bit (TSTOP) */ 
+#define FLEXIO_TIMCFG_TSTOP_SHIFT         (4)       /* Bits 4-5: Timer Stop Bit (TSTOP) */
 #define FLEXIO_TIMCFG_TSTOP_MASK          (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT)
 #  define FLEXIO_TIMCFG_TSTOP_DIS         (0x00 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit disabled */
 #  define FLEXIO_TIMCFG_TSTOP_TIMCMP      (0x01 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare */
@@ -679,7 +679,7 @@
 #  define FLEXIO_TIMCFG_TSTOP_BOTH        (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare and timer disable */
 
                                                     /* Bits 6-7: Reserved */
-#define FLEXIO_TIMCFG_TIMENA_SHIFT        (8)       /* Bits 8-10: Timer Enable (TIMENA) */ 
+#define FLEXIO_TIMCFG_TIMENA_SHIFT        (8)       /* Bits 8-10: Timer Enable (TIMENA) */
 #define FLEXIO_TIMCFG_TIMENA_MASK         (0x07 << FLEXIO_TIMCFG_TIMENA_SHIFT)
 #  define FLEXIO_TIMCFG_TIMENA_ALWAYS     (0x00 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer always enabled */
 #  define FLEXIO_TIMCFG_TIMENA_TIMENA     (0x01 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Timer N-1 enable */
@@ -713,7 +713,7 @@
 #  define FLEXIO_TIMCFG_TIMRST_TRGBOTH    (0x07 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer reset on Trigger rising or falling edge */
 
                                                     /* Bit 19: Reserved */
-#define FLEXIO_TIMCFG_TIMDEC_SHIFT             (20) /* Bits 20-22: Timer Decrement (TIMDEC) */ 
+#define FLEXIO_TIMCFG_TIMDEC_SHIFT             (20) /* Bits 20-22: Timer Decrement (TIMDEC) */
 #define FLEXIO_TIMCFG_TIMDEC_MASK              (0x07 << FLEXIO_TIMCFG_TIMDEC_SHIFT)
 #  define FLEXIO_TIMCFG_TIMDEC_CLKTIMOUT       (0x00 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on FlexIO clock, Shift clock equals Timer output */
 #  define FLEXIO_TIMCFG_TIMDEC_TRGINBOTHTIMOUT (0x01 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (both edges), Shift clock equals Timer output */
@@ -725,7 +725,7 @@
 #  define FLEXIO_TIMCFG_TIMDEC_TRGINRISTRGIN   (0x07 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input */
 
                                                     /* Bit 23: Reserved */
-#define FLEXIO_TIMCFG_TIMOUT_SHIFT        (24)      /* Bits 24-25: Timer Output (TIMOUT) */ 
+#define FLEXIO_TIMCFG_TIMOUT_SHIFT        (24)      /* Bits 24-25: Timer Output (TIMOUT) */
 #define FLEXIO_TIMCFG_TIMOUT_MASK         (0x03 << FLEXIO_TIMCFG_TIMOUT_SHIFT)
 #  define FLEXIO_TIMCFG_TIMOUT_ONE        (0x00 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic one when enabled and is not affected by timer reset */
 #  define FLEXIO_TIMCFG_TIMOUT_ZERO       (0x01 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic zero when enabled and is not affected by timer reset */

arch/arm/src/s32k3xx/hardware/s32k3xx_lpi2c.h

@@ -74,7 +74,7 @@
 #define S32K3XX_LPI2C0_MDER                 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MDER_OFFSET)
 #define S32K3XX_LPI2C0_MCFGR0               (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR0_OFFSET)
 #define S32K3XX_LPI2C0_MCFGR1               (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR1_OFFSET)
-#define S32K3XX_LPI2C0_MCFGR2               (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET) 
+#define S32K3XX_LPI2C0_MCFGR2               (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET)
 #define S32K3XX_LPI2C0_MCFGR3               (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR3_OFFSET)
 #define S32K3XX_LPI2C0_MDMR                 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MDMR_OFFSET)
 #define S32K3XX_LPI2C0_MCCR0                (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCCR0_OFFSET)
@@ -85,7 +85,7 @@
 #define S32K3XX_LPI2C0_MRDR                 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MRDR_OFFSET)
 #define S32K3XX_LPI2C0_SCR                  (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SCR_OFFSET)
 #define S32K3XX_LPI2C0_SSR                  (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SSR_OFFSET)
-#define S32K3XX_LPI2C0_SIER                 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SIER_OFFSET) 
+#define S32K3XX_LPI2C0_SIER                 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SIER_OFFSET)
 #define S32K3XX_LPI2C0_SDER                 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SDER_OFFSET)
 #define S32K3XX_LPI2C0_SCFGR1               (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SCFGR1_OFFSET)
 #define S32K3XX_LPI2C0_SCFGR2               (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SCFGR2_OFFSET)
@@ -103,7 +103,7 @@
 #define S32K3XX_LPI2C1_MDER                 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MDER_OFFSET)
 #define S32K3XX_LPI2C1_MCFGR0               (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR0_OFFSET)
 #define S32K3XX_LPI2C1_MCFGR1               (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR1_OFFSET)
-#define S32K3XX_LPI2C1_MCFGR2               (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET) 
+#define S32K3XX_LPI2C1_MCFGR2               (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET)
 #define S32K3XX_LPI2C1_MCFGR3               (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR3_OFFSET)
 #define S32K3XX_LPI2C1_MDMR                 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MDMR_OFFSET)
 #define S32K3XX_LPI2C1_MCCR0                (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCCR0_OFFSET)
@@ -114,7 +114,7 @@
 #define S32K3XX_LPI2C1_MRDR                 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MRDR_OFFSET)
 #define S32K3XX_LPI2C1_SCR                  (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SCR_OFFSET)
 #define S32K3XX_LPI2C1_SSR                  (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SSR_OFFSET)
-#define S32K3XX_LPI2C1_SIER                 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SIER_OFFSET) 
+#define S32K3XX_LPI2C1_SIER                 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SIER_OFFSET)
 #define S32K3XX_LPI2C1_SDER                 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SDER_OFFSET)
 #define S32K3XX_LPI2C1_SCFGR1               (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SCFGR1_OFFSET)
 #define S32K3XX_LPI2C1_SCFGR2               (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SCFGR2_OFFSET)
@@ -141,7 +141,7 @@
 /* Parameter Register (PARAM) */
 
 #define LPI2C_PARAM_MTXFIFO_SHIFT         (0)       /* Bits 0-3: Master Transmit FIFO Size (MTXFIFO) */
-#define LPI2C_PARAM_MTXFIFO_MASK          (0x0f << LPI2C_PARAM_MTXFIFO_SHIFT)    
+#define LPI2C_PARAM_MTXFIFO_MASK          (0x0f << LPI2C_PARAM_MTXFIFO_SHIFT)
 #  define LPI2C_PARAM_MTXFIFO_1_WORDS     (0x00 << LPI2C_PARAM_MTXFIFO_SHIFT)
 #  define LPI2C_PARAM_MTXFIFO_2_WORDS     (0x01 << LPI2C_PARAM_MTXFIFO_SHIFT)
 #  define LPI2C_PARAM_MTXFIFO_4_WORDS     (0x02 << LPI2C_PARAM_MTXFIFO_SHIFT)
@@ -287,7 +287,7 @@
 /* Master Config Register 2 (MCFGR2) */
 
 #define LPI2C_MCFGR2_BUSIDLE_SHIFT        (0)       /* Bits 0-11: Bus Idle Timeout (BUSIDLE) */
-#define LPI2C_MCFGR2_BUSIDLE_MASK         (0x0fff << LPI2C_MCFGR2_BUSIDLE_SHIFT) 
+#define LPI2C_MCFGR2_BUSIDLE_MASK         (0x0fff << LPI2C_MCFGR2_BUSIDLE_SHIFT)
 #define LPI2C_MCFGR2_BUSIDLE_DISABLE      (0x0000 << LPI2C_MCFGR2_BUSIDLE_SHIFT)
 #  define LPI2C_MCFGR2_BUSIDLE(n)         (((n) << LPI2C_MCFGR2_BUSIDLE_SHIFT) & LPI2C_MCFGR2_BUSIDLE_MASK)
                                                     /* Bits 12-15: Reserved */
@@ -306,7 +306,7 @@
 
                                                     /* Bits 0-7: Reserved */
 #define LPI2C_MCFGR3_PINLOW_SHIFT         (8)       /* Bits 8-19: Pin Low Timeout (PINLOW) */
-#define LPI2C_MCFGR3_PINLOW_MASK          (0x0fff << LPI2C_MCFGR3_PINLOW_SHIFT)  
+#define LPI2C_MCFGR3_PINLOW_MASK          (0x0fff << LPI2C_MCFGR3_PINLOW_SHIFT)
 #  define LPI2C_MCFGR3_PINLOW_CYCLES(n)   (((n) << LPI2C_MCFGR3_PINLOW_SHIFT) & LPI2C_MCFGR3_PINLOW_MASK)
                                                     /* Bits 20-31: Reserved */
 

arch/arm/src/s32k3xx/hardware/s32k3xx_mc_rgm.h

@@ -173,7 +173,7 @@
 
 #define MC_RGM_FRENTC_FRET_EN            (1 << 0)  /* Bit 0: Functional Reset Entry Timer Enable (FRET_EN) */
 #define MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT (1)       /* Bits 1-31: Functional Reset Entry Timer Value (FRET_TIMEOUT) */
-#define MC_RGM_FRENTC_FRET_TIMEOUT_MASK  (0x7fffffff << MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT) 
+#define MC_RGM_FRENTC_FRET_TIMEOUT_MASK  (0x7fffffff << MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT)
 
 /* Low Power Debug Control Register (LPDEBUG) */
 

arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h

@@ -418,9 +418,9 @@
 #define QSPI_LUT_OPRND0(n)                (((n) << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK)
 #define QSPI_LUT_PAD0_SHIFT               (8)       /* Bits 8-9: Pad information for INSTR0 (PAD0) */
 #define QSPI_LUT_PAD0_MASK                (0x03 << QSPI_LUT_PAD0_SHIFT)
-#  define QSPI_LUT_PAD0_1                 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */ 
+#  define QSPI_LUT_PAD0_1                 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */
-#  define QSPI_LUT_PAD0_2                 (0x01 << QSPI_LUT_PAD0_SHIFT) /* 2 Pad */ 
+#  define QSPI_LUT_PAD0_2                 (0x01 << QSPI_LUT_PAD0_SHIFT) /* 2 Pad */
-#  define QSPI_LUT_PAD0_4                 (0x02 << QSPI_LUT_PAD0_SHIFT) /* 4 Pad */ 
+#  define QSPI_LUT_PAD0_4                 (0x02 << QSPI_LUT_PAD0_SHIFT) /* 4 Pad */
 
 #define QSPI_LUT_INSTR0_SHIFT             (10)      /* Bits 10-15: Instruction 0 (INSTR0) */
 #define QSPI_LUT_INSTR0_MASK              (0x3f << QSPI_LUT_INSTR0_SHIFT)
@@ -431,9 +431,9 @@
 #define QSPI_LUT_OPRND1(n)                (((n) << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK)
 #define QSPI_LUT_PAD1_SHIFT               (24)       /* Bits 24-25: Pad information for INSTR1 (PAD1) */
 #define QSPI_LUT_PAD1_MASK                (0x03 << QSPI_LUT_PAD1_SHIFT)
-#  define QSPI_LUT_PAD1_1                 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */ 
+#  define QSPI_LUT_PAD1_1                 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */
-#  define QSPI_LUT_PAD1_2                 (0x01 << QSPI_LUT_PAD1_SHIFT) /* 2 Pad */ 
+#  define QSPI_LUT_PAD1_2                 (0x01 << QSPI_LUT_PAD1_SHIFT) /* 2 Pad */
-#  define QSPI_LUT_PAD1_4                 (0x02 << QSPI_LUT_PAD1_SHIFT) /* 4 Pad */ 
+#  define QSPI_LUT_PAD1_4                 (0x02 << QSPI_LUT_PAD1_SHIFT) /* 4 Pad */
 
 #define QSPI_LUT_INSTR1_SHIFT             (26)      /* Bits 26-31: Instruction 1 (INSTR1) */
 #define QSPI_LUT_INSTR1_MASK              (0x3f << QSPI_LUT_INSTR1_SHIFT)

arch/arm/src/s32k3xx/hardware/s32k3xx_wkpu.h

@@ -95,7 +95,7 @@
 #define WKPU_NCR_NFEE0                (1 << 25)  /* Bit 25: NMI Falling-edge Events Enable 0 (NFEE0) */
 #define WKPU_NCR_NREE0                (1 << 26)  /* Bit 26: NMI Rising-Edge Events Enable 0 (NREE0) */
                                                  /* Bit 27: Reserved */
-#define WKPU_NCR_NWRE0                (1 << 28)  /* Bit 28: NMI Wakeup Request Enable 0 (NWRE0) */     
+#define WKPU_NCR_NWRE0                (1 << 28)  /* Bit 28: NMI Wakeup Request Enable 0 (NWRE0) */
 #define WKPU_NCR_NDSS0_SHIFT          (29)       /* Bits 29-30: NMI Destination Source Select 0 (NDSS0) */
 #define WKPU_NCR_NDSS0_MASK           (0x03 << WKPU_NCR_NDSS0_SHIFT)
 #  define WKPU_NCR_NDSS0_NMI          (0x00 << WKPU_NCR_NDSS0_SHIFT) /* Non-maskable interrupt */

arch/arm/src/s32k3xx/s32k3xx_emac.c

@@ -73,7 +73,7 @@
 
 /* Memory synchronization */
 
-#define MEMORY_SYNC() //do { ARM_DSB(); ARM_ISB(); } while (0)                                                                                                                                                                                                                                    
+#define MEMORY_SYNC() //do { ARM_DSB(); ARM_ISB(); } while (0)
 
 /* If processing is not done at the interrupt level, then work queue support
  * is required.

arch/arm/src/sama5/sam_flexcom_spi.c

@@ -681,7 +681,7 @@ static inline struct sam_flex_spidev_s *flex_spi_dev(struct sam_flex_spics_s
       case 4:
         return &g_flexcom4dev;
         break;
-#endif 
+#endif
       default:
 
         /* shouldn't get here */

arch/arm/src/sama5/sam_mcan.c

@@ -78,7 +78,7 @@
 #  define SAMA5_MCAN_CLKSRC           PMC_PCR_GCKCSS_PLLA
 #  define SAMA5_MCAN_CLKSRC_FREQUENCY BOARD_PLLA_FREQUENCY
 #elif defined(CONFIG_SAMA5_MCAN_CLKSRC_UPLL)
-#  define SAMA5_MCAN_CLKSRC           PMC_PCR_GCKCSS_UPLL 
+#  define SAMA5_MCAN_CLKSRC           PMC_PCR_GCKCSS_UPLL
 #  define SAMA5_MCAN_CLKSRC_FREQUENCY BOARD_UPLL_FREQUENCY
 #elif defined(CONFIG_SAMA5_MCAN_CLKSRC_MCK)
 #  define SAMA5_MCAN_CLKSRC           PMC_PCR_GCKCSS_MCK
@@ -1016,7 +1016,7 @@ static const struct sam_config_s g_mcan0const =
   .pid              = SAM_PID_MCAN00,
   .irq0             = SAM_IRQ_MCAN00,
   .irq1             = SAM_IRQ_MCAN01,
-#if defined(CONFIG_SAMA5_MCAN0_ISO11898_1) 
+#if defined(CONFIG_SAMA5_MCAN0_ISO11898_1)
   .mode             = MCAN_ISO11898_1_MODE,
 #elif defined(CONFIG_SAMA5_MCAN0_FD)
   .mode             = MCAN_FD_MODE,

arch/arm/src/sama5/sam_serial.c

@@ -151,7 +151,7 @@
 #  elif defined(CONFIG_SAMA5_UART4)
 #    define TTYS0_DEV           g_uart4port  /* UART4 is ttyS0 */
 #    define UART4_ASSIGNED      1
-#  elif defined(CONFIG_SAMA5_USART0) 
+#  elif defined(CONFIG_SAMA5_USART0)
 #    define TTYS0_DEV           g_usart0port /* USART0 is ttyS0 */
 #    define USART0_ASSIGNED     1
 #  elif defined(CONFIG_SAMA5_USART1)

arch/arm/src/sama5/sam_tsd.c

@@ -1564,7 +1564,7 @@ static void sam_tsd_initialize(struct sam_tsd_s *priv)
    * been initialised. It's the only option allowed and that works.
    */
 
-#ifndef SAMA5_TSD_PENDET_TRIG_ALLOWED  
+#ifndef SAMA5_TSD_PENDET_TRIG_ALLOWED
   /* if we're allowed to use pendet trigger no need to do this */
 
   regval  = sam_adc_getreg(priv, SAM_ADC_TRGR);

arch/arm/src/sama5/sama5d2x_pio.c

@@ -214,7 +214,7 @@ static uint32_t sam_configcommon(pio_pinset_t cfgset)
     {
       if ((cfgset & PIO_CFG_SLOWCLK) != 0)
         {
-          regval |= (PIO_CFGR_IFEN | PIO_CFG_SLOWCLK); 
+          regval |= (PIO_CFGR_IFEN | PIO_CFG_SLOWCLK);
         }
       else
         {

arch/arm/src/stm32f7/Kconfig

@@ -2689,7 +2689,7 @@ config STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED
 		This option configures the stm32_dmacapable to not disqualify
 		DMA operations on memory that is not dcache aligned based solely
 		on the starting address and byte count.
-		
+
 		Use this when ALL buffer extents are known to be aligned, but the
 		the count does not use the complete buffer.
 

arch/arm/src/stm32h7/Kconfig

@@ -432,7 +432,7 @@ config STM32_APP_FORMAT_MCUBOOT
 	select STM32_HAVE_OTA_PARTITION
 	depends on EXPERIMENTAL
 	---help---
-		The MCUboot support of loading the firmware images.		
+		The MCUboot support of loading the firmware images.
 
 comment "MCUboot support depends on CONFIG_EXPERIMENTAL"
 	depends on !EXPERIMENTAL

arch/arm/src/stm32l4/stm32l4_adc.h

@@ -338,7 +338,7 @@
 #  if CONFIG_STM32L4_ADC1_EXTTRIG > 0
 #    define ADC1_EXTCFG_VALUE \
             ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC1_EXTTRIG)  | \
-            ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC1_EXTSEL)                        
+            ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC1_EXTSEL)
 #  endif
 #endif /* CONFIG_STM32L4_ADC1_EXTTRIG */
 
@@ -352,7 +352,7 @@
 #  if CONFIG_STM32L4_ADC2_EXTTRIG > 0
 #    define ADC2_EXTCFG_VALUE \
             ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC2_EXTTRIG)  | \
-            ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC2_EXTSEL)                        
+            ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC2_EXTSEL)
 #  endif
 #endif /* CONFIG_STM32L4_ADC2_EXTTRIG */
 
@@ -366,7 +366,7 @@
 #  if CONFIG_STM32L4_ADC3_EXTTRIG > 0
 #    define ADC3_EXTCFG_VALUE \
             ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC3_EXTTRIG)  | \
-            ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC3_EXTSEL)                        
+            ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC3_EXTSEL)
 #  endif
 #endif /* CONFIG_STM32L4_ADC3_EXTTRIG */
 
@@ -387,7 +387,7 @@
 #  if CONFIG_STM32L4_ADC1_JEXTTRIG > 0
 #    define ADC1_JEXTCFG_VALUE \
             ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC1_JEXTTRIG) | \
-            ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC1_JEXTSEL)                        
+            ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC1_JEXTSEL)
 #  endif
 #endif /* CONFIG_STM32L4_ADC1_JEXTTRIG */
 
@@ -399,7 +399,7 @@
 #  if CONFIG_STM32L4_ADC2_JEXTTRIG > 0
 #    define ADC2_JEXTCFG_VALUE \
             ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC2_JEXTTRIG) | \
-            ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC2_JEXTSEL)                        
+            ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC2_JEXTSEL)
 #  endif
 #endif /* CONFIG_STM32L4_ADC2_JEXTTRIG */
 
@@ -411,7 +411,7 @@
 #  if CONFIG_STM32L4_ADC3_JEXTTRIG > 0
 #    define ADC3_JEXTCFG_VALUE \
             ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC3_JEXTTRIG) | \
-            ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC3_JEXTSEL)                        
+            ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC3_JEXTSEL)
 #  endif
 #endif /* CONFIG_STM32L4_ADC3_JEXTTRIG */
 

arch/arm/src/stm32l5/hardware/stm32l5_pwr.h

@@ -141,7 +141,7 @@
 #  define PWR_CR3_RRS_4K_ON      (2 << PWE_CR3_RRS_SHIFT) /* 10: Upper 4KB of SRAM2 powered on in Standby-mode */
 #define PWR_CR3_APC              (1 << 10)                /* Bit 10: Apply pull-up and pull-down configuration */
 #define PWR_CR3_ULPMEN           (1 << 11)                /* Bit 11: Ultra-low-power mode enable */
-#define PWR_CR3_UCPD_STBY        (1 << 13)                /* Bit 13: USB Type-C power delivery Standby-mode */ 
+#define PWR_CR3_UCPD_STBY        (1 << 13)                /* Bit 13: USB Type-C power delivery Standby-mode */
 #define PWR_CR3_UCPD_DBDIS       (1 << 14)                /* Bit 14: USB Type-C power delivery dead battery disable */
 
 /* Power control register 4 */

arch/arm/src/stm32u5/hardware/stm32_flash.h

@@ -228,7 +228,7 @@
 #define FLASH_NSCR_PNB_MASK       (0x7F << FLASH_NSCR_PNB_SHIFT)
 #define FLASH_NSCR_PNB(n)         ((n)  << FLASH_NSCR_PNB_SHIFT) /* Page n, n = 0..127 */
 #define FLASH_NSCR_BKER           (1 << 11)                      /* Bit 11: Non-secure bank selection for page erase */
-#define FLASH_NSCR_BWR            (1 << 14)                      /* Bit 14: Non-secure burst write programming mode */ 
+#define FLASH_NSCR_BWR            (1 << 14)                      /* Bit 14: Non-secure burst write programming mode */
 #define FLASH_NSCR_MER2           (1 << 15)                      /* Bit 15: Non-secure bank 2 mass erase */
 #define FLASH_NSCR_STRT           (1 << 16)                      /* Bit 16: Non-secure start */
 #define FLASH_NSCR_OPTSTRT        (1 << 17)                      /* Bit 17: Options modification start */

arch/arm/src/stm32u5/hardware/stm32_pwr.h

@@ -180,7 +180,7 @@
 
 /* PWR Disable backup domain register */
 
-#define PWR_DBPR_DBP             (1 <<  0)                 /* Bit  0: Disable Backup domain write protection. */ 
+#define PWR_DBPR_DBP             (1 <<  0)                 /* Bit  0: Disable Backup domain write protection. */
 
 /* PWR Supply voltage monitoring status register */