mirror of
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Add mapping for the page table
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2872 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -59,35 +59,85 @@
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# error "Cannot support both CONFIG_PAGING and CONFIG_ARCH_ROMPGTABLE"
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# endif
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/* Page Size Selections ***************************************************/
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/* Create some friendly definitions to handle some differences between
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* small and tiny pages.
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*/
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# if CONFIG_PAGING_PAGESIZE == 1024
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/* Number of pages in an L2 table per L1 entry */
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# define PTE_NPAGES PTE_TINY_NPAGES
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/* L2 Page table address */
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# define PG_L2_BASE_PADDR PGTABLE_FINE_BASE_PADDR
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# define PG_L2_BASE_VADDR PGTABLE_FINE_BASE_VADDR
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_FINE|PMD_BIT4|PTE_CACHEABLE)
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/* MMU Flags for each memory region */
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L2_TEXTFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_FINE|PMD_BIT4|PTE_CACHEABLE)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW|PTE_CACHEABLE)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
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# define MMU_L1_PGTABFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L2_PGTABFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW)
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# elif CONFIG_PAGING_PAGESIZE == 4096
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/* Number of pages in an L2 table per L1 entry */
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# define PTE_NPAGES PTE_SMALL_NPAGES
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/* L2 Page table address */
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# define PG_L2_BASE_PADDR PGTABLE_COARSE_BASE_PADDR
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# define PG_L2_BASE_vADDR PGTABLE_COARSE_BASE_VADDR
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_COARSE|PMD_BIT4|PTE_CACHEABLE)
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# define PG_L2_BASE_VADDR PGTABLE_COARSE_BASE_VADDR
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/* MMU Flags for each memory region. */
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L2_TEXTFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_COARSE|PMD_BIT4|PTE_CACHEABLE|PTE_BUFFERABLE)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
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# define MMU_L1_PGTABFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L2_PGTABFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
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# else
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# error "Need extended definitions for CONFIG_PAGING_PAGESIZE"
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# endif
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#define PT_SIZE (PTE_NPAGES * 4)
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/* We position the data section PTE's just after the text section PTE's */
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/* We position the data section PTEs just after the text section PTE's */
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#define PG_L2_DATA_PADDR (PG_L2_BASE_PADDR + 4*PG_TEXT_NPAGES)
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#define PG_L2_DATA_VADDR (PG_L2_BASE_VADDR + 4*PG_TEXT_NPAGES)
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/* Page Table Info: The number of pages in the in the page table
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* (PG_PGTABLE_NPAGES). We position the pagetable PTEs just after
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* the data section PTEs.
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*/
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#define PG_PGTABLE_NPAGES (PGTABLE_SIZE >> PAGESHIFT)
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#define PG_L2_PGTABLE_PADDR (PG_L2_DATA_PADDR + 4*PG_DATA_NPAGES)
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#define PG_L2_PGTABLE_VADDR (PG_L2_DATA_VADDR + 4*PG_DATA_NPAGES)
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/* This is the total number of pages used in the initial page table setup
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* in up_head.S
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*/
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#define PG_STATIC_NPAGES (PG_TEXT_NPAGES + PG_DATA_PAGES + PG_PGTABLE_NPAGES)
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/* For page managment purposes, the following summarize the "heap" of
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* free pages
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*/
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#define PG_POOL_FIRSTPAGE PG_STATIC_NPAGES
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#define PG_POOL_NPAGES CONFIG_PAGING_NLOCKED
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#endif /* CONFIG_PAGING */
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/****************************************************************************
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+83
-28
@@ -180,17 +180,40 @@ __start:
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str r3, [r4, r0, lsr #18] /* identity mapping */
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#ifdef CONFIG_PAGING
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/* Populate the L1 table for the locked and paged text regions */
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/* Map the read-only .text region in place. This must be done
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* before the MMU is enabled and the virtual addressing takes
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* effect. First populate the L1 table for the locked and paged
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* text regions.
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*
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* We could probably make the the pg_span and pg_map macros into
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* call-able subroutines, but we would have to be carefully during
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* this phase while we are operating in a physical address space.
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*/
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adr r0, .Ltxtspan
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ldmia r0, {r0, r1, r2, r3}
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pg_span r0, r1, r2, r3, r4
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/* Populate the L2 table for the locked text region only */
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/* Then populate the L2 table for the locked text region only. */
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adr r0, .Ltxtmap
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ldmia r0, {r0, r1, r2, r3}
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pg_map r0, r1, r2, r3, r4
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/* Make sure that the page table is itself mapped and and read/write-able.
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* First, populate the L1 table:
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*/
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adr r0, .Lptabspan
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ldmia r0, {r0, r1, r2, r3}
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pg_span r0, r1, r2, r3, r4
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/* Then populate the L2 table. */
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adr r0, .Lptabmap
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ldmia r0, {r0, r1, r2, r3}
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pg_map r0, r1, r2, r3, r4
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#else
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/* Create a virtual single section mapping for the first MB of the .text
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* address space. Now, we have the first 1MB mapping to both phyical and
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@@ -303,7 +326,7 @@ __start:
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* PC_Relative Data
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****************************************************************************/
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/* These addresses are all virtual address */
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/* Most addresses are all virtual address */
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.type .LCvstart, %object
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.LCvstart:
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@@ -312,17 +335,43 @@ __start:
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#ifndef CONFIG_ARCH_ROMPGTABLE
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.type .LCmmuflags, %object
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.LCmmuflags:
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.long MMU_MEMFLAGS
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.long MMU_MEMFLAGS /* MMU flags for memory sections */
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#endif
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.type .LCppagetable, %object
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.type .LCppgtable, %object
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.LCppgtable:
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.long PGTABLE_BASE_PADDR /* Physical start of DRAM */
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.long PGTABLE_BASE_PADDR /* Physical start of page table */
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#ifndef CONFIG_ARCH_ROMPGTABLE
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.type .LCvpagetable, %object
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.type .LCvpgtable, %object
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.LCvpgtable:
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.long PGTABLE_BASE_VADDR /* Virtual start of DRAM */
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.long PGTABLE_BASE_VADDR /* Virtual start of page table */
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#endif
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#ifdef CONFIG_PAGING
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.Ltxtspan:
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.long PG_L2_BASE_PADDR /* Physical address of L2 table */
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.long PG_LOCKED_VBASE /* Virtual address of locked base */
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.long PG_TEXT_NPAGES /* Total mapped text pages */
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.long MMU_L1_TEXTFLAGS /* L1 MMU flags to use */
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.Ltxtmap:
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.long PG_L2_BASE_PADDR /* Physical address of L2 table */
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.long PG_LOCKED_PBASE /* Physical address of locked base */
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.long CONFIG_PAGING_NLOCKED /* Number of pages in the locked region */
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.long MMU_L2_TEXTFLAGS /* L2 MMU flags to use */
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.Lptabspan:
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.long PG_L2_PGTABLE_PADDR /* Physical address of L2 table */
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.long PGTABLE_BASE_VADDR /* Virtual address of the page table */
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.long PG_TEXT_NPAGES /* Total mapped page table pages */
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.long MMU_L1_PGTABFLAGS /* L1 MMU flags to use */
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.Lptabmap:
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.long PG_L2_PGTABLE_PADDR /* Physical address of L2 table */
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.long PGTABLE_BASE_PADDR /* Physical address of the page table */
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.long CONFIG_PAGING_NLOCKED /* Total mapped page table pages */
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.long MMU_L2_PGTABFLAGS /* L2 MMU flags to use */
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#endif
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.size _start, .-_start
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@@ -353,15 +402,15 @@ __start:
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#if defined(CONFIG_PAGING)
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/* Populate the L1 table for the data regions */
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adr r0, .Ldatamap
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adr r0, .Ldataspan
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ldmia r0, {r0, r1, r2, r3}
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pg_span r0, r1, r2, r3, r4
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/* Populate the L2 table for the data region */
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adr r0, .Ldatamap
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ldmia r0, {r0, r1, r2, r3, r4}
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pg_map r0, r1, r2, r4, r3
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ldmia r0, {r0, r1, r2, r3}
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pg_map r0, r1, r2, r3, r4
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#elif defined(CONFIG_BOOT_RUNFROMFLASH)
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# error "Logic not implemented"
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@@ -424,7 +473,13 @@ __start:
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*/
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#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_PAGING)
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# error "Logic not implemented"
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adr r3, .Ldatainit
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ldmia r3, {r0, r1, r2}
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1: ldmia r0!, {r3 - r10}
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stmia r1!, {r3 - r10}
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cmp r1, r2
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blt 1b
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#endif
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/* Perform early C-level, platform-specific initialization */
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@@ -452,24 +507,24 @@ __start:
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.long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
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#ifdef CONFIG_PAGING
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.Ltxtspan:
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.long PG_L2_BASE_PADDR
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.long PG_LOCKED_PBASE
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.long PG_TEXT_NPAGES
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.long MMU_L1_TEXTFLAGS
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.Ltxtmap:
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.long PG_L2_BASE_PADDR
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.long PG_LOCKED_PBASE
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.long CONFIG_PAGING_NLOCKED
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.long MMU_L2_TEXTFLAGS
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.Ldataspan:
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.long PG_L2_DATA_PADDR /* Physical address of L2 table */
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.long PG_DATA_PBASE /* Physical address of data base */
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.long PG_DATA_NPAGED /* Number of pages in the data region */
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.long MMU_L1_DATAFLAGS /* L1 MMU flags to use */
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.Ldatamap:
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.long PG_L2_DATA_PADDR
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.long PG_DATA_PBASE
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.long PG_DATA_NPAGED
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.long MMU_L1_DATAFLAGS
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.long MMU_L2_DATAFLAGS
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.long PG_L2_DATA_PADDR /* Physical address of L2 table */
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.long PG_DATA_VBASE /* Virtual address of data base */
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.long PG_DATA_NPAGED /* Number of pages in the data region */
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.long MMU_L2_DATAFLAGS /* L2 MMU flags to use */
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#endif
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#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_PAGING)
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.Ldatainit:
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.long _eronly /* Where .data defaults are stored in FLASH */
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.long _sdata /* Where .data needs to reside in SDRAM */
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.long _edata
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#endif
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.size .Lvstart, .-.Lvstart
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@@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/arm/up_nommuhead.S
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*
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* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/dm320/dm320_boot.c
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*
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* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/lpc313x/lpc313x_boot.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -234,6 +234,10 @@ static void up_vectormapping(void)
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/************************************************************************************
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* Name: up_copyvectorblock
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*
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* Description:
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* Copy the interrupt block to its final destination.
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*
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************************************************************************************/
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static void up_copyvectorblock(void)
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@@ -267,6 +271,14 @@ static void up_copyvectorblock(void)
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: up_boot
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*
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* Description:
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* Complete boot operations started in up_head.S
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*
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************************************************************************************/
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void up_boot(void)
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{
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/* __start provided the basic MMU mappings for SRAM. Now provide mappings for all
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+37
-12
@@ -77,7 +77,8 @@
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#define PG_ALIGNUP(addr) (((addr) + PAGEMASK) & ~PAGEMASK)
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/* CONFIG_PAGING_NLOCKED - This is the number of locked pages in the memory
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* map. The size of locked address region will then be:
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* map. The size of locked address region will then be given by
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* PG_LOCKED_SIZE.
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*/
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#define PG_LOCKED_SIZE (CONFIG_PAGING_NLOCKED << PAGESHIFT)
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@@ -87,6 +88,12 @@
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* not defined, then this logic will be set to then to CONFIG_DRAM_START
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* and CONFIG_DRAM_VSTART (i.e., assuming that the base address of the
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* locked region is at the virtual address of the beginning of RAM).
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*
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* NOTE: In some architectures, it may be necessary to take some memory
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* from the beginning of this region for vectors or for a page table.
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* In such cases, CONFIG_PAGING_LOCKED_P/VBASE should take that into
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* consideration to prevent overlapping the locked memory region and the
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* system data at the beginning of SRAM.
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*/
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#if defined(CONFIG_PAGING_LOCKED_PBASE) && defined(CONFIG_PAGING_LOCKED_VBASE)
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@@ -110,10 +117,19 @@
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#define PG_PAGED_SIZE (CONFIG_PAGING_NPAGED << PAGESHIFT)
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/* This positions the paging Read-Only text section */
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/* This positions the paging Read-Only text section. If the configuration
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* did not override the default, the paged region will immediately follow
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* the locked region.
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*/
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#if defined(CONFIG_PAGING_LOCKED_PBASE) && defined(CONFIG_PAGING_LOCKED_VBASE)
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# define PG_LOCKED_PBASE CONFIG_PAGING_LOCKED_PBASE
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# define PG_LOCKED_VBASE CONFIG_PAGING_LOCKED_VBASE
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#else
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# define PG_PAGED_PBASE PG_LOCKED_PEND
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# define PG_PAGED_VBASE PG_LOCKED_VEND
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#endif
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#define PG_PAGED_PEND (PG_PAGED_PBASE + PG_PAGED_SIZE)
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#define PG_PAGED_VEND (PG_PAGED_VBASE + PG_PAGED_SIZE)
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@@ -123,23 +139,32 @@
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#define PG_TEXT_SIZE (PG_TEXT_NPAGES << PAGESHIFT)
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/* CONFIG_PAGING_NDATA - This is the number of data pages in the memory
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* map. The size of data address region will then be:
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* map. The data region will extend to the end of RAM unless overridden
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* by a setting in the configuration file.
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*
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* NOTE: In some architectures, it may be necessary to take some memory
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* from the end of RAM for page tables or other system usage. The
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* configuration settings and linker directives must be cognizant of that.
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* CONFIG_PAGING_NDATA should be defined to prevent the data region from
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* extending all the way to the end of memory.
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*/
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#define PG_RAM_PAGES (CONFIG_DRAM_SIZE >> PAGESHIFT)
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#if PG_RAM_PAGES <= PG_TEXT_NPAGES
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#ifdef CONFIG_PAGING_NDATA
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# PG_DATA_NPAGES CONFIG_PAGING_NDATA
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#elif PG_RAM_PAGES > PG_TEXT_NPAGES
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# PG_DATA_NPAGES (PG_RAM_PAGES - PG_TEXT_NPAGES)
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#else
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# error "Not enough memory for this page layout"
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#endif
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#ifdef CONFIG_PAGING_NDATA
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# PG_DATA_NPAGED CONFIG_PAGING_NDATA
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#else
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# PG_DATA_NPAGED (PG_RAM_PAGES - PG_TEXT_NPAGES)
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#endif
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#define PG_DATA_SIZE (PG_DATA_NPAGES << PAGESHIFT)
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#define PG_DATA_SIZE (CONFIG_PAGING_NPAGED << PAGESHIFT)
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/* This positions the Read/Write data region */
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/* This positions the Read/Write data region. If the configuration
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* did not override the default, the paged region will immediately follow
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* the paged region and will extend to the end of memory.
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*/
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#if defined(CONFIG_PAGING_DATA_PBASE) && defined(CONFIG_PAGING_DATA_VBASE)
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# define PG_DATA_PBASE CONFIG_PAGING_DATA_PBASE
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