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riscv/bl602: Swap SPI MISO and MOSI

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This commit is contained in:
lupyuen
2021-12-13 07:47:02 +08:00
committed by Xiang Xiao
parent 8ce3337e85
commit 2a87b37a69
1 changed files with 30 additions and 0 deletions
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arch/risc-v/src/bl602/bl602_spi.c
+30
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@@ -1077,6 +1077,32 @@ static void bl602_set_spi_0_act_mode_sel(uint8_t mod)
} }
} }
/****************************************************************************
* Name: bl602_swap_spi_0_mosi_with_miso
*
* Description:
* Swap SPI0 MOSI with MISO
*
* Input Parameters:
* swap - Non-zero to swap MOSI and MISO
*
* Returned Value:
* None
*
****************************************************************************/
static void bl602_swap_spi_0_mosi_with_miso(uint8_t swap)
{
if (swap)
{
modifyreg32(BL602_GLB_GLB_PARM, 0, GLB_PARM_REG_SPI_0_SWAP);
}
else
{
modifyreg32(BL602_GLB_GLB_PARM, GLB_PARM_REG_SPI_0_SWAP, 0);
}
}
/**************************************************************************** /****************************************************************************
* Name: bl602_spi_init * Name: bl602_spi_init
* *
@@ -1109,6 +1135,10 @@ static void bl602_spi_init(struct spi_dev_s *dev)
bl602_set_spi_0_act_mode_sel(1); bl602_set_spi_0_act_mode_sel(1);
/* swap MOSI with MISO to be consistent with BL602 Reference Manual */
bl602_swap_spi_0_mosi_with_miso(1);
/* spi cfg reg: /* spi cfg reg:
* cr_spi_deg_en 1 * cr_spi_deg_en 1
* cr_spi_m_cont_en 0 * cr_spi_m_cont_en 0