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Clean up compilation errors

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1114 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2008-11-01 14:01:05 +00:00
parent 128fca24fb
commit 2a7f18f3e3
10 changed files with 116 additions and 119 deletions
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arch/arm/src/str71x/str71x_decodeirq.c
+1 -1
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@@ -95,7 +95,7 @@ void up_decodeirq(uint32 *regs)
* info from CIC register without the setup. * info from CIC register without the setup.
*/ */
unsigned int irq = getreq32(STR71X_EIC_IVR); unsigned int irq = getreg32(STR71X_EIC_IVR);
/* Verify that the resulting IRQ number is valid */ /* Verify that the resulting IRQ number is valid */
arch/arm/src/str71x/str71x_eic.h
+2 -2
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@@ -42,7 +42,7 @@
#include <nuttx/config.h> #include <nuttx/config.h>
#include <sys/types.h> #include <sys/types.h>
#include "<arch/irq.h> #include <arch/irq.h>
/************************************************************************************ /************************************************************************************
* Definitions * Definitions
@@ -93,7 +93,7 @@
#define STR71X_EIC_SIR31_OFFSET (0x00dc) /* 32-bits wide */ #define STR71X_EIC_SIR31_OFFSET (0x00dc) /* 32-bits wide */
#define STR71X_EIC_NCHANNELS (32) #define STR71X_EIC_NCHANNELS (32)
#define STR71X_EIC_SIR_BASE ((STR71X_EIC_BASE + STR71X_EIC_SIR_OFFSET) #define STR71X_EIC_SIR_BASE (STR71X_EIC_BASE + STR71X_EIC_SIR_OFFSET)
/* Enhanced Interupt Controller (EIC) registers *************************************/ /* Enhanced Interupt Controller (EIC) registers *************************************/
arch/arm/src/str71x/str71x_i2c.h
+67 -73
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@@ -50,7 +50,7 @@
/* Register offets ******************************************************************/ /* Register offets ******************************************************************/
#define STR71X_I2C_SR_OFFSET (0x0000) /* 8-bits wide */ #define STR71X_I2C_CR_OFFSET (0x0000) /* 8-bits wide */
#define STR71X_I2C_SR1_OFFSET (0x0004) /* 8-bits wide */ #define STR71X_I2C_SR1_OFFSET (0x0004) /* 8-bits wide */
#define STR71X_I2C_SR2_OFFSET (0x0008) /* 8-bits wide */ #define STR71X_I2C_SR2_OFFSET (0x0008) /* 8-bits wide */
#define STR71X_I2C_CCR_OFFSET (0x000c) /* 8-bits wide */ #define STR71X_I2C_CCR_OFFSET (0x000c) /* 8-bits wide */
@@ -61,88 +61,82 @@
/* Registers ************************************************************************/ /* Registers ************************************************************************/
#define STR71X_I2C_SR(b) ((b) + STR71X_I2C_SR_OFFSET) #define STR71X_I2C_CR(b) ((b) + STR71X_I2C_SR_OFFSET)
#define STR71X_I2C_SR1(b) ((b) + STR71X_I2C_SR1_OFFSET) #define STR71X_I2C_SR1(b) ((b) + STR71X_I2C_SR1_OFFSET)
#define STR71X_I2C_SR2(b) ((b) + STR71X_I2C_SR2_OFFSET) #define STR71X_I2C_SR2(b) ((b) + STR71X_I2C_SR2_OFFSET)
#define STR71X_I2C_CCR(b) ((b) + STR71X_I2C_CCR_OFFSET) #define STR71X_I2C_CCR(b) ((b) + STR71X_I2C_CCR_OFFSET)
#define STR71X_I2C_OAR1(b) ((b) + STR71X_I2C_OAR1_OFFSET) #define STR71X_I2C_OAR1(b) ((b) + STR71X_I2C_OAR1_OFFSET)
#define STR71X_I2C_OAR2(b) ((b) + STR71X_I2C_OAR2_OFFSET) #define STR71X_I2C_OAR2(b) ((b) + STR71X_I2C_OAR2_OFFSET)
#define STR71X_I2C_DR(b) ((b) + STR71X_I2C_DR_OFFSET) #define STR71X_I2C_DR(b) ((b) + STR71X_I2C_DR_OFFSET)
#define STR71X_I2C_ECCR(b) ((b) + STR71X_I2C_ECCR_OFFSET) #define STR71X_I2C_ECCR(b) ((b) + STR71X_I2C_ECCR_OFFSET)
#define STR71X_I2C0_SR (STR71X_I2C0_BASE + STR71X_I2C_SR_OFFSET) #define STR71X_I2C0_CR (STR71X_I2C0_BASE + STR71X_I2C_SR_OFFSET)
#define STR71X_I2C0_SR1 (STR71X_I2C0_BASE + STR71X_I2C_SR1_OFFSET) #define STR71X_I2C0_SR1 (STR71X_I2C0_BASE + STR71X_I2C_SR1_OFFSET)
#define STR71X_I2C0_SR2 (STR71X_I2C0_BASE + STR71X_I2C_SR2_OFFSET) #define STR71X_I2C0_SR2 (STR71X_I2C0_BASE + STR71X_I2C_SR2_OFFSET)
#define STR71X_I2C0_CCR (STR71X_I2C0_BASE + STR71X_I2C_CCR_OFFSET) #define STR71X_I2C0_CCR (STR71X_I2C0_BASE + STR71X_I2C_CCR_OFFSET)
#define STR71X_I2C0_OAR1 (STR71X_I2C0_BASE + STR71X_I2C_OAR1_OFFSET) #define STR71X_I2C0_OAR1 (STR71X_I2C0_BASE + STR71X_I2C_OAR1_OFFSET)
#define STR71X_I2C0_OAR2 (STR71X_I2C0_BASE + STR71X_I2C_OAR2_OFFSET) #define STR71X_I2C0_OAR2 (STR71X_I2C0_BASE + STR71X_I2C_OAR2_OFFSET)
#define STR71X_I2C0_DR (STR71X_I2C0_BASE + STR71X_I2C_DR_OFFSET) #define STR71X_I2C0_DR (STR71X_I2C0_BASE + STR71X_I2C_DR_OFFSET)
#define STR71X_I2C0_ECCR (STR71X_I2C0_BASE + STR71X_I2C_ECCR_OFFSET) #define STR71X_I2C0_ECCR (STR71X_I2C0_BASE + STR71X_I2C_ECCR_OFFSET)
#define STR71X_I2C1_SR (STR71X_I2C1_BASE + STR71X_I2C_SR_OFFSET) #define STR71X_I2C1_CR (STR71X_I2C1_BASE + STR71X_I2C_SR_OFFSET)
#define STR71X_I2C1_SR1 (STR71X_I2C1_BASE + STR71X_I2C_SR1_OFFSET) #define STR71X_I2C1_SR1 (STR71X_I2C1_BASE + STR71X_I2C_SR1_OFFSET)
#define STR71X_I2C1_SR2 (STR71X_I2C1_BASE + STR71X_I2C_SR2_OFFSET) #define STR71X_I2C1_SR2 (STR71X_I2C1_BASE + STR71X_I2C_SR2_OFFSET)
#define STR71X_I2C1_CCR (STR71X_I2C1_BASE + STR71X_I2C_CCR_OFFSET) #define STR71X_I2C1_CCR (STR71X_I2C1_BASE + STR71X_I2C_CCR_OFFSET)
#define STR71X_I2C1_OAR1 (STR71X_I2C1_BASE + STR71X_I2C_OAR1_OFFSET) #define STR71X_I2C1_OAR1 (STR71X_I2C1_BASE + STR71X_I2C_OAR1_OFFSET)
#define STR71X_I2C1_OAR2 (STR71X_I2C1_BASE + STR71X_I2C_OAR2_OFFSET) #define STR71X_I2C1_OAR2 (STR71X_I2C1_BASE + STR71X_I2C_OAR2_OFFSET)
#define STR71X_I2C1_DR (STR71X_I2C1_BASE + STR71X_I2C_DR_OFFSET) #define STR71X_I2C1_DR (STR71X_I2C1_BASE + STR71X_I2C_DR_OFFSET)
#define STR71X_I2C1_ECCR (STR71X_I2C1_BASE + STR71X_I2C_ECCR_OFFSET) #define STR71X_I2C1_ECCR (STR71X_I2C1_BASE + STR71X_I2C_ECCR_OFFSET)
/* Register bit settings ***********************************************************/ /* Register bit settings ***********************************************************/
ST71X_I2C_CR = 0x00, /* I2C Control Register (CR) */
ST71X_I2C_SR1 = 0x04,
ST71X_I2C_SR2 = 0x08,
ST71X_I2C_CCR = 0x0C,
ST71X_I2C_OAR1 = 0x10,
ST71X_I2C_OAR2 = 0x14,
ST71X_I2C_DR = 0x18,
ST71X_I2C_ECCR = 0x1C
} ST71X_I2C_Registers;
#define ST71X_I2C_SB (0x00000001) #define STR71X_I2CCR_ITE (0x01) /* Bit 0: Interrupt enable */
#define ST71X_I2C_MSL (0x00000002) #define STR71X_I2CCR_STOP (0x02) /* Bit 1: Generation of a stop condition */
#define ST71X_I2C_ADSL (0x00000004) #define STR71X_I2CCR_ACK (0x04) /* Bit 2: Acknowledge enable */
#define ST71X_I2C_BTF (0x00000008) #define STR71X_I2CCR_START (0x08) /* Bit 3: Generation of a start condition */
#define ST71X_I2C_BUSY (0x00000010) #define STR71X_I2CCR_ENGC (0x10) /* Bit 4: Enable general call */
#define ST71X_I2C_TRA (0x00000020) #define STR71X_I2CCR_PE (0x20) /* Bit 5: Peripheral enable */
#define ST71X_I2C_ADD10 (0x00000040)
#define ST71X_I2C_EVF (0x00000080)
#define ST71X_I2C_GCAL (0x00000100)
#define ST71X_I2C_BERR (0x00000200)
#define ST71X_I2C_ARLO (0x00000400)
#define ST71X_I2C_STOPF (0x00000800)
#define ST71X_I2C_AF (0x00001000)
#define ST71X_I2C_ENDAD (0x00002000)
#define ST71X_I2C_STOP (0x00008000)
#define ST71X_I2C_ACK (0x00010000)
#define ST71X_I2C_START (0x00020000)
#define ST71X_I2C_PESET (0x0020) /* I2C Status Register 1 (SR1) */
#define ST71X_I2C_PERESET (0x00df)
#define ST71X_I2C_ENGC (0x0010)
#define ST71X_I2C_START (0x0008)
#define ST71X_I2C_STOP (0x0002)
#define ST71X_I2C_ACK (0x0004)
#define ST71X_I2C_ITE (0x0001)
#define ST71X_I2C_EVENT (0x3fff)
/* I2C Events */ #define STR71X_I2CSR1_SB (0x01) /* Bit 0: Start bit (master mode) */
#define STR71X_I2CSR1_MSL (0x02) /* Bit 1: Master/slave */
#define STR71X_I2CSR1_ADSL (0x04) /* Bit 2: Address matched */
#define STR71X_I2CSR1_BTF (0x08) /* Bit 3: Byte transfer finished */
#define STR71X_I2CSR1_BUSY (0x10) /* Bit 4: Bus busy */
#define STR71X_I2CSR1_TRA (0x20) /* Bit 5: Transmitter/receiver */
#define STR71X_I2CSR1_ADD10 (0x40) /* Bit 6: 10-bit addressing in master mode */
#define STR71X_I2CSR1_EVF (0x80) /* Bit 7: Event flag */
#define ST71X_I2C_EVENT_SLAVEADDRESSMATCHED (ST71X_I2C_EVF|ST71X_I2C_BUSY|ST71X_I2C_ADSL) /* I2C Status Register 2 (SR2) */
#define ST71X_I2C_EVENT_SLAVEBYTERECEIVED (ST71X_I2C_EVF|ST71X_I2C_BUSY|ST71X_I2C_BTF)
#define ST71X_I2C_EVENT_SLAVEBYTETRANSMITTED (ST71X_I2C_EVF|ST71X_I2C_BUSY|ST71X_I2C_BTF|ST71X_I2C_TRA)
#define ST71X_I2C_EVENT_MASTERMODESELECT (ST71X_I2C_EVF|ST71X_I2C_BUSY|ST71X_I2C_MSL|ST71X_I2C_SB)
#define ST71X_I2C_EVENT_MASTERMODESELECTED (ST71X_I2C_EVF|ST71X_I2C_BUSY|ST71X_I2C_MSL|ST71X_I2C_ENDAD)
#define ST71X_I2C_EVENT_MASTERBYTERECEIVED (ST71X_I2C_EVF|ST71X_I2C_BUSY|ST71X_I2C_MSL|ST71X_I2C_BTF)
#define ST71X_I2C_EVENT_MASTERBYTETRANSMITTED (ST71X_I2C_EVF|ST71X_I2C_BUSY|ST71X_I2C_MSL|ST71X_I2C_BTF|ST71X_I2C_TRA)
#define ST71X_I2C_EVENT_MASTERMODEADDRESS10 (ST71X_I2C_EVF|ST71X_I2C_BUSY|ST71X_I2C_MSL|ST71X_I2C_ADD10)
#define ST71X_I2C_EVENT_SLAVESTOPDETECTED ST71X_I2C_STOPF
#define ST71X_I2C_EVENT_SLAVEACKFAILURE (ST71X_I2C_EVF|ST71X_I2C_BUSY|ST71X_I2C_BTF|ST71X_I2C_TRA|ST71X_I2C_AF)
#define ST71X_I2C_BUSERRORDETECTED ST71X_I2C_BERR #define STR71X_I2CSR2_GCAL (0x01) /* Bit 0: General call (slave mode) */
#define ST71X_I2C_ARBITRATIONLOST ST71X_I2C_ARLO #define STR71X_I2CSR2_BERR (0x02) /* Bit 1: Bus error */
#define ST71X_I2C_SLAVEGENERALCALL (ST71X_I2C_BUSY|ST71X_I2C_GCAL) #define STR71X_I2CSR2_ARLO (0x04) /* Bit 2: Arbitration lost */
#define STR71X_I2CSR2_STOPF (0x08) /* Bit 3: Stop detection (slave mode) */
#define STR71X_I2CSR2_AF (0x10) /* Bit 4: Acknowledge failure */
#define STR71X_I2CSR2_ENDAD (0x20) /* Bit 5: End of address transmission */
/* I2C Clock Control Register (CCR) */
#define STR71X_I2CCCR_DIVMASK (0x7f) /* Bits 0-6: 7 bits of the 12-bit clock divider */
#define STR71X_I2CCCR_FMSM (0x80) /* Bit 7: Fast/standard I2C mode */
/* I2C Extended Clock Control Register (ECCR) */
#define STR71X_I2CECCR_DIVMASK (0x1f) /* Bits 0-5: 5 bits of the 12-bit clock divider */
/* I2C Own Address Register 2 (OAR2) */
#define STR71X_I2COAR2_ADDRMASK (0x06) /* Bits 1-2: 2 bits of the 10-bit interface address */
#define STR71X_I2COAR2_FREQMASK (0xe0) /* Bits 5-7: Frequency */
#define STR71X_I2COAR2_5_10 (0x00) /* FPCLK1 = 5 to 10 */
#define STR71X_I2COAR2_10_16 (0x20) /* FPCLK1 = 10 to 16.67 */
#define STR71X_I2COAR2_16_26 (0x40) /* FPCLK1 = 16.67 to 26.67 */
#define STR71X_I2COAR2_26_40 (0x60) /* FPCLK1 = 26.67 to 40 */
#define STR71X_I2COAR2_40_53 (0x80) /* FPCLK1 = 40 to 53.33 */
/************************************************************************************ /************************************************************************************
* Public Types * Public Types
arch/arm/src/str71x/str71x_irq.c
+6 -5
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@@ -39,10 +39,12 @@
#include <nuttx/config.h> #include <nuttx/config.h>
#include <sys/types.h> #include <sys/types.h>
#include <errno.h>
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include "up_arch.h" #include "up_arch.h"
#include "os_internal.h"
#include "up_internal.h" #include "up_internal.h"
#include "chip.h"
/**************************************************************************** /****************************************************************************
* Definitions * Definitions
@@ -72,15 +74,13 @@ uint32 *current_regs;
void up_irqinitialize(void) void up_irqinitialize(void)
{ {
uint32 reg32;
/* The bulk of IRQ initialization if performed in str71x_head.S, so we /* The bulk of IRQ initialization if performed in str71x_head.S, so we
* have very little to do here: * have very little to do here:
*/ */
/* Enable IRQs (but not FIQs -- they aren't used) */ /* Enable IRQs (but not FIQs -- they aren't used) */
putreg32(STR71X_EICICR_IRQEN, STR71X_EIC_ICR) putreg32(STR71X_EICICR_IRQEN, STR71X_EIC_ICR);
/* Currents_regs is non-NULL only while processing an interrupt */ /* Currents_regs is non-NULL only while processing an interrupt */
@@ -178,11 +178,12 @@ void up_maskack_irq(int irq)
int up_irqpriority(int irq, ubyte priority) int up_irqpriority(int irq, ubyte priority)
{ {
uint32 addr;
uint32 reg32; uint32 reg32;
if ((unsigned)irq < NR_IRQS && priority < 16) if ((unsigned)irq < NR_IRQS && priority < 16)
{ {
uint32 addr = STR71X_EIC_SIR(irq); addr = STR71X_EIC_SIR(irq);
reg32 = getreg32(addr); reg32 = getreg32(addr);
reg32 &= STR71X_EICSIR_SIPLMASK; reg32 &= STR71X_EICSIR_SIPLMASK;
reg32 |= priority; reg32 |= priority;
arch/arm/src/str71x/str71x_lowputc.c
+17 -17
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@@ -38,9 +38,11 @@
**************************************************************************/ **************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <sys/types.h>
#include "up_internal.h" #include "up_internal.h"
#include "up_arch.h" #include "up_arch.h"
#include "chp.h" #include "chip.h"
/************************************************************************** /**************************************************************************
* Private Definitions * Private Definitions
@@ -51,7 +53,7 @@
/* Is there a UART enabled? */ /* Is there a UART enabled? */
#if defined(CONFIG_STR71X_UART0) || defined(CONFIG_STR71X_UART1) || \ #if defined(CONFIG_STR71X_UART0) || defined(CONFIG_STR71X_UART1) || \
defined(CONFIG_STR71X_UART2) || defined(CONFIG_STR71X_UART3)) defined(CONFIG_STR71X_UART2) || defined(CONFIG_STR71X_UART3)
# define HAVE_UART 1 # define HAVE_UART 1
/* Is there a serial console? */ /* Is there a serial console? */
@@ -230,7 +232,7 @@
*/ */
#define UART_BAUDDIVISOR (16 * STR71X_UART_BAUD) #define UART_BAUDDIVISOR (16 * STR71X_UART_BAUD)
#define UART_BAUDRATE ((PCLK1 + (UART_BAUDDIVISOR/2) / UART_BAUDDIVISOR) #define UART_BAUDRATE ((PCLK1 + (UART_BAUDDIVISOR/2) / UART_BAUDDIVISOR))
/************************************************************************** /**************************************************************************
* Private Types * Private Types
@@ -266,12 +268,10 @@
void up_lowputc(char ch) void up_lowputc(char ch)
{ {
#if HAVE_CONSOLE #ifdef HAVE_CONSOLE
uint16 reg16;
/* Wait until the TX FIFO is not full */ /* Wait until the TX FIFO is not full */
while (getreg16(STR71X_UART_SR(STR71X_UART_BASE)) & STR71X_UARTSR_TF != 0); while ((getreg16(STR71X_UART_SR(STR71X_UART_BASE)) & STR71X_UARTSR_TF) != 0);
/* Then send the character */ /* Then send the character */
@@ -291,13 +291,13 @@ void up_lowputc(char ch)
void up_lowsetup(void) void up_lowsetup(void)
{ {
#if HAVE_CONSOLE #ifdef HAVE_CONSOLE
uint16 reg16; uint16 reg16;
/* Enable the selected console device */ /* Enable the selected console device */
/* Set the UART baud rate */ /* Set the UART baud rate */
putreg16(UART_BAUDRATE, STR71X_UART_BR(STR71X_UART_BASE)); putreg16((uint16)UART_BAUDRATE, STR71X_UART_BR(STR71X_UART_BASE));
/* Configure the UART control registers */ /* Configure the UART control registers */
@@ -305,8 +305,8 @@ void up_lowsetup(void)
/* Clear FIFOs */ /* Clear FIFOs */
putreg16(0, STR71X_UART2_TXRSTR_(STR71X_UART_BASE)); putreg16(0, STR71X_UART_TXRSTR(STR71X_UART_BASE));
putreg16(0, SSTR71X_UART2_RXRSTR(STR71X_UART_BASE)); putreg16(0, STR71X_UART_RXRSTR(STR71X_UART_BASE));
#endif #endif
/* Configure GPIO0 pins to enable all UARTs in the configuration /* Configure GPIO0 pins to enable all UARTs in the configuration
@@ -315,18 +315,18 @@ void up_lowsetup(void)
#if HAVE_UART #if HAVE_UART
reg16 = getreg16(STR71X_GPIO0_PC0); reg16 = getreg16(STR71X_GPIO0_PC0);
reg16 &= STR71X_GPIO0_MASK; reg16 &= STR71X_UART_GPIO0_MASK;
reg16 |= STR71X_GPIO0_PC0BITS; reg16 |= STR71X_UART_GPIO0_PC0BITS;
putreg16(reg16, STR71X_GPIO0_PC0); putreg16(reg16, STR71X_GPIO0_PC0);
reg16 = getreg16(STR71X_GPIO0_PC1); reg16 = getreg16(STR71X_GPIO0_PC1);
reg16 &= STR71X_GPIO0_MASK; reg16 &= STR71X_UART_GPIO0_MASK;
reg16 |= STR71X_GPIO0_PC1BITS; reg16 |= STR71X_UART_GPIO0_PC1BITS;
putreg16(reg16, STR71X_GPIO0_PC1); putreg16(reg16, STR71X_GPIO0_PC1);
reg16 = getreg16(STR71X_GPIO0_PC2); reg16 = getreg16(STR71X_GPIO0_PC2);
reg16 &= STR71X_GPIO0_MASK; reg16 &= STR71X_UART_GPIO0_MASK;
reg16 |= STR71X_GPIO0_PC2BITS; reg16 |= STR71X_UART_GPIO0_PC2BITS;
putreg16(reg16, STR71X_GPIO0_PC2); putreg16(reg16, STR71X_GPIO0_PC2);
#endif #endif
} }
arch/arm/src/str71x/str71x_pcu.h
+3 -2
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@@ -83,7 +83,7 @@
#define STR71X_PCUPDIVR_APB1DIV2 (0x0001) /* PCLK1 = RCLK / 2 */ #define STR71X_PCUPDIVR_APB1DIV2 (0x0001) /* PCLK1 = RCLK / 2 */
#define STR71X_PCUPDIVR_APB1DIV4 (0x0002) /* PCLK1 = RCLK / 4 */ #define STR71X_PCUPDIVR_APB1DIV4 (0x0002) /* PCLK1 = RCLK / 4 */
#define STR71X_PCUPDIVR_APB1DIV8 (0x0003) /* PCLK1 = RCLK / 8 */ #define STR71X_PCUPDIVR_APB1DIV8 (0x0003) /* PCLK1 = RCLK / 8 */
#define STR71X_PCUPDIVR_FACT1MASK (0x0300) /* Bits 8-9: Division factor for APB2 peripherals */ #define STR71X_PCUPDIVR_FACT2MASK (0x0300) /* Bits 8-9: Division factor for APB2 peripherals */
#define STR71X_PCUPDIVR_APB2DIV1 (0x0000) /* PCLK2 = RCLK */ #define STR71X_PCUPDIVR_APB2DIV1 (0x0000) /* PCLK2 = RCLK */
#define STR71X_PCUPDIVR_APB2DIV2 (0x0100) /* PCLK2 = RCLK / 2 */ #define STR71X_PCUPDIVR_APB2DIV2 (0x0100) /* PCLK2 = RCLK / 2 */
#define STR71X_PCUPDIVR_APB2DIV4 (0x0200) /* PCLK2 = RCLK / 4 */ #define STR71X_PCUPDIVR_APB2DIV4 (0x0200) /* PCLK2 = RCLK / 4 */
@@ -138,8 +138,9 @@
#define STR71X_PCUPWRCR_PWRDWN (0x0040) /* Bit 6: Activate standby mode */ #define STR71X_PCUPWRCR_PWRDWN (0x0040) /* Bit 6: Activate standby mode */
#define STR71X_PCUPWRCR_OSCBYP (0x0080) /* Bit 7: 32KHz oscillator bypass */ #define STR71X_PCUPWRCR_OSCBYP (0x0080) /* Bit 7: 32KHz oscillator bypass */
#define STR71X_PCUPWRCR_LVDDIS (0x0100) /* Bit 8: Low voltage detector disable */ #define STR71X_PCUPWRCR_LVDDIS (0x0100) /* Bit 8: Low voltage detector disable */
#define STR71X_PCUPWRCR_LVDDIS (0x0200) /* Bit 9: FLASH low speed (low power) select */ #define STR71X_PCUPWRCR_FLASHLP (0x0200) /* Bit 9: FLASH low speed (low power) select */
#define STR71X_PCUPWRCR_VROK (0x1000) /* Bit 12: Voltage regulator OK */ #define STR71X_PCUPWRCR_VROK (0x1000) /* Bit 12: Voltage regulator OK */
#define STR71X_PCUPWRCR_WKUPALRM (0x2000) /* Bit 13: Wakeup or alarm active */
#define STR71X_PCUPWRCR_BUSY (0x4000) /* Bit 14: PCU register backup logic busy */ #define STR71X_PCUPWRCR_BUSY (0x4000) /* Bit 14: PCU register backup logic busy */
#define STR71X_PCUPWRCR_WREN (0x8000) /* Bit 15: PCU register write enable */ #define STR71X_PCUPWRCR_WREN (0x8000) /* Bit 15: PCU register write enable */
arch/arm/src/str71x/str71x_prccu.c
+11 -10
View File
@@ -47,6 +47,7 @@
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include "chip.h" #include "chip.h"
#include "up_arch.h"
/******************************************************************************** /********************************************************************************
* Definitions * Definitions
@@ -57,9 +58,9 @@
*/ */
#ifdef STR71X_PLL1_DIV2 #ifdef STR71X_PLL1_DIV2
# define STR71X_PLL1_CLK2 (STR71X_RCCU_MAIN_OSC/2) # define STR71X_PLL1_CLK2 (STR71X_RCCU_MAIN_OSC/2)
#else #else
# define STR71X_RCCU_MAIN_OSC STR71X_RCCU_MAIN_OSC # define STR71X_PLL1_CLK2 STR71X_RCCU_MAIN_OSC
#endif #endif
/* Select set of peripherals to be enabled */ /* Select set of peripherals to be enabled */
@@ -225,7 +226,7 @@
# define PLL1MUL STR71X_RCCUPLL1CR_MUL16 # define PLL1MUL STR71X_RCCUPLL1CR_MUL16
#elif STR71X_PLL1OUT_MUL == 20 #elif STR71X_PLL1OUT_MUL == 20
# define PLL1MUL STR71X_RCCUPLL1CR_MUL20 # define PLL1MUL STR71X_RCCUPLL1CR_MUL20
#else STR71X_PLL1OUT_MUL == 24 #elif STR71X_PLL1OUT_MUL == 24
# define PLL1MUL STR71X_RCCUPLL1CR_MUL24 # define PLL1MUL STR71X_RCCUPLL1CR_MUL24
#else #else
# error "Unsupporetd value for STR71X_PLL1OUT_MUL" # error "Unsupporetd value for STR71X_PLL1OUT_MUL"
@@ -291,7 +292,7 @@
# define PLL2MUL STR71X_PCUPPL2CR_MUL16 # define PLL2MUL STR71X_PCUPPL2CR_MUL16
#elif STR71X_PLL2OUT_MUL == 20 #elif STR71X_PLL2OUT_MUL == 20
# define PLL2MUL STR71X_PCUPPL2CR_MUL20 # define PLL2MUL STR71X_PCUPPL2CR_MUL20
#else STR71X_PLL2OUT_MUL == 28 #elif STR71X_PLL2OUT_MUL == 28
# define PLL2MUL STR71X_PCUPPL2CR_MUL28 # define PLL2MUL STR71X_PCUPPL2CR_MUL28
#else #else
# error "Unsupporetd value for STR71X_PLL2OUT_MUL" # error "Unsupporetd value for STR71X_PLL2OUT_MUL"
@@ -363,7 +364,7 @@ void str71x_prccuinit(void)
reg16 = getreg16(STR71X_PCU_MDIVR); reg16 = getreg16(STR71X_PCU_MDIVR);
reg16 &= ~STR71X_PCUMDIVR_FACTMASK; reg16 &= ~STR71X_PCUMDIVR_FACTMASK;
reg16 |= MCLKDIV; reg16 |= MCLKDIV;
purreg16(reg16 , STR71X_PCU_MDIVR); putreg16(reg16 , STR71X_PCU_MDIVR);
/* Turn off the PLL1 by setting bits DX[2:0] */ /* Turn off the PLL1 by setting bits DX[2:0] */
@@ -382,7 +383,7 @@ void str71x_prccuinit(void)
/* Wait for the PLL to lock */ /* Wait for the PLL to lock */
while (getreg16(STR71X_RCCU_CFR) & STR71X_RCCUCFR_LOCK) == 0); while ((getreg16(STR71X_RCCU_CFR) & STR71X_RCCUCFR_LOCK) == 0);
/* Set the CK2_16 Bit in the CFR to use CLK2/PLL1OUT as CLK3 */ /* Set the CK2_16 Bit in the CFR to use CLK2/PLL1OUT as CLK3 */
@@ -391,14 +392,14 @@ void str71x_prccuinit(void)
/* Wait for the PLL to lock */ /* Wait for the PLL to lock */
while (getreg16(STR71X_RCCU_CFR) & STR71X_RCCUCFR_LOCK) == 0); while ((getreg16(STR71X_RCCU_CFR) & STR71X_RCCUCFR_LOCK) == 0);
/* Select CLK3 (vs the alternative source) for RCLK in the clock /* Select CLK3 (vs the alternative source) for RCLK in the clock
* control register (CCR) * control register (CCR)
*/ */
reg16 = getreg16(STR71X_RCCU_CCR); reg16 = getreg16(STR71X_RCCU_CCR);
reg16 &= ~STR71X_RCCUCCR_CKAFSEL reg16 &= ~STR71X_RCCUCCR_CKAFSEL;
putreg16(reg16, STR71X_RCCU_CCR); putreg16(reg16, STR71X_RCCU_CCR);
/* Select PLL1OUT as the CLK3 */ /* Select PLL1OUT as the CLK3 */
@@ -424,11 +425,11 @@ void str71x_prccuinit(void)
reg16 &= ~STR71X_PCUPPL2CR_FRQRNG; reg16 &= ~STR71X_PCUPPL2CR_FRQRNG;
#else #else
reg16 |= STR71X_PCUPPL2CR_FRQRNG; reg16 |= STR71X_PCUPPL2CR_FRQRNG;
#else #endif
putreg16(reg16, STR71X_PCU_PLL2CR); putreg16(reg16, STR71X_PCU_PLL2CR);
/* Wait for PLL2 to lock in */ /* Wait for PLL2 to lock in */
// while (getreg16(STR71X_PCU_PLL2CR) & STR71X_PCUPPL2CR_LOCK) == 0); // while ((getreg16(STR71X_PCU_PLL2CR) & STR71X_PCUPPL2CR_LOCK) == 0);
#endif #endif
/* Select the USB clock source */ /* Select the USB clock source */
arch/arm/src/str71x/str71x_rccu.h
+1 -1
View File
@@ -110,7 +110,7 @@
#define STR71X_RCCUPLL1CR_DIV7 (0x00000006) /* PLLCK / 7 */ #define STR71X_RCCUPLL1CR_DIV7 (0x00000006) /* PLLCK / 7 */
#define STR71X_RCCUPLL1CR_CLK2 (0x00000007) /* FREEN==0: CLK2 */ #define STR71X_RCCUPLL1CR_CLK2 (0x00000007) /* FREEN==0: CLK2 */
#define STR71X_RCCUPLL1CR_FREERM (0x00000007) /* FREEN==1: PLL1 in free running mode */ #define STR71X_RCCUPLL1CR_FREERM (0x00000007) /* FREEN==1: PLL1 in free running mode */
#define STR71X_RCCUPLL1CR_MXMASK (0x00000030) /* Bit 4-5: #define STR71X_RCCUPLL1CR_MXMASK (0x00000030) /* Bit 4-5: PLL1 clock multiplier */
#define STR71X_RCCUPLL1CR_MUL20 (0x00000000) /* CLK2 * 20 */ #define STR71X_RCCUPLL1CR_MUL20 (0x00000000) /* CLK2 * 20 */
#define STR71X_RCCUPLL1CR_MUL12 (0x00000010) /* CLK2 * 12 */ #define STR71X_RCCUPLL1CR_MUL12 (0x00000010) /* CLK2 * 12 */
#define STR71X_RCCUPLL1CR_MUL24 (0x00000020) /* CLK2 * 24 */ #define STR71X_RCCUPLL1CR_MUL24 (0x00000020) /* CLK2 * 24 */
arch/arm/src/str71x/str71x_uart.h
+5 -5
View File
@@ -133,11 +133,11 @@
#define STR71X_UARTCR_STOPBIT10 (0x0008) /* 1.0 stop bit */ #define STR71X_UARTCR_STOPBIT10 (0x0008) /* 1.0 stop bit */
#define STR71X_UARTCR_STOPBIT15 (0x0010) /* 1.5 stop bits */ #define STR71X_UARTCR_STOPBIT15 (0x0010) /* 1.5 stop bits */
#define STR71X_UARTCR_STOPBIT20 (0x0018) /* 2.0 stop bits */ #define STR71X_UARTCR_STOPBIT20 (0x0018) /* 2.0 stop bits */
#define STR71X_UARTCR_PARITYODD (0x0020) /* Bit 5: #define STR71X_UARTCR_PARITYODD (0x0020) /* Bit 5: Parity selection */
#define STR71X_UARTCR_LOOPBACK (0x0040) /* Bit 6: #define STR71X_UARTCR_LOOPBACK (0x0040) /* Bit 6: Loopback mode enable */
#define STR71X_UARTCR_RUN (0x0080) /* Bit 7: #define STR71X_UARTCR_RUN (0x0080) /* Bit 7: Baudrate generator run bit */
#define STR71X_UARTCR_RXENABLE (0x0100) /* Bit 8: #define STR71X_UARTCR_RXENABLE (0x0100) /* Bit 8: Receiver enable */
#define STR71X_UARTCR_SCENABLE (0x0200) /* Bit 9: #define STR71X_UARTCR_SCENABLE (0x0200) /* Bit 9: SmartCard mode enable */
#define STR71X_UARTCR_FIFOENABLE (0x0400) /* Bit 10: FIFO enable */ #define STR71X_UARTCR_FIFOENABLE (0x0400) /* Bit 10: FIFO enable */
/* UART interrupt enable (IER) register */ /* UART interrupt enable (IER) register */
arch/arm/src/str71x/str71x_wdog.h
+3 -3
View File
@@ -33,8 +33,8 @@
* *
************************************************************************************/ ************************************************************************************/
#ifndef #define __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H #ifndef __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H
#define #define __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H #define __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H
/************************************************************************************ /************************************************************************************
* Included Files * Included Files
@@ -72,4 +72,4 @@
* Public Functions * Public Functions
************************************************************************************/ ************************************************************************************/
#endif /* #define __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H */ #endif /* __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H */